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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.464095 # Number of seconds simulated
sim_ticks 464094642500 # Number of ticks simulated
final_tick 464094642500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 178110 # Simulator instruction rate (inst/s)
host_op_rate 198694 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 53516537 # Simulator tick rate (ticks/s)
host_mem_usage 227392 # Number of bytes of host memory used
host_seconds 8671.99 # Real time elapsed on the host
sim_insts 1544563041 # Number of instructions simulated
sim_ops 1723073854 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 189817088 # Number of bytes read from this memory
system.physmem.bytes_inst_read 48640 # Number of instructions bytes read from this memory
system.physmem.bytes_written 78237376 # Number of bytes written to this memory
system.physmem.num_reads 2965892 # Number of read requests responded to by this memory
system.physmem.num_writes 1222459 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 409005127 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 104806 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 168580649 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 577585776 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 928189286 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 300558884 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 246363041 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 16110008 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 171748174 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 156362542 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 18325675 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 390 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 292832773 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2158671516 # Number of instructions fetch has processed
system.cpu.fetch.Branches 300558884 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 174688217 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 429285540 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 83802150 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 129138530 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 322 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 283809493 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 5370008 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 918527985 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.613925 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.238783 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 489242491 53.26% 53.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 23031671 2.51% 55.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 38788083 4.22% 59.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 47826065 5.21% 65.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 40763412 4.44% 69.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 46954546 5.11% 74.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 39099426 4.26% 79.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 18124481 1.97% 80.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 174697810 19.02% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 918527985 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.323812 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.325680 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 322137890 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 109173401 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 403303983 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 16642613 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 67270098 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 46182318 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 747 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 2347171741 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 2550 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 67270098 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 343773810 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 50758192 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 21988 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 397138305 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 59565592 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2290275122 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 23158 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 4666704 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 46265569 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 2 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 2264842596 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 10571584644 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 10571581459 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 3185 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1706319959 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 558522637 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 5679 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 5674 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 136915079 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 624891325 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 218844969 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 86018221 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 66187056 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2190772661 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 1712 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2016120341 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 4885308 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 463006686 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1075673735 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1208 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 918527985 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.194947 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.923224 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 251260735 27.35% 27.35% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 138867546 15.12% 42.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 158222967 17.23% 59.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 116427032 12.68% 72.37% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 125736326 13.69% 86.06% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 75508875 8.22% 94.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 39162431 4.26% 98.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 10675084 1.16% 99.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 2666989 0.29% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 918527985 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 822239 3.28% 3.28% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 4824 0.02% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 19001190 75.81% 79.11% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 5234373 20.89% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1234297815 61.22% 61.22% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 931066 0.05% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 50 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 9 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 587044073 29.12% 90.39% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 193847304 9.61% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 2016120341 # Type of FU issued
system.cpu.iq.rate 2.172100 # Inst issue rate
system.cpu.iq.fu_busy_cnt 25062626 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.012431 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 4980716257 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2653967070 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1958162011 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 344 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 554 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 132 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2041182792 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 175 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 63608263 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 138964553 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 284704 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 189296 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 43997922 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 451252 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 67270098 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 23165985 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1316827 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2190782552 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 5581738 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 624891325 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 218844969 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1648 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 207697 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 50017 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 189296 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 8647984 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 10198062 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 18846046 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1986617242 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 572452659 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 29503099 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 8179 # number of nop insts executed
system.cpu.iew.exec_refs 763318356 # number of memory reference insts executed
system.cpu.iew.exec_branches 238198091 # Number of branches executed
system.cpu.iew.exec_stores 190865697 # Number of stores executed
system.cpu.iew.exec_rate 2.140315 # Inst execution rate
system.cpu.iew.wb_sent 1967150761 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1958162143 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1296167059 # num instructions producing a value
system.cpu.iew.wb_consumers 2068734310 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 2.109658 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.626551 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 1544563059 # The number of committed instructions
system.cpu.commit.commitCommittedOps 1723073872 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 467775476 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 504 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 16109498 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 851257888 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.024150 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.756084 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 363004636 42.64% 42.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 192697561 22.64% 65.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 73553862 8.64% 73.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 35091204 4.12% 78.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 18733793 2.20% 80.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 30684966 3.60% 83.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 19668934 2.31% 86.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 10962087 1.29% 87.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 106860845 12.55% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 851257888 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1544563059 # Number of instructions committed
system.cpu.commit.committedOps 1723073872 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 660773819 # Number of memory references committed
system.cpu.commit.loads 485926772 # Number of loads committed
system.cpu.commit.membars 62 # Number of memory barriers committed
system.cpu.commit.branches 213462366 # Number of branches committed
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1536941857 # Number of committed integer instructions.
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
system.cpu.commit.bw_lim_events 106860845 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 2935245792 # The number of ROB reads
system.cpu.rob.rob_writes 4449143808 # The number of ROB writes
system.cpu.timesIdled 899784 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 9661301 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1544563041 # Number of Instructions Simulated
system.cpu.committedOps 1723073854 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1544563041 # Number of Instructions Simulated
system.cpu.cpi 0.600940 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.600940 # CPI: Total CPI of All Threads
system.cpu.ipc 1.664060 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.664060 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 9952061686 # number of integer regfile reads
system.cpu.int_regfile_writes 1938314522 # number of integer regfile writes
system.cpu.fp_regfile_reads 132 # number of floating regfile reads
system.cpu.fp_regfile_writes 135 # number of floating regfile writes
system.cpu.misc_regfile_reads 2898335768 # number of misc regfile reads
system.cpu.misc_regfile_writes 128 # number of misc regfile writes
system.cpu.icache.replacements 24 # number of replacements
system.cpu.icache.tagsinuse 636.409684 # Cycle average of tags in use
system.cpu.icache.total_refs 283808312 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 793 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 357891.944515 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 636.409684 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.310747 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.310747 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 283808312 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 283808312 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 283808312 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 283808312 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 283808312 # number of overall hits
system.cpu.icache.overall_hits::total 283808312 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1181 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1181 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1181 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1181 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1181 # number of overall misses
system.cpu.icache.overall_misses::total 1181 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 39284000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 39284000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 39284000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 39284000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 39284000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 39284000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 283809493 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 283809493 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 283809493 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 283809493 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 283809493 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 283809493 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33263.336156 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 33263.336156 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 33263.336156 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 388 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 388 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 388 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 388 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 388 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 388 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 793 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 793 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 793 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 793 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 793 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 793 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27229500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 27229500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27229500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 27229500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27229500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 27229500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34337.326608 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34337.326608 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34337.326608 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9619385 # number of replacements
system.cpu.dcache.tagsinuse 4087.714803 # Cycle average of tags in use
system.cpu.dcache.total_refs 660788859 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9623481 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 68.664224 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 3348066000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4087.714803 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.997977 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.997977 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 493410063 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 493410063 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 167378645 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 167378645 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 88 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 88 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 63 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 63 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 660788708 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 660788708 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 660788708 # number of overall hits
system.cpu.dcache.overall_hits::total 660788708 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 10697227 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 10697227 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5207402 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5207402 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 15904629 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 15904629 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 15904629 # number of overall misses
system.cpu.dcache.overall_misses::total 15904629 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 189148262000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 189148262000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 129349741794 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 129349741794 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 113500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 113500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 318498003794 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 318498003794 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 318498003794 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 318498003794 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 504107290 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 504107290 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 91 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 91 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 63 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 63 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 676693337 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 676693337 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 676693337 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 676693337 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021220 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030173 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.032967 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.023503 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.023503 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17681.990108 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24839.592141 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37833.333333 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20025.490931 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20025.490931 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 271743722 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 161500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 91838 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2958.946427 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 20187.500000 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 3133740 # number of writebacks
system.cpu.dcache.writebacks::total 3133740 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2967640 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 2967640 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3313508 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3313508 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 6281148 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 6281148 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 6281148 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 6281148 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7729587 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7729587 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893894 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1893894 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9623481 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9623481 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9623481 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9623481 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 93074627500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 93074627500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 45380366039 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 45380366039 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138454993539 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 138454993539 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138454993539 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 138454993539 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015333 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014221 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014221 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12041.345482 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23961.407576 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14387.204956 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14387.204956 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2953454 # number of replacements
system.cpu.l2cache.tagsinuse 26874.371014 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7878176 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2980778 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.642993 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 100977467500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 10760.004135 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 11.346810 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 16103.020070 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.328369 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.000346 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.491425 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.820141 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 29 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 5680110 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 5680139 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 3133740 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 3133740 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 978232 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 978232 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 29 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 6658342 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 6658371 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 29 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 6658342 # number of overall hits
system.cpu.l2cache.overall_hits::total 6658371 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 764 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 2049477 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 2050241 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 915662 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 915662 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 764 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2965139 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 2965903 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 764 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2965139 # number of overall misses
system.cpu.l2cache.overall_misses::total 2965903 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26208000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70354429500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 70380637500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 31766495000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 31766495000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 26208000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 102120924500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 102147132500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 26208000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 102120924500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 102147132500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 793 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 7729587 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 7730380 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 3133740 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 3133740 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893894 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1893894 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 793 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9623481 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9624274 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 793 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9623481 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9624274 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963430 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.265147 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.483481 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963430 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.308115 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963430 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.308115 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34303.664921 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34327.991727 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34692.381031 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34303.664921 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34440.518471 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34303.664921 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34440.518471 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 58178500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 6799 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8556.920135 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1222459 # number of writebacks
system.cpu.l2cache.writebacks::total 1222459 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 760 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2049470 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 2050230 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 915662 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 915662 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 760 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2965132 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 2965892 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 760 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2965132 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 2965892 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23680000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 63915816500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63939496500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 28922990000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 28922990000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23680000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92838806500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 92862486500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23680000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92838806500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 92862486500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958386 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.265146 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.483481 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958386 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308114 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958386 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308114 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31157.894737 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31186.509927 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31586.972049 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31157.894737 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31310.176579 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31157.894737 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31310.176579 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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