blob: 77908b2aa4d57aa55fe08e3c1b9ef40a523f2cfd (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
|
---------- Begin Simulation Statistics ----------
sim_seconds 2.391205 # Number of seconds simulated
sim_ticks 2391205115000 # Number of ticks simulated
final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1176543 # Simulator instruction rate (inst/s)
host_op_rate 1313033 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1828326739 # Simulator tick rate (ticks/s)
host_mem_usage 268744 # Number of bytes of host memory used
host_seconds 1307.87 # Real time elapsed on the host
sim_insts 1538759601 # Number of instructions simulated
sim_ops 1717270334 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 125322112 # Number of bytes read from this memory
system.physmem.bytes_read::total 125361536 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 65100672 # Number of bytes written to this memory
system.physmem.bytes_written::total 65100672 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1958158 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1958774 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1017198 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1017198 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 16487 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 52409604 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 52426091 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 16487 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 16487 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 27225047 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 27225047 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 27225047 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 16487 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 52409604 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 79651138 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 79651138 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 1177898 # Transaction distribution
system.membus.trans_dist::ReadResp 1177898 # Transaction distribution
system.membus.trans_dist::Writeback 1017198 # Transaction distribution
system.membus.trans_dist::ReadExReq 780876 # Transaction distribution
system.membus.trans_dist::ReadExResp 780876 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4934746 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4934746 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 190462208 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 11113556000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
system.membus.respLayer1.occupancy 17628966000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 4782410230 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1538759601 # Number of instructions committed
system.cpu.committedOps 1717270334 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1536941842 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
system.cpu.num_func_calls 27330256 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls
system.cpu.num_int_insts 1536941842 # number of integer instructions
system.cpu.num_fp_insts 36 # number of float instructions
system.cpu.num_int_register_reads 9304895467 # number of times the integer registers were read
system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written
system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu.num_mem_refs 660773815 # number of memory refs
system.cpu.num_load_insts 485926769 # Number of load instructions
system.cpu.num_store_insts 174847046 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 4782410230 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 213462426 # Number of branches fetched
system.cpu.icache.tags.replacements 7 # number of replacements
system.cpu.icache.tags.tagsinuse 514.976015 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 2420948.200627 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 514.976015 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.251453 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.251453 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 606 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 3089131818 # Number of tag accesses
system.cpu.icache.tags.data_accesses 3089131818 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1544564952 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1544564952 # number of overall hits
system.cpu.icache.overall_hits::total 1544564952 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses
system.cpu.icache.overall_misses::total 638 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 34233000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 34233000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 34233000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 34233000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 34233000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 34233000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1544565590 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1544565590 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1544565590 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53656.739812 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 53656.739812 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53656.739812 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 53656.739812 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53656.739812 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 53656.739812 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32957000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 32957000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32957000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 32957000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32957000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 32957000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51656.739812 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51656.739812 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 1926075 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30987.094489 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 154026636000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 15648.493745 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 24.153175 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 15314.447570 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.477554 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000737 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.467360 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.945651 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1082 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1693 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26880 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 106351328 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 106351328 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 6048805 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 6048827 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 3697418 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 3697418 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1108273 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1108273 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 7157078 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 7157100 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 7157078 # number of overall hits
system.cpu.l2cache.overall_hits::total 7157100 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 1177282 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1177898 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 780876 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 780876 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1958158 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 1958774 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1958158 # number of overall misses
system.cpu.l2cache.overall_misses::total 1958774 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32099000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61225555000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 61257654000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40608829000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 40608829000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 32099000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 101834384000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 101866483000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 32099000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 101834384000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 101866483000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 3697418 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 3697418 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9115236 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9115874 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162921 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.162992 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413348 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.413348 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.214823 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.214875 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.214823 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.214875 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52108.766234 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52005.853313 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52005.907133 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.196569 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.196569 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52108.766234 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52005.192635 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52005.225207 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52108.766234 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52005.192635 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52005.225207 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1017198 # number of writebacks
system.cpu.l2cache.writebacks::total 1017198 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177282 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1177898 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 780876 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 780876 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1958158 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1958774 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1958158 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1958774 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24707000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47098171000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47122878000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31238317000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31238317000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24707000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336488000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 78361195000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24707000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336488000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 78361195000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.162992 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413348 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413348 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.214875 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.214875 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40108.766234 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.853313 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.907133 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.196569 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40004.196569 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40108.766234 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40108.766234 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 9111140 # number of replacements
system.cpu.dcache.tags.tagsinuse 4083.522356 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 645855059 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 70.854453 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.996954 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1214 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2578 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 146 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1319055826 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1319055826 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 645854937 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 645854937 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 645854937 # number of overall hits
system.cpu.dcache.overall_hits::total 645854937 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7226087 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7226087 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 9115236 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
system.cpu.dcache.overall_misses::total 9115236 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 143391866000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 143391866000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359006000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 57359006000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 200750872000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 200750872000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 200750872000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 200750872000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 482384126 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 482384126 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 654970173 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 654970173 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 654970173 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 654970173 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014980 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.014980 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.639580 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.639580 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.351514 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.351514 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22023.661483 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22023.661483 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks
system.cpu.dcache.writebacks::total 3697418 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9115236 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128939692000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 128939692000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580708000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580708000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182520400000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 182520400000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182520400000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 182520400000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.639580 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.639580 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.351514 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.351514 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 342944519 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21927890 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 21929166 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820009856 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 820050688 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
---------- End Simulation Statistics ----------
|
