blob: c9d66243af2ea5dc5aa990c3b9f074e5c137e70f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
|
---------- Begin Simulation Statistics ----------
sim_seconds 2.408512 # Number of seconds simulated
sim_ticks 2408512388000 # Number of ticks simulated
final_tick 2408512388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1431405 # Simulator instruction rate (inst/s)
host_op_rate 1597462 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2240478292 # Simulator tick rate (ticks/s)
host_mem_usage 233776 # Number of bytes of host memory used
host_seconds 1075.00 # Real time elapsed on the host
sim_insts 1538759601 # Number of instructions simulated
sim_ops 1717270334 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 137819840 # Number of bytes read from this memory
system.physmem.bytes_read::total 137859264 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 67221184 # Number of bytes written to this memory
system.physmem.bytes_written::total 67221184 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2153435 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2154051 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1050331 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1050331 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 16369 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 57221977 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 57238345 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 16369 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 16369 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 27909835 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 27909835 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 27909835 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 16369 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 57221977 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 85148181 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 4817024776 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1538759601 # Number of instructions committed
system.cpu.committedOps 1717270334 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1536941842 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
system.cpu.num_func_calls 27330256 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 177498327 # number of instructions that are conditional controls
system.cpu.num_int_insts 1536941842 # number of integer instructions
system.cpu.num_fp_insts 36 # number of float instructions
system.cpu.num_int_register_reads 9304894672 # number of times the integer registers were read
system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written
system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu.num_mem_refs 660773815 # number of memory refs
system.cpu.num_load_insts 485926769 # Number of load instructions
system.cpu.num_store_insts 174847046 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 4817024776 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 7 # number of replacements
system.cpu.icache.tagsinuse 515.022606 # Cycle average of tags in use
system.cpu.icache.total_refs 1544564952 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 2420948.200627 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 515.022606 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.251476 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.251476 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1544564952 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1544564952 # number of overall hits
system.cpu.icache.overall_hits::total 1544564952 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses
system.cpu.icache.overall_misses::total 638 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 34804000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 34804000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 34804000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 34804000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 34804000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 34804000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1544565590 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1544565590 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1544565590 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54551.724138 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54551.724138 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54551.724138 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 54551.724138 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54551.724138 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54551.724138 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32890000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 32890000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32890000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 32890000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32890000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 32890000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51551.724138 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51551.724138 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51551.724138 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 51551.724138 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51551.724138 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 51551.724138 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9111140 # number of replacements
system.cpu.dcache.tagsinuse 4083.603265 # Cycle average of tags in use
system.cpu.dcache.total_refs 645855059 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 25922973000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4083.603265 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.996973 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.996973 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 645854937 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 645854937 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 645854937 # number of overall hits
system.cpu.dcache.overall_hits::total 645854937 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7226087 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7226087 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 9115236 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
system.cpu.dcache.overall_misses::total 9115236 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 158470312000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 158470312000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 59587262000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 59587262000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 218057574000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 218057574000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 218057574000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 218057574000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 482384126 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 482384126 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 654970173 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 654970173 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 654970173 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 654970173 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014980 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.014980 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21930.307786 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 21930.307786 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31541.854031 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31541.854031 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23922.317974 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23922.317974 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23922.317974 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 23922.317974 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 3385547 # number of writebacks
system.cpu.dcache.writebacks::total 3385547 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9115236 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 136792051000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 136792051000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53919815000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 53919815000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 190711866000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 190711866000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 190711866000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 190711866000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18930.307786 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18930.307786 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28541.854031 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28541.854031 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20922.317974 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20922.317974 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20922.317974 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20922.317974 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2138446 # number of replacements
system.cpu.l2cache.tagsinuse 30628.680390 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8443619 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2168151 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 3.894387 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 437045285000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 14782.399882 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 15.716042 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 15830.564466 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.451123 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.000480 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.483110 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.934713 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 5861680 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 5861702 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 3385547 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 3385547 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1100121 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1100121 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 6961801 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 6961823 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 6961801 # number of overall hits
system.cpu.l2cache.overall_hits::total 6961823 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 1364407 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1365023 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 789028 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 789028 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2153435 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 2154051 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2153435 # number of overall misses
system.cpu.l2cache.overall_misses::total 2154051 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32032000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70949164000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 70981196000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41029456000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 41029456000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 32032000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 111978620000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 112010652000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 32032000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 111978620000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 112010652000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 3385547 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 3385547 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9115236 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9115874 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188817 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.188885 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.417663 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.417663 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.236246 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.236297 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.236246 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.236297 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1050331 # number of writebacks
system.cpu.l2cache.writebacks::total 1050331 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1364407 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1365023 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 789028 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 789028 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2153435 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 2154051 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2153435 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 2154051 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24640000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54576280000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54600920000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31561120000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31561120000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24640000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86137400000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 86162040000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24640000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86137400000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 86162040000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188817 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188885 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417663 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417663 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.236246 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.236297 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.236246 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.236297 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|