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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.041622 # Number of seconds simulated
sim_ticks 41622221000 # Number of ticks simulated
final_tick 41622221000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 47594 # Simulator instruction rate (inst/s)
host_op_rate 47594 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 21554846 # Simulator tick rate (ticks/s)
host_mem_usage 275256 # Number of bytes of host memory used
host_seconds 1930.99 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory
system.physmem.bytes_read::total 316032 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 178816 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 178816 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 4296167 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3296701 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 7592867 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 4296167 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 4296167 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 4296167 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3296701 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7592867 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 4938 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 4938 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 316032 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 316032 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 311 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 344 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 302 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 293 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 259 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 224 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 279 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 294 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 290 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 273 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 301 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 345 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 351 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 357 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 333 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 382 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 41622168000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 4938 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 3236 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1195 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 440 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.totQLat 23362750 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 122110250 # Sum of mem lat for all requests
system.physmem.totBusLat 24690000 # Total cycles spent in databus access
system.physmem.totBankLat 74057500 # Total cycles spent in bank access
system.physmem.avgQLat 4731.22 # Average queueing delay per request
system.physmem.avgBankLat 14997.47 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 24728.69 # Average memory access latency
system.physmem.avgRdBW 7.59 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 7.59 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.06 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 4243 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 85.93 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 8428952.61 # Average gap between requests
system.cpu.branchPred.lookups 13412628 # Number of BP lookups
system.cpu.branchPred.condPredicted 9650145 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 4269214 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 7424480 # Number of BTB lookups
system.cpu.branchPred.BTBHits 3768497 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 50.757723 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1029619 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 126 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 19996247 # DTB read hits
system.cpu.dtb.read_misses 10 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 19996257 # DTB read accesses
system.cpu.dtb.write_hits 6501860 # DTB write hits
system.cpu.dtb.write_misses 23 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 6501883 # DTB write accesses
system.cpu.dtb.data_hits 26498107 # DTB hits
system.cpu.dtb.data_misses 33 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 26498140 # DTB accesses
system.cpu.itb.fetch_hits 9956943 # ITB hits
system.cpu.itb.fetch_misses 49 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 9956992 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
system.cpu.numCycles 83244443 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken 5905664 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 7506964 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 73570548 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 136146020 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 2206128 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 8058016 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 38521871 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 26722393 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 799060 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 4268356 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 5972346 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 41.680307 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 57404029 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 82970150 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 10684 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 7636716 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 75607727 # Number of cycles cpu stages are processed.
system.cpu.activity 90.826155 # Percentage of cycles cpu is active
system.cpu.comLoads 19996198 # Number of Load instructions committed
system.cpu.comStores 6501103 # Number of Store instructions committed
system.cpu.comBranches 10240685 # Number of Branches instructions committed
system.cpu.comNops 7723346 # Number of Nop instructions committed
system.cpu.comNonSpec 389 # Number of Non-Speculative instructions committed
system.cpu.comInts 43665352 # Number of Integer instructions committed
system.cpu.comFloats 3775974 # Number of Floating Point instructions committed
system.cpu.committedInsts 91903056 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total)
system.cpu.cpi 0.905785 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 0.905785 # CPI: Total CPI of All Threads
system.cpu.ipc 1.104014 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 1.104014 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 27564085 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 55680358 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 66.887778 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 33992749 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 49251694 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 59.165143 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 33393108 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 49851335 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 59.885481 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 65217942 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 18026501 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 21.654900 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 29384710 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 53859733 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 64.700695 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 7635 # number of replacements
system.cpu.icache.tagsinuse 1492.649281 # Cycle average of tags in use
system.cpu.icache.total_refs 9945578 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 9520 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1044.703571 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1492.649281 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.728833 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.728833 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 9945578 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 9945578 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 9945578 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 9945578 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::total 9945578 # number of overall hits
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system.cpu.icache.ReadReq_misses::total 11365 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 11365 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 11365 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 11365 # number of overall misses
system.cpu.icache.overall_misses::total 11365 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 259163500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 259163500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 259163500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 259163500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 259163500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 259163500 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::total 9956943 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::total 9956943 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::total 9956943 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.001141 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::total 0.001141 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::total 0.001141 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22803.651562 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 22803.651562 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22803.651562 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 22803.651562 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22803.651562 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 22803.651562 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.demand_mshr_hits::total 1845 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 1845 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 1845 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9520 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 9520 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 9520 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::total 209587500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 209587500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 209587500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 209587500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 209587500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22015.493697 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22015.493697 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22015.493697 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 22015.493697 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22015.493697 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 22015.493697 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.tagsinuse 2190.263303 # Cycle average of tags in use
system.cpu.l2cache.total_refs 6793 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.069775 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 17.839003 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1821.325102 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 351.099198 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_percent::cpu.inst 0.055582 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.010715 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.066842 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::total 6779 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits
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system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.overall_accesses::total 11743 # number of overall (read+write) accesses
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system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses
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system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35008.919470 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38237.774720 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36410.836371 # average overall mshr miss latency
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system.cpu.dcache.tagsinuse 1441.801421 # Cycle average of tags in use
system.cpu.dcache.total_refs 26488625 # Total number of references to valid blocks.
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system.cpu.dcache.occ_blocks::cpu.data 1441.801421 # Average occupied blocks per requestor
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system.cpu.dcache.overall_misses::total 8676 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::total 31369500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000029 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001246 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001246 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000327 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000327 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000327 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54555.652174 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 54555.652174 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42716.763363 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 42716.763363 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 43501.383126 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 43501.383126 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 43501.383126 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 43501.383126 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 13712 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 822 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.681265 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
system.cpu.dcache.writebacks::total 107 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 100 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6353 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 6353 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 6453 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 6453 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 6453 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 6453 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25078500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 25078500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86165500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 86165500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 111244000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 111244000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 111244000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 111244000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52796.842105 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52796.842105 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49293.764302 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49293.764302 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50042.285200 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 50042.285200 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50042.285200 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 50042.285200 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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