path: root/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.023661                       # Number of seconds simulated
sim_ticks                                 23661066000                       # Number of ticks simulated
final_tick                                23661066000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 163409                       # Simulator instruction rate (inst/s)
host_op_rate                                   163409                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               45930776                       # Simulator tick rate (ticks/s)
host_mem_usage                                 223740                       # Number of bytes of host memory used
host_seconds                                   515.15                       # Real time elapsed on the host
sim_insts                                    84179709                       # Number of instructions simulated
sim_ops                                      84179709                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            197312                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            138432                       # Number of bytes read from this memory
system.physmem.bytes_read::total               335744                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       197312                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          197312                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst               3083                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               2163                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                  5246                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst              8339100                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              5850624                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                14189724                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         8339100                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            8339100                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             8339100                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             5850624                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               14189724                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                     23226472                       # DTB read hits
system.cpu.dtb.read_misses                     199471                       # DTB read misses
system.cpu.dtb.read_acv                             2                       # DTB read access violations
system.cpu.dtb.read_accesses                 23425943                       # DTB read accesses
system.cpu.dtb.write_hits                     7079215                       # DTB write hits
system.cpu.dtb.write_misses                      1341                       # DTB write misses
system.cpu.dtb.write_acv                            3                       # DTB write access violations
system.cpu.dtb.write_accesses                 7080556                       # DTB write accesses
system.cpu.dtb.data_hits                     30305687                       # DTB hits
system.cpu.dtb.data_misses                     200812                       # DTB misses
system.cpu.dtb.data_acv                             5                       # DTB access violations
system.cpu.dtb.data_accesses                 30506499                       # DTB accesses
system.cpu.itb.fetch_hits                    14950241                       # ITB hits
system.cpu.itb.fetch_misses                       107                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses                14950348                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                  389                       # Number of system calls
system.cpu.numCycles                         47322133                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                 15026940                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted           10894124                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect             964629                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups               8768677                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                  7072325                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                  1489344                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect                3225                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles           15650036                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      128237375                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    15026940                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            8561669                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      22385381                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 4637420                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles                5548184                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                   49                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles          2165                       # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines                  14950241                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                337394                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           47225069                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.715451                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.372476                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 24839688     52.60%     52.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  2391446      5.06%     57.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1209126      2.56%     60.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  1776446      3.76%     63.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2802962      5.94%     69.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1171165      2.48%     72.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1227887      2.60%     75.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                   787448      1.67%     76.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 11018901     23.33%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             47225069                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.317546                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        2.709882                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 17490874                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles               4250840                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  20765641                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               1090220                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                3627494                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              2542741                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 12176                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              125152088                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                 32110                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                3627494                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 18655906                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                  966254                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles           8182                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  20668416                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               3298817                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              122169743                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                     4                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 401900                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               2424267                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands            89702215                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             158657740                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        148914395                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups           9743345                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              68427361                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 21274854                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               1091                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           1100                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                   8739612                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             25558040                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores             8300974                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           2604808                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores           921406                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  106164029                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                2236                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                  96990974                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            187003                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        21520200                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     16153199                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           1847                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      47225069                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.053803                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.875376                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            12469931     26.41%     26.41% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1             9437048     19.98%     46.39% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             8469534     17.93%     64.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             6320288     13.38%     77.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             4943441     10.47%     88.17% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             2849790      6.03%     94.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             1723941      3.65%     97.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              801134      1.70%     99.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              209962      0.44%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        47225069                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  187127     11.94%     11.94% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     11.94% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.94% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                   172      0.01%     11.95% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.95% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                  7127      0.45%     12.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                 5609      0.36%     12.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                843370     53.79%     66.55% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     66.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     66.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     66.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     66.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     66.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     66.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     66.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     66.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     66.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     66.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     66.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     66.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     66.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     66.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     66.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     66.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     66.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     66.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     66.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     66.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     66.55% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 445220     28.40%     94.95% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                 79228      5.05%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 7      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              58991306     60.82%     60.82% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               480706      0.50%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd             2802495      2.89%     64.21% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp              115483      0.12%     64.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt             2386219      2.46%     66.79% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult             311493      0.32%     67.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv              759735      0.78%     67.89% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                319      0.00%     67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.89% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             23972181     24.72%     92.61% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             7171030      7.39%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               96990974                       # Type of FU issued
system.cpu.iq.rate                           2.049590                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     1567853                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.016165                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          227829224                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         118898019                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     87368354                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads            15132649                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes            8823096                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses      7068677                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses               90563080                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                 7995740                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1518780                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      5561842                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        19579                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        34790                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1799871                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        10514                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked             5                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                3627494                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                  132338                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                 17118                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           116467170                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            392102                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              25558040                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts              8300974                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               2236                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                   2929                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                    49                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          34790                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         570155                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       508194                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1078349                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts              95694648                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              23426609                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1296326                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                      10300905                       # number of nop insts executed
system.cpu.iew.exec_refs                     30507339                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 12077728                       # Number of branches executed
system.cpu.iew.exec_stores                    7080730                       # Number of stores executed
system.cpu.iew.exec_rate                     2.022196                       # Inst execution rate
system.cpu.iew.wb_sent                       94980194                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      94437031                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  64621172                       # num instructions producing a value
system.cpu.iew.wb_consumers                  90003030                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.995621                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.717989                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts       91903055                       # The number of committed instructions
system.cpu.commit.commitCommittedOps         91903055                       # The number of committed instructions
system.cpu.commit.commitSquashedInsts        24565165                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls             389                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            952869                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     43597575                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.107985                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.734489                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     17052737     39.11%     39.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1      9973933     22.88%     61.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4509329     10.34%     72.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2295130      5.26%     77.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1618190      3.71%     81.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1123694      2.58%     83.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       722585      1.66%     85.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       817482      1.88%     87.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      5484495     12.58%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     43597575                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             91903055                       # Number of instructions committed
system.cpu.commit.committedOps               91903055                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       26497301                       # Number of memory references committed
system.cpu.commit.loads                      19996198                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                   10240685                       # Number of branches committed
system.cpu.commit.fp_insts                    6862061                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  79581076                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1029620                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               5484495                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    154580260                       # The number of ROB reads
system.cpu.rob.rob_writes                   236588154                       # The number of ROB writes
system.cpu.timesIdled                            2240                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           97064                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                    84179709                       # Number of Instructions Simulated
system.cpu.committedOps                      84179709                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total              84179709                       # Number of Instructions Simulated
system.cpu.cpi                               0.562156                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.562156                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.778865                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.778865                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                129472042                       # number of integer regfile reads
system.cpu.int_regfile_writes                70778136                       # number of integer regfile writes
system.cpu.fp_regfile_reads                   6192217                       # number of floating regfile reads
system.cpu.fp_regfile_writes                  6050128                       # number of floating regfile writes
system.cpu.misc_regfile_reads                  714420                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.icache.replacements                  10236                       # number of replacements
system.cpu.icache.tagsinuse               1604.355346                       # Cycle average of tags in use
system.cpu.icache.total_refs                 14936697                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                  12175                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                1226.833429                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst    1604.355346                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.783377                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.783377                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     14936697                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        14936697                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      14936697                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         14936697                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     14936697                       # number of overall hits
system.cpu.icache.overall_hits::total        14936697                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        13544                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         13544                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        13544                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          13544                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        13544                       # number of overall misses
system.cpu.icache.overall_misses::total         13544                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    214516500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    214516500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    214516500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    214516500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    214516500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    214516500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     14950241                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     14950241                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     14950241                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     14950241                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     14950241                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     14950241                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000906                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000906                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000906                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000906                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000906                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000906                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15838.489368                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 15838.489368                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 15838.489368                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 15838.489368                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 15838.489368                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 15838.489368                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1369                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         1369                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         1369                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         1369                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         1369                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         1369                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        12175                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        12175                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        12175                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        12175                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        12175                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        12175                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    142455000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    142455000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    142455000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    142455000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    142455000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    142455000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000814                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000814                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000814                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000814                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000814                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000814                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11700.616016                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11700.616016                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11700.616016                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11700.616016                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11700.616016                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11700.616016                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                    158                       # number of replacements
system.cpu.dcache.tagsinuse               1456.192464                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 28189208                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                   2243                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs               12567.636202                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    1456.192464                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.355516                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.355516                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     21695723                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        21695723                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      6493020                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        6493020                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data          465                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total          465                       # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data      28188743                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         28188743                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     28188743                       # number of overall hits
system.cpu.dcache.overall_hits::total        28188743                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data          984                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total           984                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data         8083                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total         8083                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data         9067                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total           9067                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data         9067                       # number of overall misses
system.cpu.dcache.overall_misses::total          9067                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data     32711000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total     32711000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data    344620000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total    344620000                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        45000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total        45000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data    377331000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total    377331000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data    377331000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total    377331000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     21696707                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     21696707                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data          466                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total          466                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     28197810                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     28197810                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     28197810                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     28197810                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000045                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000045                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001243                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.001243                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002146                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002146                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.000322                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.000322                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.000322                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.000322                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33242.886179                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 33242.886179                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42635.160213                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 42635.160213                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        45000                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        45000                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 41615.859711                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 41615.859711                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 41615.859711                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 41615.859711                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        12500                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 1                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs        12500                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks          108                       # number of writebacks
system.cpu.dcache.writebacks::total               108                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data          474                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total          474                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6351                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total         6351                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data         6825                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total         6825                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data         6825                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total         6825                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data          510                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total          510                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1732                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         1732                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data         2242                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total         2242                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data         2242                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total         2242                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     18104500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total     18104500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     68881000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total     68881000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        42000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        42000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data     86985500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total     86985500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data     86985500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total     86985500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000024                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000024                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000266                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000266                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.002146                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.002146                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000080                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.000080                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000080                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.000080                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35499.019608                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35499.019608                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39769.630485                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39769.630485                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        42000                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        42000                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38798.171276                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 38798.171276                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38798.171276                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 38798.171276                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.tagsinuse              2417.634669                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                    9160                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                  3606                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  2.540211                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks    17.697335                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   2024.265560                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data    375.671774                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.000540                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.061776                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.011465                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.073780                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst         9092                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data           54                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total           9146                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks          108                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total          108                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data           26                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total           26                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst         9092                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data           80                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total            9172                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         9092                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data           80                       # number of overall hits
system.cpu.l2cache.overall_hits::total           9172                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3083                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data          457                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         3540                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data         1706                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         1706                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3083                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         2163                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          5246                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3083                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         2163                       # number of overall misses
system.cpu.l2cache.overall_misses::total         5246                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    108859500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data     17384500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    126244000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     66352500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total     66352500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    108859500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data     83737000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    192596500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    108859500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data     83737000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    192596500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        12175                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data          511                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        12686                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks          108                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total          108                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data         1732                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         1732                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        12175                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data         2243                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total        14418                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        12175                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data         2243                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total        14418                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.253224                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.894325                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.279048                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.984988                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.984988                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.253224                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.964333                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.363851                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.253224                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.964333                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.363851                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35309.601038                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38040.481400                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 35662.146893                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38893.610785                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38893.610785                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35309.601038                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38713.361073                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 36713.019443                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35309.601038                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38713.361073                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 36713.019443                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs         7500                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                1                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs         7500                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3083                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          457                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         3540                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1706                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         1706                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3083                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         2163                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         5246                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3083                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         2163                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total         5246                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     98880000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     15955500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    114835500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     60925000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     60925000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     98880000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     76880500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    175760500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     98880000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     76880500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    175760500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.253224                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.894325                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.279048                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.984988                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.984988                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.253224                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964333                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.363851                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.253224                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964333                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.363851                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32072.656503                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34913.566740                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32439.406780                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35712.192263                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35712.192263                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32072.656503                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35543.458160                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33503.717118                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32072.656503                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35543.458160                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33503.717118                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------