path: root/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.021919                       # Number of seconds simulated
sim_ticks                                 21919473500                       # Number of ticks simulated
final_tick                                21919473500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 199769                       # Simulator instruction rate (inst/s)
host_op_rate                                   199769                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               52017673                       # Simulator tick rate (ticks/s)
host_mem_usage                                 302932                       # Number of bytes of host memory used
host_seconds                                   421.39                       # Real time elapsed on the host
sim_insts                                    84179709                       # Number of instructions simulated
sim_ops                                      84179709                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            195776                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            138496                       # Number of bytes read from this memory
system.physmem.bytes_read::total               334272                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       195776                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          195776                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst               3059                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               2164                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                  5223                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst              8931601                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              6318400                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                15250001                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         8931601                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            8931601                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             8931601                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             6318400                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               15250001                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                          5223                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                        5223                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                   334272                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                    334272                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                 470                       # Per bank write bursts
system.physmem.perBankRdBursts::1                 290                       # Per bank write bursts
system.physmem.perBankRdBursts::2                 302                       # Per bank write bursts
system.physmem.perBankRdBursts::3                 523                       # Per bank write bursts
system.physmem.perBankRdBursts::4                 220                       # Per bank write bursts
system.physmem.perBankRdBursts::5                 223                       # Per bank write bursts
system.physmem.perBankRdBursts::6                 218                       # Per bank write bursts
system.physmem.perBankRdBursts::7                 288                       # Per bank write bursts
system.physmem.perBankRdBursts::8                 239                       # Per bank write bursts
system.physmem.perBankRdBursts::9                 278                       # Per bank write bursts
system.physmem.perBankRdBursts::10                249                       # Per bank write bursts
system.physmem.perBankRdBursts::11                251                       # Per bank write bursts
system.physmem.perBankRdBursts::12                396                       # Per bank write bursts
system.physmem.perBankRdBursts::13                338                       # Per bank write bursts
system.physmem.perBankRdBursts::14                489                       # Per bank write bursts
system.physmem.perBankRdBursts::15                449                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     21919378500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                    5223                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                      3272                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      1189                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       507                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       237                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        15                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples          860                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      387.497674                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     231.928894                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     358.454487                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127            254     29.53%     29.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255          187     21.74%     51.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           83      9.65%     60.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           58      6.74%     67.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639           36      4.19%     71.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767           34      3.95%     75.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895           40      4.65%     80.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023           50      5.81%     86.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151          118     13.72%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total            860                       # Bytes accessed per row activation
system.physmem.totQLat                       44538500                       # Total ticks spent queuing
system.physmem.totMemAccLat                 142469750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                     26115000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        8527.38                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  27277.38                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          15.25                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       15.25                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.12                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.12                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                       4358                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.44                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                      4196702.76                       # Average gap between requests
system.physmem.pageHitRate                      83.44                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                    3160080                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                    1724250                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                  19741800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy             1431596400                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy              935708580                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy            12330335250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy              14722266360                       # Total energy per rank (pJ)
system.physmem_0.averagePower              671.680556                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE    20510216250                       # Time in different power states
system.physmem_0.memoryStateTime::REF       731900000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT       676644750                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                    3341520                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                    1823250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                  20872800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy             1431596400                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy              913464900                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy            12349847250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy              14720946120                       # Total energy per rank (pJ)
system.physmem_1.averagePower              671.620322                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE    20542312250                       # Time in different power states
system.physmem_1.memoryStateTime::REF       731900000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT       644355250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                16112018                       # Number of BP lookups
system.cpu.branchPred.condPredicted          11701868                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            926184                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              8628002                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 7529875                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             87.272523                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1595504                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                407                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                     24062707                       # DTB read hits
system.cpu.dtb.read_misses                     205786                       # DTB read misses
system.cpu.dtb.read_acv                             2                       # DTB read access violations
system.cpu.dtb.read_accesses                 24268493                       # DTB read accesses
system.cpu.dtb.write_hits                     7162407                       # DTB write hits
system.cpu.dtb.write_misses                      1203                       # DTB write misses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_accesses                 7163610                       # DTB write accesses
system.cpu.dtb.data_hits                     31225114                       # DTB hits
system.cpu.dtb.data_misses                     206989                       # DTB misses
system.cpu.dtb.data_acv                             2                       # DTB access violations
system.cpu.dtb.data_accesses                 31432103                       # DTB accesses
system.cpu.itb.fetch_hits                    15925407                       # ITB hits
system.cpu.itb.fetch_misses                        77                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses                15925484                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                  389                       # Number of system calls
system.cpu.numCycles                         43838948                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           16632320                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      137954260                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    16112018                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9125379                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      25989721                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1930958                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                  137                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles          2266                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles            8                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  15925407                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                365179                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           43589931                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              3.164819                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.433135                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 19407451     44.52%     44.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  2621129      6.01%     50.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1337584      3.07%     53.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  1925835      4.42%     58.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  3007413      6.90%     64.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1288266      2.96%     67.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1362128      3.12%     71.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                   884292      2.03%     73.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 11755833     26.97%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             43589931                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.367527                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        3.146842                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 12848398                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles               8248987                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  19437203                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               2101434                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 953909                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              2651089                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 11974                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              132128383                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                 49953                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                 953909                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 13970899                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 4649700                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          10898                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  20300581                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               3703944                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              128750721                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 69632                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                2039237                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                1388591                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                  55010                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands            94550726                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             167277672                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        159796203                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups           7481468                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              68427361                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 26123365                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                949                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts            946                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                   8314647                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             26912240                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores             8709829                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           3514186                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          1623457                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  111857121                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                1283                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                  99743085                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            115820                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        27678694                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     21106490                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            894                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      43589931                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.288214                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.099779                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            11253194     25.82%     25.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1             7641118     17.53%     43.35% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             7479948     17.16%     60.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             5719610     13.12%     73.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             4459621     10.23%     83.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             2975044      6.83%     90.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             2026173      4.65%     95.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             1169285      2.68%     98.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              865938      1.99%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        43589931                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  482162     20.24%     20.24% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     20.24% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     20.24% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                   537      0.02%     20.26% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     20.26% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                 34275      1.44%     21.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                12320      0.52%     22.22% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv               1010506     42.41%     64.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     64.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     64.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     64.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     64.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     64.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     64.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     64.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     64.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     64.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     64.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     64.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     64.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     64.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     64.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     64.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     64.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     64.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     64.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     64.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     64.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     64.63% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 685066     28.75%     93.38% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                157661      6.62%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 7      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              60678292     60.83%     60.83% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               490564      0.49%     61.33% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd             2838989      2.85%     64.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp              115355      0.12%     64.29% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt             2438911      2.45%     66.73% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult             313691      0.31%     67.05% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv              766049      0.77%     67.82% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                319      0.00%     67.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.82% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             24838081     24.90%     92.72% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             7262827      7.28%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               99743085                       # Type of FU issued
system.cpu.iq.rate                           2.275216                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2382527                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.023887                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          229948900                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         130065304                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     89786778                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads            15625548                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes            9512793                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses      7169302                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses               93776538                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                 8349067                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1917366                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      6916042                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        11056                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        41363                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      2208726                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        42784                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked          1527                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 953909                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 3616734                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                464700                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           122788755                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            239982                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              26912240                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts              8709829                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               1283                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                  38454                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                420547                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          41363                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         525246                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       502956                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1028202                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts              98432500                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              24268972                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1310585                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                      10930351                       # number of nop insts executed
system.cpu.iew.exec_refs                     31432616                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 12487704                       # Number of branches executed
system.cpu.iew.exec_stores                    7163644                       # Number of stores executed
system.cpu.iew.exec_rate                     2.245321                       # Inst execution rate
system.cpu.iew.wb_sent                       97645732                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      96956080                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  66985594                       # num instructions producing a value
system.cpu.iew.wb_consumers                  95002941                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       2.211642                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.705090                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        30887581                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls             389                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            914614                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     39095972                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.350704                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.921132                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     14698430     37.60%     37.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1      8547015     21.86%     59.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3864183      9.88%     69.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      1929221      4.93%     74.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1372371      3.51%     77.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1004316      2.57%     80.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       690404      1.77%     82.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       733733      1.88%     84.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      6256299     16.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     39095972                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             91903055                       # Number of instructions committed
system.cpu.commit.committedOps               91903055                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       26497301                       # Number of memory references committed
system.cpu.commit.loads                      19996198                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                   10240685                       # Number of branches committed
system.cpu.commit.fp_insts                    6862061                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  79581076                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1029620                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass      7723353      8.40%      8.40% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu         51001453     55.49%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          458252      0.50%     64.40% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     64.40% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd        2732553      2.97%     67.37% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp         104605      0.11%     67.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt        2333953      2.54%     70.02% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult        296445      0.32%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv         754822      0.82%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt           318      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        19996198     21.76%     92.93% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite        6501103      7.07%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total          91903055                       # Class of committed instruction
system.cpu.commit.bw_lim_events               6256299                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                    155629269                       # The number of ROB reads
system.cpu.rob.rob_writes                   250130763                       # The number of ROB writes
system.cpu.timesIdled                            4629                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          249017                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                    84179709                       # Number of Instructions Simulated
system.cpu.committedOps                      84179709                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.520778                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.520778                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.920204                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.920204                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                132982273                       # number of integer regfile reads
system.cpu.int_regfile_writes                72919705                       # number of integer regfile writes
system.cpu.fp_regfile_reads                   6252521                       # number of floating regfile reads
system.cpu.fp_regfile_writes                  6155462                       # number of floating regfile writes
system.cpu.misc_regfile_reads                  719143                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.dcache.tags.replacements               158                       # number of replacements
system.cpu.dcache.tags.tagsinuse          1457.350779                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            28592916                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs              2244                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs          12741.941176                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  1457.350779                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.355799                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.355799                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         2086                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          131                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          542                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4         1389                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.509277                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          57207152                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         57207152                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     22099846                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        22099846                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      6492613                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        6492613                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data          457                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total          457                       # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data      28592459                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         28592459                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     28592459                       # number of overall hits
system.cpu.dcache.overall_hits::total        28592459                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data         1047                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total          1047                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data         8490                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total         8490                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data         9537                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total           9537                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data         9537                       # number of overall misses
system.cpu.dcache.overall_misses::total          9537                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data     69532500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total     69532500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data    543709251                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total    543709251                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        85000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total        85000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data    613241751                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total    613241751                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data    613241751                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total    613241751                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     22100893                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     22100893                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data          458                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total          458                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     28601996                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     28601996                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     28601996                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     28601996                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000047                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000047                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001306                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.001306                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002183                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002183                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.000333                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.000333                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.000333                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.000333                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66411.174785                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 66411.174785                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64041.136749                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 64041.136749                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        85000                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        85000                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 64301.326518                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 64301.326518                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 64301.326518                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 64301.326518                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        32746                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets          127                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs               389                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    84.179949                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    63.500000                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks          108                       # number of writebacks
system.cpu.dcache.writebacks::total               108                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data          540                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total          540                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6754                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total         6754                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data         7294                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total         7294                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data         7294                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total         7294                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data          507                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total          507                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1736                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         1736                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data         2243                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total         2243                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data         2243                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total         2243                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     39700000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total     39700000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    135151495                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total    135151495                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        84000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        84000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data    174851495                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total    174851495                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data    174851495                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total    174851495                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000023                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000023                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000267                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000267                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.002183                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.002183                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000078                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.000078                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000078                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.000078                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78303.747535                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78303.747535                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77852.243664                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77852.243664                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        84000                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        84000                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77954.300045                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 77954.300045                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77954.300045                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 77954.300045                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements              9477                       # number of replacements
system.cpu.icache.tags.tagsinuse          1601.339074                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            15910864                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             11414                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs           1393.977922                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1601.339074                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.781904                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.781904                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1937                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          181                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          752                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          944                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.945801                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          31862226                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         31862226                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     15910864                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        15910864                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      15910864                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         15910864                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     15910864                       # number of overall hits
system.cpu.icache.overall_hits::total        15910864                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        14542                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         14542                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        14542                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          14542                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        14542                       # number of overall misses
system.cpu.icache.overall_misses::total         14542                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    447928500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    447928500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    447928500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    447928500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    447928500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    447928500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     15925406                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     15925406                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     15925406                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     15925406                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     15925406                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     15925406                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000913                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000913                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000913                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000913                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000913                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000913                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30802.399945                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 30802.399945                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 30802.399945                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 30802.399945                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 30802.399945                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 30802.399945                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          837                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 4                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs   209.250000                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3128                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         3128                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         3128                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         3128                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         3128                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         3128                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        11414                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        11414                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        11414                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        11414                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        11414                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        11414                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    338490500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    338490500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    338490500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    338490500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    338490500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    338490500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000717                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000717                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000717                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000717                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000717                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000717                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29655.729806                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29655.729806                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29655.729806                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 29655.729806                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29655.729806                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 29655.729806                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse         2397.609271                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs              17951                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs             3579                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             5.015647                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks    17.690606                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  2004.677718                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data   375.240947                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.000540                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.061178                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.011451                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.073169                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024         3579                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           70                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          178                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          908                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2421                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.109222                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses           191659                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses          191659                       # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks          108                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total          108                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data           26                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total           26                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         8355                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total         8355                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data           54                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total           54                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst         8355                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data           80                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total            8435                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         8355                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data           80                       # number of overall hits
system.cpu.l2cache.overall_hits::total           8435                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data         1710                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         1710                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3059                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         3059                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data          454                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total          454                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3059                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         2164                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          5223                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3059                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         2164                       # number of overall misses
system.cpu.l2cache.overall_misses::total         5223                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    132132500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total    132132500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    233633500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    233633500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     38438500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total     38438500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    233633500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data    170571000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    404204500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    233633500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data    170571000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    404204500                       # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks          108                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total          108                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data         1736                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         1736                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        11414                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total        11414                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          508                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total          508                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        11414                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data         2244                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total        13658                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        11414                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data         2244                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total        13658                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.985023                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.985023                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.268004                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.268004                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.893701                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.893701                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.268004                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.964349                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.382413                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.268004                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.964349                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.382413                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77270.467836                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77270.467836                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76375.776398                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76375.776398                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84666.299559                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84666.299559                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76375.776398                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78822.088725                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 77389.335631                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76375.776398                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78822.088725                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 77389.335631                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1710                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         1710                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3059                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3059                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          454                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total          454                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3059                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         2164                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         5223                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3059                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         2164                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total         5223                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    115032500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    115032500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    203043500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    203043500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     33898500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     33898500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    203043500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    148931000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    351974500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    203043500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    148931000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    351974500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.985023                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.985023                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.268004                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.268004                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.893701                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.893701                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.268004                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964349                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.382413                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.268004                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964349                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.382413                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67270.467836                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67270.467836                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66375.776398                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66375.776398                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74666.299559                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74666.299559                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66375.776398                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68822.088725                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67389.335631                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66375.776398                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68822.088725                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67389.335631                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests        23293                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests         9635                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp         11922                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback          108                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict         9527                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq         1736                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp         1736                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq        11414                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq          508                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        32305                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4646                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total             36951                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       730496                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       150528                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total             881024                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples        23293                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0              23293    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total          23293                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy       11754500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      17121000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy       3366000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.membus.trans_dist::ReadResp               3513                       # Transaction distribution
system.membus.trans_dist::ReadExReq              1710                       # Transaction distribution
system.membus.trans_dist::ReadExResp             1710                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq          3513                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10446                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                  10446                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       334272                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                  334272                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples              5223                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                    5223    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                5223                       # Request fanout histogram
system.membus.reqLayer0.occupancy             6235500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy           27428750                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)

---------- End Simulation Statistics   ----------