path: root/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.021906                       # Number of seconds simulated
sim_ticks                                 21906070500                       # Number of ticks simulated
final_tick                                21906070500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 201237                       # Simulator instruction rate (inst/s)
host_op_rate                                   201237                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               52367931                       # Simulator tick rate (ticks/s)
host_mem_usage                                 260088                       # Number of bytes of host memory used
host_seconds                                   418.31                       # Real time elapsed on the host
sim_insts                                    84179709                       # Number of instructions simulated
sim_ops                                      84179709                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED  21906070500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst            195968                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            138560                       # Number of bytes read from this memory
system.physmem.bytes_read::total               334528                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       195968                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          195968                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst               3062                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               2165                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                  5227                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst              8945831                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              6325187                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                15271018                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         8945831                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            8945831                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             8945831                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             6325187                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               15271018                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                          5227                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                        5227                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                   334528                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                    334528                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                 470                       # Per bank write bursts
system.physmem.perBankRdBursts::1                 292                       # Per bank write bursts
system.physmem.perBankRdBursts::2                 302                       # Per bank write bursts
system.physmem.perBankRdBursts::3                 523                       # Per bank write bursts
system.physmem.perBankRdBursts::4                 220                       # Per bank write bursts
system.physmem.perBankRdBursts::5                 223                       # Per bank write bursts
system.physmem.perBankRdBursts::6                 218                       # Per bank write bursts
system.physmem.perBankRdBursts::7                 288                       # Per bank write bursts
system.physmem.perBankRdBursts::8                 239                       # Per bank write bursts
system.physmem.perBankRdBursts::9                 278                       # Per bank write bursts
system.physmem.perBankRdBursts::10                249                       # Per bank write bursts
system.physmem.perBankRdBursts::11                251                       # Per bank write bursts
system.physmem.perBankRdBursts::12                395                       # Per bank write bursts
system.physmem.perBankRdBursts::13                338                       # Per bank write bursts
system.physmem.perBankRdBursts::14                492                       # Per bank write bursts
system.physmem.perBankRdBursts::15                449                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     21905974500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                    5227                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                      3276                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      1193                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       513                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       227                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        16                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples          862                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      385.707657                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     229.399691                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     360.883028                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127            260     30.16%     30.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255          179     20.77%     50.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           93     10.79%     61.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           57      6.61%     68.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639           30      3.48%     71.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767           37      4.29%     76.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895           31      3.60%     79.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023           50      5.80%     85.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151          125     14.50%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total            862                       # Bytes accessed per row activation
system.physmem.totQLat                       40339750                       # Total ticks spent queuing
system.physmem.totMemAccLat                 138346000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                     26135000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        7717.57                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  26467.57                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          15.27                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       15.27                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.12                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.12                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                       4357                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.36                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                      4190926.82                       # Average gap between requests
system.physmem.pageHitRate                      83.36                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                    3129840                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                    1707750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                  19570200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy             1430579280                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy              905463810                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy            12347522250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy              14707973130                       # Total energy per rank (pJ)
system.physmem_0.averagePower              671.505534                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE    20538678250                       # Time in different power states
system.physmem_0.memoryStateTime::REF       731380000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT       632936750                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                    3333960                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                    1819125                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                  20779200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy             1430579280                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy              902236185                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy            12350353500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy              14709101250                       # Total energy per rank (pJ)
system.physmem_1.averagePower              671.557040                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE    20543762750                       # Time in different power states
system.physmem_1.memoryStateTime::REF       731380000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT       628284250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED  21906070500                       # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups                16102243                       # Number of BP lookups
system.cpu.branchPred.condPredicted          11688063                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            931000                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              8962915                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 7507921                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             83.766509                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1594308                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                466                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups           29379                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits              25730                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses             3649                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted          560                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                     24059471                       # DTB read hits
system.cpu.dtb.read_misses                     206747                       # DTB read misses
system.cpu.dtb.read_acv                             6                       # DTB read access violations
system.cpu.dtb.read_accesses                 24266218                       # DTB read accesses
system.cpu.dtb.write_hits                     7167964                       # DTB write hits
system.cpu.dtb.write_misses                      1190                       # DTB write misses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_accesses                 7169154                       # DTB write accesses
system.cpu.dtb.data_hits                     31227435                       # DTB hits
system.cpu.dtb.data_misses                     207937                       # DTB misses
system.cpu.dtb.data_acv                             6                       # DTB access violations
system.cpu.dtb.data_accesses                 31435372                       # DTB accesses
system.cpu.itb.fetch_hits                    15930202                       # ITB hits
system.cpu.itb.fetch_misses                        79                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses                15930281                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                  389                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON     21906070500                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                         43812142                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           16640800                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      137955116                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    16102243                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9127959                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      25951378                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1939862                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                  140                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles          2284                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           28                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  15930202                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                367997                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           43564561                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              3.166682                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.433652                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 19388904     44.51%     44.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  2617971      6.01%     50.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1329653      3.05%     53.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  1933242      4.44%     58.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  3001866      6.89%     64.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1292154      2.97%     67.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1355153      3.11%     70.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                   885983      2.03%     73.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 11759635     26.99%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             43564561                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.367529                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        3.148787                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 12866207                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles               8201064                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  19435677                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               2103016                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 958597                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              2653560                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 11864                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              132121785                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                 49799                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                 958597                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 13983011                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 4637206                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          10599                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  20305280                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               3669868                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              128752916                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 70736                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                2012785                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                1367413                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                  56554                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands            94580122                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             167299448                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        159747069                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups           7552378                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              68427361                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 26152761                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                954                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts            949                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                   8254781                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             26901517                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores             8704631                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           3463893                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          1634991                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  111837286                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                1924                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                  99746434                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            118591                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        27659500                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     21091403                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           1535                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      43564561                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.289623                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.099110                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            11223672     25.76%     25.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1             7655343     17.57%     43.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             7467756     17.14%     60.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             5704970     13.10%     73.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             4467403     10.25%     83.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             2981246      6.84%     90.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             2039535      4.68%     95.35% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             1169471      2.68%     98.04% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              855165      1.96%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        43564561                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  481664     20.16%     20.16% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     20.16% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     20.16% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                   522      0.02%     20.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     20.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                 34768      1.46%     21.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                12121      0.51%     22.15% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv               1011551     42.34%     64.49% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     64.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     64.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     64.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     64.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     64.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     64.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     64.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     64.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     64.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     64.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     64.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     64.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     64.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     64.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     64.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     64.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     64.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     64.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     64.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     64.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     64.49% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 688710     28.83%     93.32% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                159620      6.68%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 7      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              60652801     60.81%     60.81% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               489881      0.49%     61.30% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.30% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd             2847832      2.86%     64.15% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp              115342      0.12%     64.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt             2442782      2.45%     66.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult             314177      0.31%     67.03% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv              766025      0.77%     67.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                319      0.00%     67.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.80% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             24850091     24.91%     92.71% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             7267177      7.29%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               99746434                       # Type of FU issued
system.cpu.iq.rate                           2.276685                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2388956                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.023950                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          229877287                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         129889935                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     89741335                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads            15687689                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes            9649325                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses      7189295                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses               93754597                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                 8380786                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1921314                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      6905319                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        11494                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        40918                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      2203528                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        42875                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked          1512                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 958597                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 3610605                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                461685                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           122758059                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            241249                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              26901517                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts              8704631                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               1924                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                  38682                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                417297                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          40918                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         531922                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       502439                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1034361                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts              98421413                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              24266766                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1325021                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                      10918849                       # number of nop insts executed
system.cpu.iew.exec_refs                     31435958                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 12470734                       # Number of branches executed
system.cpu.iew.exec_stores                    7169192                       # Number of stores executed
system.cpu.iew.exec_rate                     2.246441                       # Inst execution rate
system.cpu.iew.wb_sent                       97629714                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      96930630                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  66965531                       # num instructions producing a value
system.cpu.iew.wb_consumers                  94946242                       # num instructions consuming a value
system.cpu.iew.wb_rate                       2.212415                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.705299                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts        30856710                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls             389                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            919666                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     39073158                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.352076                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.920100                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     14677251     37.56%     37.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1      8528323     21.83%     59.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3880033      9.93%     69.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      1914323      4.90%     74.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1374739      3.52%     77.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1034073      2.65%     80.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       692942      1.77%     82.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       727068      1.86%     84.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      6244406     15.98%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     39073158                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             91903055                       # Number of instructions committed
system.cpu.commit.committedOps               91903055                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       26497301                       # Number of memory references committed
system.cpu.commit.loads                      19996198                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                   10240685                       # Number of branches committed
system.cpu.commit.fp_insts                    6862061                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  79581076                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1029620                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass      7723353      8.40%      8.40% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu         51001453     55.49%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          458252      0.50%     64.40% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     64.40% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd        2732553      2.97%     67.37% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp         104605      0.11%     67.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt        2333953      2.54%     70.02% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult        296445      0.32%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv         754822      0.82%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt           318      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     71.17% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        19996198     21.76%     92.93% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite        6501103      7.07%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total          91903055                       # Class of committed instruction
system.cpu.commit.bw_lim_events               6244406                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                    155587477                       # The number of ROB reads
system.cpu.rob.rob_writes                   250066312                       # The number of ROB writes
system.cpu.timesIdled                            4758                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          247581                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                    84179709                       # Number of Instructions Simulated
system.cpu.committedOps                      84179709                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.520460                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.520460                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.921379                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.921379                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                132984940                       # number of integer regfile reads
system.cpu.int_regfile_writes                72890464                       # number of integer regfile writes
system.cpu.fp_regfile_reads                   6263699                       # number of floating regfile reads
system.cpu.fp_regfile_writes                  6177982                       # number of floating regfile writes
system.cpu.misc_regfile_reads                  719169                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  21906070500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements               158                       # number of replacements
system.cpu.dcache.tags.tagsinuse          1457.358075                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            28585648                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs              2245                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs          12733.028062                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  1457.358075                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.355800                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.355800                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         2087                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          130                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          543                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4         1389                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.509521                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          57192649                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         57192649                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  21906070500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data     22092545                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        22092545                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      6492630                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        6492630                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data          473                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total          473                       # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data      28585175                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         28585175                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     28585175                       # number of overall hits
system.cpu.dcache.overall_hits::total        28585175                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data         1080                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total          1080                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data         8473                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total         8473                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data         9553                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total           9553                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data         9553                       # number of overall misses
system.cpu.dcache.overall_misses::total          9553                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data     72549500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total     72549500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data    550211742                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total    550211742                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        86000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total        86000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data    622761242                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total    622761242                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data    622761242                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total    622761242                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     22093625                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     22093625                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data          474                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total          474                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     28594728                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     28594728                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     28594728                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     28594728                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000049                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000049                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001303                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.001303                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002110                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002110                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.000334                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.000334                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.000334                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.000334                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67175.462963                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 67175.462963                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64937.063850                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 64937.063850                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        86000                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        86000                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 65190.122684                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 65190.122684                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 65190.122684                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 65190.122684                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        33457                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets          131                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs               396                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    84.487374                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    65.500000                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks          108                       # number of writebacks
system.cpu.dcache.writebacks::total               108                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data          565                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total          565                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6744                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total         6744                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data         7309                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total         7309                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data         7309                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total         7309                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data          515                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total          515                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1729                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         1729                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data         2244                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total         2244                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data         2244                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total         2244                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     40822500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total     40822500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    136978995                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total    136978995                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        85000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        85000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data    177801495                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total    177801495                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data    177801495                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total    177801495                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000023                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000023                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000266                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000266                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.002110                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.002110                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000078                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.000078                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000078                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.000078                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79266.990291                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79266.990291                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79224.404280                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79224.404280                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        85000                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        85000                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79234.177807                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 79234.177807                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79234.177807                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 79234.177807                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  21906070500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements              9515                       # number of replacements
system.cpu.icache.tags.tagsinuse          1600.893985                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            15915792                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             11453                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs           1389.661399                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1600.893985                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.781687                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.781687                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1938                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          180                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          753                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          943                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.946289                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          31871855                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         31871855                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  21906070500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst     15915792                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        15915792                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      15915792                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         15915792                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     15915792                       # number of overall hits
system.cpu.icache.overall_hits::total        15915792                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        14409                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         14409                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        14409                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          14409                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        14409                       # number of overall misses
system.cpu.icache.overall_misses::total         14409                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    447639000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    447639000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    447639000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    447639000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    447639000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    447639000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     15930201                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     15930201                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     15930201                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     15930201                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     15930201                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     15930201                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000905                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000905                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000905                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000905                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000905                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000905                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31066.625026                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 31066.625026                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 31066.625026                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 31066.625026                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 31066.625026                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 31066.625026                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          446                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 5                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    89.200000                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks         9515                       # number of writebacks
system.cpu.icache.writebacks::total              9515                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2955                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         2955                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         2955                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         2955                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         2955                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         2955                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        11454                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        11454                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        11454                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        11454                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        11454                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        11454                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    337628000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    337628000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    337628000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    337628000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    337628000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    337628000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000719                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000719                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000719                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000719                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000719                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000719                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29476.863978                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29476.863978                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29476.863978                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 29476.863978                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29476.863978                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 29476.863978                       # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  21906070500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse         3490.224517                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs              18145                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs             5227                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             3.471399                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst  2007.515587                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  1482.708930                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.061265                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.045249                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.106513                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024         5227                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          263                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1371                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3517                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.159515                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses           192203                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses          192203                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  21906070500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks          108                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total          108                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks         9515                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total         9515                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data           26                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total           26                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         8392                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total         8392                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data           54                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total           54                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst         8392                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data           80                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total            8472                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         8392                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data           80                       # number of overall hits
system.cpu.l2cache.overall_hits::total           8472                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data         1703                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         1703                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3062                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         3062                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data          462                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total          462                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3062                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         2165                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          5227                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3062                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         2165                       # number of overall misses
system.cpu.l2cache.overall_misses::total         5227                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    133969500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total    133969500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    232023500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    232023500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     39550000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total     39550000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    232023500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data    173519500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    405543000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    232023500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data    173519500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    405543000                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks          108                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total          108                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks         9515                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total         9515                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data         1729                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         1729                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        11454                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total        11454                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          516                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total          516                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        11454                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data         2245                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total        13699                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        11454                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data         2245                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total        13699                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.984962                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.984962                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.267330                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.267330                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.895349                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.895349                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.267330                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.964365                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.381561                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.267330                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.964365                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.381561                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78666.764533                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78666.764533                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75775.146963                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75775.146963                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85606.060606                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85606.060606                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75775.146963                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80147.575058                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 77586.187105                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75775.146963                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80147.575058                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 77586.187105                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1703                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         1703                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3062                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3062                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          462                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total          462                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3062                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         2165                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         5227                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3062                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         2165                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total         5227                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    116939500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    116939500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    201403500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    201403500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     34930000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     34930000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    201403500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    151869500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    353273000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    201403500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    151869500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    353273000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.984962                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.984962                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.267330                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.267330                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.895349                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.895349                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.267330                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964365                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.381561                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.267330                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964365                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.381561                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68666.764533                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68666.764533                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65775.146963                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65775.146963                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75606.060606                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75606.060606                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65775.146963                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70147.575058                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67586.187105                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65775.146963                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70147.575058                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67586.187105                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests        23372                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests         9673                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  21906070500                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp         11969                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty          108                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean         9515                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict           50                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq         1729                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp         1729                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq        11454                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq          516                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        32422                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4648                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total             37070                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1341952                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       150592                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total            1492544                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples        13699                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0              13699    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total          13699                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy       21309000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      17179500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy       3367500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.membus.snoop_filter.tot_requests          5227                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED  21906070500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp               3524                       # Transaction distribution
system.membus.trans_dist::ReadExReq              1703                       # Transaction distribution
system.membus.trans_dist::ReadExResp             1703                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq          3524                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10454                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                  10454                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       334528                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                  334528                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples              5227                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                    5227    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                5227                       # Request fanout histogram
system.membus.reqLayer0.occupancy             6278000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy           27461750                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)

---------- End Simulation Statistics   ----------