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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.023496 # Number of seconds simulated
sim_ticks 23495860500 # Number of ticks simulated
final_tick 23495860500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 162171 # Simulator instruction rate (inst/s)
host_op_rate 162171 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 45264552 # Simulator tick rate (ticks/s)
host_mem_usage 273204 # Number of bytes of host memory used
host_seconds 519.08 # Real time elapsed on the host
sim_insts 84179709 # Number of instructions simulated
sim_ops 84179709 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 196096 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 138432 # Number of bytes read from this memory
system.physmem.bytes_read::total 334528 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 196096 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 196096 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3064 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2163 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5227 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 8345981 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 5891761 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14237742 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 8345981 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 8345981 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 8345981 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5891761 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 14237742 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 5227 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 5227 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 334528 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 334528 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 469 # Per bank write bursts
system.physmem.perBankRdBursts::1 291 # Per bank write bursts
system.physmem.perBankRdBursts::2 302 # Per bank write bursts
system.physmem.perBankRdBursts::3 524 # Per bank write bursts
system.physmem.perBankRdBursts::4 220 # Per bank write bursts
system.physmem.perBankRdBursts::5 226 # Per bank write bursts
system.physmem.perBankRdBursts::6 220 # Per bank write bursts
system.physmem.perBankRdBursts::7 285 # Per bank write bursts
system.physmem.perBankRdBursts::8 236 # Per bank write bursts
system.physmem.perBankRdBursts::9 280 # Per bank write bursts
system.physmem.perBankRdBursts::10 248 # Per bank write bursts
system.physmem.perBankRdBursts::11 254 # Per bank write bursts
system.physmem.perBankRdBursts::12 398 # Per bank write bursts
system.physmem.perBankRdBursts::13 336 # Per bank write bursts
system.physmem.perBankRdBursts::14 491 # Per bank write bursts
system.physmem.perBankRdBursts::15 447 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 23495733500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 5227 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 3282 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1191 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 631 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 112 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 867 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 383.188005 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 230.923786 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 354.572905 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 252 29.07% 29.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 197 22.72% 51.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 79 9.11% 60.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 57 6.57% 67.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 42 4.84% 72.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 41 4.73% 77.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 51 5.88% 82.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 24 2.77% 85.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 124 14.30% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 867 # Bytes accessed per row activation
system.physmem.totQLat 41053500 # Total ticks spent queuing
system.physmem.totMemAccLat 139059750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 26135000 # Total ticks spent in databus transfers
system.physmem.avgQLat 7854.12 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 26604.12 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 14.24 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 14.24 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.11 # Data bus utilization in percentage
system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 4351 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.24 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 4495070.50 # Average gap between requests
system.physmem.pageHitRate 83.24 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 21787630000 # Time in different power states
system.physmem.memoryStateTime::REF 784420000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 919340000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.membus.throughput 14237742 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 3522 # Transaction distribution
system.membus.trans_dist::ReadResp 3522 # Transaction distribution
system.membus.trans_dist::ReadExReq 1705 # Transaction distribution
system.membus.trans_dist::ReadExResp 1705 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10454 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 10454 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334528 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 334528 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 334528 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 6755000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 48973500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 14867597 # Number of BP lookups
system.cpu.branchPred.condPredicted 10786733 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 927657 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 8507235 # Number of BTB lookups
system.cpu.branchPred.BTBHits 6975722 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 81.997523 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1468896 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 3134 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 23141508 # DTB read hits
system.cpu.dtb.read_misses 194908 # DTB read misses
system.cpu.dtb.read_acv 2 # DTB read access violations
system.cpu.dtb.read_accesses 23336416 # DTB read accesses
system.cpu.dtb.write_hits 7073051 # DTB write hits
system.cpu.dtb.write_misses 1111 # DTB write misses
system.cpu.dtb.write_acv 1 # DTB write access violations
system.cpu.dtb.write_accesses 7074162 # DTB write accesses
system.cpu.dtb.data_hits 30214559 # DTB hits
system.cpu.dtb.data_misses 196019 # DTB misses
system.cpu.dtb.data_acv 3 # DTB access violations
system.cpu.dtb.data_accesses 30410578 # DTB accesses
system.cpu.itb.fetch_hits 14761442 # ITB hits
system.cpu.itb.fetch_misses 106 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 14761548 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
system.cpu.numCycles 46991722 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 15493602 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 127144789 # Number of instructions fetch has processed
system.cpu.fetch.Branches 14867597 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 8444618 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 22164191 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 4494518 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 5543985 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 114 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 2326 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 14761442 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 326314 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 46736650 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.720451 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.375825 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 24572459 52.58% 52.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2364267 5.06% 57.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1190852 2.55% 60.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 1750659 3.75% 63.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 2760354 5.91% 69.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1155374 2.47% 72.31% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1219764 2.61% 74.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 773397 1.65% 76.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 10949524 23.43% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 46736650 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.316388 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.705685 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 17320813 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 4244089 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 20558459 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1092640 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 3520649 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 2518881 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 12242 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 124135665 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 32164 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 3520649 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 18467014 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 956444 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 7682 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 20482522 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 3302339 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 121292511 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 99 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 405307 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 2418029 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 89077183 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 157604141 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 150534696 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 7069444 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 20649822 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 718 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 707 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 8775432 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 25394818 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 8253633 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 2570331 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 907077 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 105549830 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2075 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 96657653 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 179218 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 20902238 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 15662437 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1686 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 46736650 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.068134 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.876130 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 12165151 26.03% 26.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 9350062 20.01% 46.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 8404811 17.98% 64.02% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 6298333 13.48% 77.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 4922419 10.53% 88.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2869013 6.14% 94.17% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1725015 3.69% 97.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 796629 1.70% 99.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 205217 0.44% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 46736650 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 189767 12.10% 12.10% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 12.10% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 12.10% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 186 0.01% 12.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 7209 0.46% 12.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 5897 0.38% 12.94% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 843167 53.74% 66.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 66.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 66.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.68% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 445094 28.37% 95.05% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 77619 4.95% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 58783696 60.82% 60.82% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 479813 0.50% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2802274 2.90% 64.21% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 115457 0.12% 64.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 2387860 2.47% 66.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 311147 0.32% 67.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 760157 0.79% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 23859982 24.69% 92.60% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 7156941 7.40% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 96657653 # Type of FU issued
system.cpu.iq.rate 2.056908 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1568939 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.016232 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 226667825 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 117702286 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 87133167 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 15132288 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 8786528 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 7070448 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 90230128 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 7996457 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1520956 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 5398620 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 18484 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 34785 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1752530 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 10530 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 2127 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 3520649 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 133897 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 18217 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 115793083 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 374761 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 25394818 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 8253633 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 2075 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 2932 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 43 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 34785 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 541104 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 495336 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1036440 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 95417746 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 23336859 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1239907 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 10241178 # number of nop insts executed
system.cpu.iew.exec_refs 30411225 # number of memory reference insts executed
system.cpu.iew.exec_branches 12030179 # Number of branches executed
system.cpu.iew.exec_stores 7074366 # Number of stores executed
system.cpu.iew.exec_rate 2.030522 # Inst execution rate
system.cpu.iew.wb_sent 94727613 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 94203615 # cumulative count of insts written-back
system.cpu.iew.wb_producers 64511907 # num instructions producing a value
system.cpu.iew.wb_consumers 89904657 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 2.004685 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.717559 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 23891142 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 915882 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 43216001 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.126598 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.743951 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 16755601 38.77% 38.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 9919008 22.95% 61.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 4484606 10.38% 72.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2269127 5.25% 77.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1610437 3.73% 81.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1128955 2.61% 83.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 722092 1.67% 85.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 821021 1.90% 87.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 5505154 12.74% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 43216001 # Number of insts commited each cycle
system.cpu.commit.committedInsts 91903055 # Number of instructions committed
system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 26497301 # Number of memory references committed
system.cpu.commit.loads 19996198 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 10240685 # Number of branches committed
system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions.
system.cpu.commit.int_insts 79581076 # Number of committed integer instructions.
system.cpu.commit.function_calls 1029620 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 51001542 55.49% 63.90% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.40% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 2732464 2.97% 67.37% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 104605 0.11% 67.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 2333953 2.54% 70.02% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 296445 0.32% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 754822 0.82% 71.17% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 318 0.00% 71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.17% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 19996198 21.76% 92.93% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction
system.cpu.commit.bw_lim_events 5505154 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 153504004 # The number of ROB reads
system.cpu.rob.rob_writes 235133069 # The number of ROB writes
system.cpu.timesIdled 5418 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 255072 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 0.558231 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.558231 # CPI: Total CPI of All Threads
system.cpu.ipc 1.791373 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.791373 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 129151691 # number of integer regfile reads
system.cpu.int_regfile_writes 70572840 # number of integer regfile writes
system.cpu.fp_regfile_reads 6193374 # number of floating regfile reads
system.cpu.fp_regfile_writes 6052358 # number of floating regfile writes
system.cpu.misc_regfile_reads 714605 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.toL2Bus.throughput 37684936 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 11995 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 11995 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 109 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1731 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1731 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22964 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4597 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 27561 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 734848 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150592 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 885440 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 885440 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 7026500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 17802750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3545000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.icache.tags.replacements 9548 # number of replacements
system.cpu.icache.tags.tagsinuse 1597.278061 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 14747183 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 11482 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1284.374064 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1597.278061 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.779921 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.779921 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1934 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 760 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 930 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.944336 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 29534364 # Number of tag accesses
system.cpu.icache.tags.data_accesses 29534364 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 14747183 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 14747183 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 14747183 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 14747183 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 14747183 # number of overall hits
system.cpu.icache.overall_hits::total 14747183 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 14258 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 14258 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 14258 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 14258 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 14258 # number of overall misses
system.cpu.icache.overall_misses::total 14258 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 414157250 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 414157250 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 414157250 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 414157250 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 414157250 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 414157250 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 14761441 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 14761441 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 14761441 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 14761441 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 14761441 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 14761441 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000966 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000966 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000966 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000966 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000966 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000966 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29047.359377 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 29047.359377 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 29047.359377 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 29047.359377 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 29047.359377 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 29047.359377 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 61.600000 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2776 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 2776 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 2776 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 2776 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 2776 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 2776 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11482 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 11482 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 11482 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 11482 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 11482 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 11482 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 306274750 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 306274750 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 306274750 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 306274750 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 306274750 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 306274750 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000778 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000778 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000778 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000778 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000778 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000778 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26674.338094 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26674.338094 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26674.338094 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 26674.338094 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26674.338094 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 26674.338094 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 2409.001155 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 8488 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 3589 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 2.365004 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 17.673690 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2011.868133 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 379.459331 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.000539 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061397 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.011580 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.073517 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3589 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 909 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109528 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 116000 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 116000 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 8418 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 55 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 8473 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 109 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 109 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 8418 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 81 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 8499 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 8418 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 81 # number of overall hits
system.cpu.l2cache.overall_hits::total 8499 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 3064 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 458 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 3522 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 1705 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1705 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3064 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2163 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 5227 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3064 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2163 # number of overall misses
system.cpu.l2cache.overall_misses::total 5227 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 210607000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35793000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 246400000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 122677500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 122677500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 210607000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 158470500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 369077500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 210607000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 158470500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 369077500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 11482 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 513 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 11995 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 109 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 109 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1731 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1731 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 11482 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2244 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 13726 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 11482 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2244 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 13726 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.266852 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.892788 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.293622 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984980 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.984980 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.266852 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.963904 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.380810 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.266852 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.963904 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.380810 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68735.966057 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78150.655022 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69960.249858 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71951.612903 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71951.612903 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68735.966057 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73264.216366 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 70609.814425 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68735.966057 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73264.216366 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 70609.814425 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3064 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 3522 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1705 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1705 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3064 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2163 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 5227 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3064 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2163 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 5227 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 171789000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30123000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 201912000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 101752000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 101752000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171789000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131875000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 303664000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171789000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131875000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 303664000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.266852 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.892788 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.293622 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984980 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984980 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.266852 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963904 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.380810 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.266852 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963904 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.380810 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56066.906005 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65770.742358 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57328.790460 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59678.592375 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59678.592375 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56066.906005 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60968.562182 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58095.274536 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56066.906005 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60968.562182 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58095.274536 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 159 # number of replacements
system.cpu.dcache.tags.tagsinuse 1456.991941 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 28100018 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2244 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 12522.289661 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 1456.991941 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.355711 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.355711 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 2085 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1388 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.509033 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 56220748 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 56220748 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 21606921 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21606921 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 6492872 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 6492872 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 225 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 225 # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data 28099793 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 28099793 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 28099793 # number of overall hits
system.cpu.dcache.overall_hits::total 28099793 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1002 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1002 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 8231 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 8231 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 9233 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9233 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9233 # number of overall misses
system.cpu.dcache.overall_misses::total 9233 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 62924000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 62924000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 508720531 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 508720531 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 571644531 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 571644531 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 571644531 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 571644531 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 21607923 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 21607923 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 226 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 226 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 28109026 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 28109026 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 28109026 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 28109026 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001266 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001266 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004425 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004425 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62798.403194 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 62798.403194 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61805.434455 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 61805.434455 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 61913.195170 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 61913.195170 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61913.195170 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 61913.195170 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 23691 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 343 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.069971 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 109 # number of writebacks
system.cpu.dcache.writebacks::total 109 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 490 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 490 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6500 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 6500 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 6990 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 6990 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 6990 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 6990 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 512 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 512 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1731 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2243 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2243 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2243 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2243 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36779750 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 36779750 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124808747 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 124808747 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161588497 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 161588497 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161588497 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 161588497 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004425 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004425 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71835.449219 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71835.449219 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72102.106875 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72102.106875 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72041.238074 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 72041.238074 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72041.238074 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 72041.238074 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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