blob: ba87aad33450ed7f494f589aa8aea2c1825c8d6c (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.118740 # Number of seconds simulated
sim_ticks 118740049000 # Number of ticks simulated
final_tick 118740049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2095418 # Simulator instruction rate (inst/s)
host_tick_rate 2707308980 # Simulator tick rate (ticks/s)
host_mem_usage 211256 # Number of bytes of host memory used
host_seconds 43.86 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
system.physmem.bytes_read 304960 # Number of bytes read from this memory
system.physmem.bytes_inst_read 167744 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.physmem.num_reads 4765 # Number of read requests responded to by this memory
system.physmem.num_writes 0 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 2568299 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 1412699 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 2568299 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 19996198 # DTB read hits
system.cpu.dtb.read_misses 10 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 19996208 # DTB read accesses
system.cpu.dtb.write_hits 6501103 # DTB write hits
system.cpu.dtb.write_misses 23 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 6501126 # DTB write accesses
system.cpu.dtb.data_hits 26497301 # DTB hits
system.cpu.dtb.data_misses 33 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 26497334 # DTB accesses
system.cpu.itb.fetch_hits 91903090 # ITB hits
system.cpu.itb.fetch_misses 47 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 91903137 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
system.cpu.numCycles 237480098 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 91903056 # Number of instructions executed
system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses
system.cpu.num_func_calls 2059216 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls
system.cpu.num_int_insts 79581109 # number of integer instructions
system.cpu.num_fp_insts 6862064 # number of float instructions
system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read
system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written
system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read
system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written
system.cpu.num_mem_refs 26497334 # number of memory refs
system.cpu.num_load_insts 19996208 # Number of load instructions
system.cpu.num_store_insts 6501126 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 237480098 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 6681 # number of replacements
system.cpu.icache.tagsinuse 1418.037996 # Cycle average of tags in use
system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1418.037996 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.692401 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 91894580 # number of ReadReq hits
system.cpu.icache.demand_hits 91894580 # number of demand (read+write) hits
system.cpu.icache.overall_hits 91894580 # number of overall hits
system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses
system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses
system.cpu.icache.overall_misses 8510 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 229222000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 229222000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 229222000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 91903090 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 91903090 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 26935.605170 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 26935.605170 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 203692000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 203692000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 203692000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23935.605170 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 157 # number of replacements
system.cpu.dcache.tagsinuse 1442.028823 # Cycle average of tags in use
system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 1442.028823 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.352058 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits
system.cpu.dcache.demand_hits 26495078 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 26495078 # number of overall hits
system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses
system.cpu.dcache.demand_misses 2223 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 2223 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 24374000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 96796000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 121170000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 121170000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 55375.286041 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 54507.422402 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 54507.422402 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 107 # number of writebacks
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 22949000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 91552000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 114501000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 114501000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52375.286041 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 2074.048594 # Cycle average of tags in use
system.cpu.l2cache.total_refs 5951 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 3109 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 1.914120 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 2056.253411 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 17.795183 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.062752 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.000543 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 5942 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 5968 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 5968 # number of overall hits
system.cpu.l2cache.ReadReq_misses 3043 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 1722 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 4765 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 4765 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 158236000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 89544000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 247780000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 247780000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 8985 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 10733 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.338676 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.443958 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.443958 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 3043 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 4765 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 4765 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 121720000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 68880000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 190600000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 190600000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338676 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.443958 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.443958 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|
