path: root/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.131756                       # Number of seconds simulated
sim_ticks                                131756455500                       # Number of ticks simulated
final_tick                               131756455500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 249754                       # Simulator instruction rate (inst/s)
host_op_rate                                   263281                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              190965456                       # Simulator tick rate (ticks/s)
host_mem_usage                                 316672                       # Number of bytes of host memory used
host_seconds                                   689.95                       # Real time elapsed on the host
sim_insts                                   172317809                       # Number of instructions simulated
sim_ops                                     181650742                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            138304                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            109312                       # Number of bytes read from this memory
system.physmem.bytes_read::total               247616                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       138304                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          138304                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst               2161                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               1708                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                  3869                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst              1049694                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data               829652                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1879346                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         1049694                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            1049694                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             1049694                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data              829652                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                1879346                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                          3869                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                        3869                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                   247616                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                    247616                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                 305                       # Per bank write bursts
system.physmem.perBankRdBursts::1                 217                       # Per bank write bursts
system.physmem.perBankRdBursts::2                 135                       # Per bank write bursts
system.physmem.perBankRdBursts::3                 313                       # Per bank write bursts
system.physmem.perBankRdBursts::4                 307                       # Per bank write bursts
system.physmem.perBankRdBursts::5                 305                       # Per bank write bursts
system.physmem.perBankRdBursts::6                 273                       # Per bank write bursts
system.physmem.perBankRdBursts::7                 222                       # Per bank write bursts
system.physmem.perBankRdBursts::8                 249                       # Per bank write bursts
system.physmem.perBankRdBursts::9                 218                       # Per bank write bursts
system.physmem.perBankRdBursts::10                295                       # Per bank write bursts
system.physmem.perBankRdBursts::11                201                       # Per bank write bursts
system.physmem.perBankRdBursts::12                183                       # Per bank write bursts
system.physmem.perBankRdBursts::13                218                       # Per bank write bursts
system.physmem.perBankRdBursts::14                224                       # Per bank write bursts
system.physmem.perBankRdBursts::15                204                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    131756361000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                    3869                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                      3618                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       238                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        13                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples          895                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      274.663687                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     183.028895                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     274.690311                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127            245     27.37%     27.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255          357     39.89%     67.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           81      9.05%     76.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           51      5.70%     82.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639           43      4.80%     86.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767           26      2.91%     89.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895           22      2.46%     92.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023           16      1.79%     93.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151           54      6.03%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total            895                       # Bytes accessed per row activation
system.physmem.totQLat                       26801000                       # Total ticks spent queuing
system.physmem.totMemAccLat                  99344750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                     19345000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        6927.11                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  25677.11                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.88                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.88                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.01                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                       2968                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   76.71                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                     34054370.90                       # Average gap between requests
system.physmem.pageHitRate                      76.71                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                    3069360                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                    1674750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                  16169400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy             8605343760                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             3539588850                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy            75945927000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy              88111773120                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.773044                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   126343733250                       # Time in different power states
system.physmem_0.memoryStateTime::REF      4399460000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT      1010942750                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                    3681720                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                    2008875                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                  13774800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy             8605343760                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy             3587668065                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy            75903760500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy              88116237720                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.806861                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   126271447000                       # Time in different power states
system.physmem_1.memoryStateTime::REF      4399460000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT      1080937500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                49934480                       # Number of BP lookups
system.cpu.branchPred.condPredicted          39666708                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           5743450                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             24374232                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                23299942                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             95.592518                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1908561                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                139                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  400                       # Number of system calls
system.cpu.numCycles                        263512911                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   172317809                       # Number of instructions committed
system.cpu.committedOps                     181650742                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      11759003                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                               1.529226                       # CPI: cycles per instruction
system.cpu.ipc                               0.653925                       # IPC: instructions per cycle
system.cpu.tickCycles                       257129924                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                         6382987                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements                42                       # number of replacements
system.cpu.dcache.tags.tagsinuse          1377.698544                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            40765677                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs              1810                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs          22522.473481                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  1377.698544                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.336352                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.336352                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         1768                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           38                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           83                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3          271                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4         1358                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.431641                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          81538036                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         81538036                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     28358222                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        28358222                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     12362641                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       12362641                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        22407                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        22407                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      40720863                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         40720863                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     40720863                       # number of overall hits
system.cpu.dcache.overall_hits::total        40720863                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data          790                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total           790                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data         1646                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total         1646                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data         2436                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total           2436                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data         2436                       # number of overall misses
system.cpu.dcache.overall_misses::total          2436                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data     57599734                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total     57599734                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data    127302750                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total    127302750                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data    184902484                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total    184902484                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data    184902484                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total    184902484                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     28359012                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     28359012                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22407                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        22407                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     40723299                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     40723299                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     40723299                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     40723299                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000028                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000028                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000133                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.000133                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.000060                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.000060                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.000060                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.000060                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72911.055696                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 72911.055696                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77340.674362                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 77340.674362                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 75904.139573                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 75904.139573                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 75904.139573                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 75904.139573                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks           16                       # number of writebacks
system.cpu.dcache.writebacks::total                16                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data           78                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total           78                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data          548                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total          548                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data          626                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total          626                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data          626                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total          626                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data          712                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total          712                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1098                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         1098                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data         1810                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total         1810                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data         1810                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total         1810                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     51193764                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total     51193764                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     85249250                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total     85249250                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data    136443014                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total    136443014                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data    136443014                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total    136443014                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000025                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000089                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000089                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.000044                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.000044                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71901.353933                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71901.353933                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77640.482696                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77640.482696                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75382.880663                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75382.880663                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75382.880663                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75382.880663                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements              2891                       # number of replacements
system.cpu.icache.tags.tagsinuse          1424.909254                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            71597357                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs              4688                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          15272.473763                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1424.909254                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.695756                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.695756                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1797                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           60                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          490                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          129                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1067                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.877441                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         143208780                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        143208780                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     71597357                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        71597357                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      71597357                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         71597357                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     71597357                       # number of overall hits
system.cpu.icache.overall_hits::total        71597357                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         4689                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          4689                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         4689                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           4689                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         4689                       # number of overall misses
system.cpu.icache.overall_misses::total          4689                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    200362248                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    200362248                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    200362248                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    200362248                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    200362248                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    200362248                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     71602046                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     71602046                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     71602046                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     71602046                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     71602046                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     71602046                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000065                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000065                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000065                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000065                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000065                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000065                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42730.272553                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 42730.272553                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 42730.272553                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 42730.272553                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 42730.272553                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 42730.272553                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4689                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total         4689                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst         4689                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total         4689                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst         4689                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total         4689                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    192401752                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    192401752                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    192401752                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    192401752                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    192401752                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    192401752                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000065                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000065                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000065                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000065                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000065                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000065                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41032.576669                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41032.576669                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41032.576669                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 41032.576669                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41032.576669                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 41032.576669                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse         2001.520500                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs               2606                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs             2787                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.935056                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks     3.029170                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  1507.676368                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data   490.814962                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.000092                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.046011                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.014978                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.061082                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024         2787                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           68                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          520                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3          157                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2005                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.085052                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses            56005                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses           56005                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst         2525                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data           80                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total           2605                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks           16                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total           16                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data            8                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total            8                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst         2525                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data           88                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total            2613                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         2525                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data           88                       # number of overall hits
system.cpu.l2cache.overall_hits::total           2613                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         2164                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data          632                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         2796                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data         1090                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         1090                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2164                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         1722                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          3886                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2164                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         1722                       # number of overall misses
system.cpu.l2cache.overall_misses::total         3886                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    161201250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data     49637250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    210838500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     84065750                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total     84065750                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    161201250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data    133703000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    294904250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    161201250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data    133703000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    294904250                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst         4689                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data          712                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total         5401                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks           16                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total           16                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data         1098                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         1098                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         4689                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data         1810                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total         6499                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         4689                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data         1810                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total         6499                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.461506                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.887640                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.517682                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.992714                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.992714                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.461506                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.951381                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.597938                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.461506                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.951381                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.597938                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74492.259704                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78539.952532                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 75407.188841                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77124.541284                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77124.541284                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74492.259704                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77644.018583                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 75888.896037                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74492.259704                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77644.018583                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 75888.896037                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           14                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           16                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           14                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           16                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           14                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           16                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2162                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          618                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         2780                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1090                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         1090                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2162                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         1708                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         3870                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2162                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         1708                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total         3870                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    134008500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     40696500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    174705000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     70436750                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     70436750                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    134008500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    111133250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    245141750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    134008500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    111133250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    245141750                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.461079                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.867978                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.514719                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.992714                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.992714                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.461079                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.943646                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.595476                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.461079                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.943646                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.595476                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61983.580019                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65851.941748                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62843.525180                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64620.871560                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64620.871560                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61983.580019                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65066.305621                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63344.121447                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61983.580019                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65066.305621                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63344.121447                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq           5401                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp          5400                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback           16                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq         1098                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp         1098                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         9377                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3636                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total             13013                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       300032                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       116864                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total             416896                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples         6515                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3               6515    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total           6515                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy        3273500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       7496248                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy       3020486                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.membus.trans_dist::ReadReq                2779                       # Transaction distribution
system.membus.trans_dist::ReadResp               2779                       # Transaction distribution
system.membus.trans_dist::ReadExReq              1090                       # Transaction distribution
system.membus.trans_dist::ReadExResp             1090                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         7738                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                   7738                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       247616                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                  247616                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples              3869                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                    3869    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                3869                       # Request fanout histogram
system.membus.reqLayer0.occupancy             4526500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy           20559250                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------