path: root/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.131746                       # Number of seconds simulated
sim_ticks                                131745950000                       # Number of ticks simulated
final_tick                               131745950000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 165378                       # Simulator instruction rate (inst/s)
host_op_rate                                   174335                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              126440065                       # Simulator tick rate (ticks/s)
host_mem_usage                                 304748                       # Number of bytes of host memory used
host_seconds                                  1041.96                       # Real time elapsed on the host
sim_insts                                   172317809                       # Number of instructions simulated
sim_ops                                     181650742                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            138176                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            109312                       # Number of bytes read from this memory
system.physmem.bytes_read::total               247488                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       138176                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          138176                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst               2159                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               1708                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                  3867                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst              1048806                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data               829718                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1878525                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         1048806                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            1048806                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             1048806                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data              829718                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                1878525                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                          3867                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                        3867                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                   247488                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                    247488                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                 305                       # Per bank write bursts
system.physmem.perBankRdBursts::1                 217                       # Per bank write bursts
system.physmem.perBankRdBursts::2                 135                       # Per bank write bursts
system.physmem.perBankRdBursts::3                 313                       # Per bank write bursts
system.physmem.perBankRdBursts::4                 308                       # Per bank write bursts
system.physmem.perBankRdBursts::5                 305                       # Per bank write bursts
system.physmem.perBankRdBursts::6                 273                       # Per bank write bursts
system.physmem.perBankRdBursts::7                 222                       # Per bank write bursts
system.physmem.perBankRdBursts::8                 249                       # Per bank write bursts
system.physmem.perBankRdBursts::9                 218                       # Per bank write bursts
system.physmem.perBankRdBursts::10                295                       # Per bank write bursts
system.physmem.perBankRdBursts::11                199                       # Per bank write bursts
system.physmem.perBankRdBursts::12                183                       # Per bank write bursts
system.physmem.perBankRdBursts::13                218                       # Per bank write bursts
system.physmem.perBankRdBursts::14                224                       # Per bank write bursts
system.physmem.perBankRdBursts::15                203                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    131745861500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                    3867                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                      3616                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       238                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        13                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples          912                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      269.543860                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     178.691365                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     273.658023                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127            266     29.17%     29.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255          353     38.71%     67.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           82      8.99%     76.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           61      6.69%     83.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639           33      3.62%     87.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767           27      2.96%     90.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895           14      1.54%     91.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023           19      2.08%     93.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151           57      6.25%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total            912                       # Bytes accessed per row activation
system.physmem.totQLat                       28130750                       # Total ticks spent queuing
system.physmem.totMemAccLat                 100637000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                     19335000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        7274.57                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  26024.57                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.88                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.88                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.01                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                       2950                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   76.29                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                     34069268.55                       # Average gap between requests
system.physmem.pageHitRate                      76.29                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                    3092040                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                    1687125                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                  16177200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy             8604835200                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             3575900700                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy            75909402750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy              88111095015                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.807422                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   126280313250                       # Time in different power states
system.physmem_0.memoryStateTime::REF      4399200000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT      1064296750                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                    3787560                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                    2066625                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                  13767000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy             8604835200                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy             3595739265                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy            75892008750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy              88112204400                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.815773                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   126251429250                       # Time in different power states
system.physmem_1.memoryStateTime::REF      4399200000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT      1093059250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                49935043                       # Number of BP lookups
system.cpu.branchPred.condPredicted          39664695                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           5744224                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             24405530                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                23309445                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             95.508866                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1908457                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                139                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  400                       # Number of system calls
system.cpu.numCycles                        263491900                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   172317809                       # Number of instructions committed
system.cpu.committedOps                     181650742                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      11758002                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                               1.529104                       # CPI: cycles per instruction
system.cpu.ipc                               0.653978                       # IPC: instructions per cycle
system.cpu.tickCycles                       257145198                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                         6346702                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements                42                       # number of replacements
system.cpu.dcache.tags.tagsinuse          1377.772724                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            40762987                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs              1810                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs          22520.987293                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  1377.772724                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.336370                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.336370                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         1768                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           37                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           83                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3          271                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4         1358                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.431641                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          81532656                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         81532656                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     28355530                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        28355530                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     12362643                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       12362643                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        22407                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        22407                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      40718173                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         40718173                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     40718173                       # number of overall hits
system.cpu.dcache.overall_hits::total        40718173                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data          792                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total           792                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data         1644                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total         1644                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data         2436                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total           2436                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data         2436                       # number of overall misses
system.cpu.dcache.overall_misses::total          2436                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data     54011984                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total     54011984                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data    115610250                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total    115610250                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data    169622234                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total    169622234                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data    169622234                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total    169622234                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     28356322                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     28356322                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22407                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        22407                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     40720609                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     40720609                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     40720609                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     40720609                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000028                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000028                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000133                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.000133                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.000060                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.000060                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.000060                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.000060                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68196.949495                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 68196.949495                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70322.536496                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 70322.536496                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 69631.458949                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 69631.458949                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 69631.458949                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 69631.458949                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks           16                       # number of writebacks
system.cpu.dcache.writebacks::total                16                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data           80                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total           80                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data          546                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total          546                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data          626                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total          626                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data          626                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total          626                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data          712                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total          712                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1098                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         1098                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data         1810                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total         1810                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data         1810                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total         1810                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     47293264                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total     47293264                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     76508500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total     76508500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data    123801764                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total    123801764                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data    123801764                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total    123801764                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000025                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000089                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000089                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.000044                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.000044                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66423.123596                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66423.123596                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69679.872495                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69679.872495                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68398.764641                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 68398.764641                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68398.764641                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 68398.764641                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements              2909                       # number of replacements
system.cpu.icache.tags.tagsinuse          1424.880841                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            71614329                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs              4705                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          15220.898831                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1424.880841                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.695743                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.695743                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1796                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           60                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          492                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          125                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1068                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.876953                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         143242775                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        143242775                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     71614329                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        71614329                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      71614329                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         71614329                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     71614329                       # number of overall hits
system.cpu.icache.overall_hits::total        71614329                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         4706                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          4706                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         4706                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           4706                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         4706                       # number of overall misses
system.cpu.icache.overall_misses::total          4706                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    186377497                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    186377497                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    186377497                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    186377497                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    186377497                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    186377497                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     71619035                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     71619035                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     71619035                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     71619035                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     71619035                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     71619035                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000066                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000066                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000066                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000066                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000066                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000066                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39604.228007                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 39604.228007                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 39604.228007                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 39604.228007                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 39604.228007                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 39604.228007                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4706                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total         4706                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst         4706                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total         4706                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst         4706                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total         4706                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    176047503                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    176047503                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    176047503                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    176047503                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    176047503                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    176047503                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000066                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000066                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000066                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37409.159159                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37409.159159                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37409.159159                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 37409.159159                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37409.159159                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 37409.159159                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse         2001.520471                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs               2624                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs             2785                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.942190                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks     3.029184                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  1507.649056                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data   490.842232                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.000092                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.046010                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.014979                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.061082                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024         2785                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           67                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          522                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3          153                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2005                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.084991                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses            56139                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses           56139                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst         2543                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data           80                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total           2623                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks           16                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total           16                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data            8                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total            8                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst         2543                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data           88                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total            2631                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         2543                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data           88                       # number of overall hits
system.cpu.l2cache.overall_hits::total           2631                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         2163                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data          632                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         2795                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data         1090                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         1090                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2163                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         1722                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          3885                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2163                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         1722                       # number of overall misses
system.cpu.l2cache.overall_misses::total         3885                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    145907500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data     45776750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    191684250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     75329000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total     75329000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    145907500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data    121105750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    267013250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    145907500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data    121105750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    267013250                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst         4706                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data          712                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total         5418                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks           16                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total           16                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data         1098                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         1098                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         4706                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data         1810                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total         6516                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         4706                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data         1810                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total         6516                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.459626                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.887640                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.515873                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.992714                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.992714                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.459626                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.951381                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.596225                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.459626                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.951381                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.596225                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67456.079519                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72431.566456                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68581.127013                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69109.174312                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69109.174312                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67456.079519                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70328.542393                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 68729.279279                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67456.079519                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70328.542393                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 68729.279279                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            3                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           14                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           17                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            3                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           14                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           17                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           14                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           17                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2160                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          618                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         2778                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1090                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         1090                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2160                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         1708                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         3868                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2160                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         1708                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total         3868                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    118562000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     37228000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    155790000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     61501500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     61501500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    118562000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     98729500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    217291500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    118562000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     98729500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    217291500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.458989                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.867978                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.512735                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.992714                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.992714                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.458989                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.943646                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.593616                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.458989                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.943646                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.593616                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54889.814815                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60239.482201                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56079.913607                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56423.394495                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56423.394495                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54889.814815                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57804.156909                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56176.706308                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54889.814815                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57804.156909                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56176.706308                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq           5418                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp          5417                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback           16                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq         1098                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp         1098                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         9411                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3636                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total             13047                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       301120                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       116864                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total             417984                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples         6532                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               5                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::5               6532    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            5                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total           6532                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy        3282000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       7517497                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy       2996736                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.membus.trans_dist::ReadReq                2777                       # Transaction distribution
system.membus.trans_dist::ReadResp               2777                       # Transaction distribution
system.membus.trans_dist::ReadExReq              1090                       # Transaction distribution
system.membus.trans_dist::ReadExResp             1090                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         7734                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                   7734                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       247488                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                  247488                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples              3867                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                    3867    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                3867                       # Request fanout histogram
system.membus.reqLayer0.occupancy             4723500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy           36361000                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------