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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.088753 # Number of seconds simulated
sim_ticks 88752965000 # Number of ticks simulated
final_tick 88752965000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 137389 # Simulator instruction rate (inst/s)
host_op_rate 150427 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 70763677 # Simulator tick rate (ticks/s)
host_mem_usage 230996 # Number of bytes of host memory used
host_seconds 1254.22 # Real time elapsed on the host
sim_insts 172315134 # Number of instructions simulated
sim_ops 188668617 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 245120 # Number of bytes read from this memory
system.physmem.bytes_inst_read 132800 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.physmem.num_reads 3830 # Number of read requests responded to by this memory
system.physmem.num_writes 0 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 2761823 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 1496288 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 2761823 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 177505931 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 95571520 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 75157417 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 6614903 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 45712904 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 43519744 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 4405793 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 115592 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 39981641 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 379098511 # Number of instructions fetch has processed
system.cpu.fetch.Branches 95571520 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 47925537 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 80419547 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 27360994 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 36321255 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 9619 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.CacheLines 36794328 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 1674379 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 177448059 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.339145 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.059886 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 97198391 54.78% 54.78% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 5418485 3.05% 57.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 10378909 5.85% 63.68% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 10238278 5.77% 69.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 8615978 4.86% 74.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 6776678 3.82% 78.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 6211591 3.50% 81.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 8309244 4.68% 86.31% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 24300505 13.69% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 177448059 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.538413 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.135695 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 46244696 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 34742594 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 74394013 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1503955 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 20562801 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 14594283 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 162509 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 391670680 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 678477 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 20562801 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 52453090 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 543058 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 28975165 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 69650922 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 5263023 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 366605935 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 86833 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 2872425 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 626371131 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1557311065 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1540047768 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 17263297 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 298063520 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 328307611 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2289898 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2280879 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 22663777 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 42181045 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 15903489 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 4032649 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2834648 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 323955475 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2094173 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 249134070 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 566766 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 135834494 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 345192034 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 457957 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 177448059 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.403983 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.631604 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 78553048 44.27% 44.27% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 28575726 16.10% 60.37% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 26790293 15.10% 75.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 21442072 12.08% 87.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 12420165 7.00% 94.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 5896079 3.32% 97.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 3065113 1.73% 99.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 544695 0.31% 99.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 160868 0.09% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 177448059 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 586662 26.53% 26.53% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 5526 0.25% 26.78% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 26.78% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 26.78% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 26.78% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 26.78% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 26.78% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 26.78% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 26.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 26.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 26.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 26.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 26.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 26.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 26.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 26.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 26.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 26.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 26.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 26.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 139 0.01% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 26 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1170221 52.93% 79.72% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 448459 20.28% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 194883965 78.22% 78.22% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 995226 0.40% 78.62% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 33040 0.01% 78.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 164177 0.07% 78.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 253566 0.10% 78.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 76466 0.03% 78.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 466502 0.19% 79.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 206303 0.08% 79.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 71862 0.03% 79.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 79.13% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 38048843 15.27% 94.41% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 13933800 5.59% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 249134070 # Type of FU issued
system.cpu.iq.rate 1.403525 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2211033 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.008875 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 674734020 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 459694658 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 237377529 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 3759978 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2202441 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 1840495 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 249450810 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 1894293 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1632018 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 12329139 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 16500 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 13400 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 3256434 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 152 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 20562801 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 11850 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 518 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 326106294 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 1027766 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 42181045 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 15903489 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 2071684 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 91 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 257 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 13400 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 4154974 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 3938016 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 8092990 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 242315384 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 36530974 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 6818686 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 56646 # number of nop insts executed
system.cpu.iew.exec_refs 50147755 # number of memory reference insts executed
system.cpu.iew.exec_branches 53661515 # Number of branches executed
system.cpu.iew.exec_stores 13616781 # Number of stores executed
system.cpu.iew.exec_rate 1.365111 # Inst execution rate
system.cpu.iew.wb_sent 240126243 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 239218024 # cumulative count of insts written-back
system.cpu.iew.wb_producers 143974107 # num instructions producing a value
system.cpu.iew.wb_consumers 250982237 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.347662 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.573643 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 172329522 # The number of committed instructions
system.cpu.commit.commitCommittedOps 188683005 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 137423310 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1636216 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 6480810 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 156885259 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.202682 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.914186 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 79822518 50.88% 50.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 37410215 23.85% 74.73% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 15894720 10.13% 84.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 8464339 5.40% 90.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 4786654 3.05% 93.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1458057 0.93% 94.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 1746360 1.11% 95.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1243896 0.79% 96.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 6058500 3.86% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 156885259 # Number of insts commited each cycle
system.cpu.commit.committedInsts 172329522 # Number of instructions committed
system.cpu.commit.committedOps 188683005 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 42498961 # Number of memory references committed
system.cpu.commit.loads 29851906 # Number of loads committed
system.cpu.commit.membars 22408 # Number of memory barriers committed
system.cpu.commit.branches 40284104 # Number of branches committed
system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions.
system.cpu.commit.int_insts 150115909 # Number of committed integer instructions.
system.cpu.commit.function_calls 1848934 # Number of function calls committed.
system.cpu.commit.bw_lim_events 6058500 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 476927873 # The number of ROB reads
system.cpu.rob.rob_writes 672877067 # The number of ROB writes
system.cpu.timesIdled 1694 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 57872 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 172315134 # Number of Instructions Simulated
system.cpu.committedOps 188668617 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 172315134 # Number of Instructions Simulated
system.cpu.cpi 1.030124 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.030124 # CPI: Total CPI of All Threads
system.cpu.ipc 0.970757 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.970757 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1076172941 # number of integer regfile reads
system.cpu.int_regfile_writes 384809064 # number of integer regfile writes
system.cpu.fp_regfile_reads 2908130 # number of floating regfile reads
system.cpu.fp_regfile_writes 2493684 # number of floating regfile writes
system.cpu.misc_regfile_reads 462718931 # number of misc regfile reads
system.cpu.misc_regfile_writes 824878 # number of misc regfile writes
system.cpu.icache.replacements 2566 # number of replacements
system.cpu.icache.tagsinuse 1372.206162 # Cycle average of tags in use
system.cpu.icache.total_refs 36789295 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 4311 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 8533.819299 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1372.206162 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.670023 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.670023 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 36789295 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 36789295 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 36789295 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 36789295 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 36789295 # number of overall hits
system.cpu.icache.overall_hits::total 36789295 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 5033 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 5033 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 5033 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 5033 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 5033 # number of overall misses
system.cpu.icache.overall_misses::total 5033 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 109886500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 109886500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 109886500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 109886500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 109886500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 109886500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 36794328 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 36794328 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 36794328 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 36794328 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 36794328 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 36794328 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000137 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000137 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000137 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21833.200874 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21833.200874 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21833.200874 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 722 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 722 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 722 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 722 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 722 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 722 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4311 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 4311 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 4311 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 4311 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 4311 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 4311 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 78475000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 78475000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 78475000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 78475000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 78475000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 78475000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18203.433078 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18203.433078 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18203.433078 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 57 # number of replacements
system.cpu.dcache.tagsinuse 1411.383328 # Cycle average of tags in use
system.cpu.dcache.total_refs 46835892 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1864 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 25126.551502 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 1411.383328 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.344576 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.344576 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 34426629 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 34426629 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 12356789 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 12356789 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 27646 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 27646 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 24828 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 24828 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 46783418 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 46783418 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 46783418 # number of overall hits
system.cpu.dcache.overall_hits::total 46783418 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1806 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1806 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 7498 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 7498 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 9304 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9304 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9304 # number of overall misses
system.cpu.dcache.overall_misses::total 9304 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 59300000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 59300000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 235066000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 235066000 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 64000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 64000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 294366000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 294366000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 294366000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 294366000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 34428435 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 34428435 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 27648 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 27648 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 24828 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 24828 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 46792722 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 46792722 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 46792722 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 46792722 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000052 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000606 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000072 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000199 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000199 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32834.994463 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31350.493465 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32000 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31638.650043 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31638.650043 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 20 # number of writebacks
system.cpu.dcache.writebacks::total 20 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1032 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1032 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6408 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 6408 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 7440 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 7440 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 7440 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 7440 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 774 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1090 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1090 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1864 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1864 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1864 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1864 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24612000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 24612000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 38340000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 38340000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62952000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 62952000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62952000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 62952000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31798.449612 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35174.311927 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33772.532189 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33772.532189 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 1984.437698 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2319 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2759 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.840522 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 4.039076 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1445.465976 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 534.932646 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.000123 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.044112 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.016325 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.060560 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 2233 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 85 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2318 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 20 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 20 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2233 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 93 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2326 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2233 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 93 # number of overall hits
system.cpu.l2cache.overall_hits::total 2326 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 2078 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 689 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 2767 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 1082 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1082 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 2078 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1771 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 3849 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2078 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1771 # number of overall misses
system.cpu.l2cache.overall_misses::total 3849 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71213500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23628000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 94841500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 37178000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 37178000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 71213500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 60806000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 132019500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 71213500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 60806000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 132019500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 4311 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 774 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 5085 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 20 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 20 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1090 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1090 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 4311 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1864 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 6175 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 4311 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1864 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 6175 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.482023 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.890181 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992661 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.482023 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.950107 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.482023 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.950107 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34270.211742 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34293.178520 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34360.443623 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34270.211742 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34334.274421 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34270.211742 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34334.274421 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 16 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 19 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 16 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 16 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 19 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2075 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 673 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 2748 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1082 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1082 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2075 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1755 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 3830 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2075 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1755 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 3830 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 64436000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20976000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 85412000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33589000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33589000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64436000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54565000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 119001000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64436000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54565000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 119001000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.481327 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869509 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992661 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.481327 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941524 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.481327 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941524 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31053.493976 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31167.904903 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31043.438078 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31053.493976 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31091.168091 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31053.493976 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31091.168091 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|
