path: root/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.074149                       # Number of seconds simulated
sim_ticks                                 74148853000                       # Number of ticks simulated
final_tick                                74148853000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  87257                       # Simulator instruction rate (inst/s)
host_op_rate                                    95539                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               37550131                       # Simulator tick rate (ticks/s)
host_mem_usage                                 292636                       # Number of bytes of host memory used
host_seconds                                  1974.66                       # Real time elapsed on the host
sim_insts                                   172303021                       # Number of instructions simulated
sim_ops                                     188656503                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            131648                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            111744                       # Number of bytes read from this memory
system.physmem.bytes_read::total               243392                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       131648                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          131648                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst               2057                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               1746                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                  3803                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst              1775456                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1507023                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3282478                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         1775456                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            1775456                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             1775456                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1507023                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3282478                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                          3804                       # Total number of read requests seen
system.physmem.writeReqs                            0                       # Total number of write requests seen
system.physmem.cpureqs                           3804                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                       243392                       # Total number of bytes read from memory
system.physmem.bytesWritten                         0                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd                 243392                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                   319                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                   234                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                   190                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                   235                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                   227                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                   193                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                   221                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                   282                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                   243                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                   247                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                  249                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                  261                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                  249                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                  234                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                  181                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                  239                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                    0                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
system.physmem.totGap                     74148834500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                    3804                       # Categorize read packet sizes
system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # categorize write packet sizes
system.physmem.writePktSize::1                      0                       # categorize write packet sizes
system.physmem.writePktSize::2                      0                       # categorize write packet sizes
system.physmem.writePktSize::3                      0                       # categorize write packet sizes
system.physmem.writePktSize::4                      0                       # categorize write packet sizes
system.physmem.writePktSize::5                      0                       # categorize write packet sizes
system.physmem.writePktSize::6                      0                       # categorize write packet sizes
system.physmem.writePktSize::7                      0                       # categorize write packet sizes
system.physmem.writePktSize::8                      0                       # categorize write packet sizes
system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::6                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
system.physmem.rdQLenPdf::0                      2808                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       800                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       151                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        38                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                       11954297                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                  86040297                       # Sum of mem lat for all requests
system.physmem.totBusLat                     15216000                       # Total cycles spent in databus access
system.physmem.totBankLat                    58870000                       # Total cycles spent in bank access
system.physmem.avgQLat                        3142.56                       # Average queueing delay per request
system.physmem.avgBankLat                    15475.81                       # Average bank access latency per request
system.physmem.avgBusLat                      4000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  22618.37                       # Average memory access latency
system.physmem.avgRdBW                           3.28                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                   3.28                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   0.00                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        16000.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
system.physmem.avgWrQLen                         0.00                       # Average write queue length over time
system.physmem.readRowHits                       3306                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   86.91                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                     19492332.94                       # Average gap between requests
system.cpu.branchPred.lookups                94799058                       # Number of BP lookups
system.cpu.branchPred.condPredicted          74801869                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           6279291                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             44724397                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                43048437                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             96.252694                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 4355507                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              88338                       # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  400                       # Number of system calls
system.cpu.numCycles                        148297707                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           39650853                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      380235632                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    94799058                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           47403944                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      80363745                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                27281096                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles                7190522                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                   43                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles          5914                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles            1                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles           51                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  36846162                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               1830987                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          148197153                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.802808                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.153253                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 68002614     45.89%     45.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  5258973      3.55%     49.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 10529156      7.10%     56.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 10279296      6.94%     63.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  8665155      5.85%     69.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  6547882      4.42%     73.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  6243481      4.21%     77.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  8012637      5.41%     83.36% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 24657959     16.64%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            148197153                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.639248                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        2.564002                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 45504222                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles               5859124                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  74799977                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               1201103                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               20832727                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             14326960                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                164415                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              392837219                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                734618                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles               20832727                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 50888432                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                  722612                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         592441                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  70554465                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               4606476                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              371355589                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                    30                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 339881                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               3653545                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents                8                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           631848996                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1581867929                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1564559444                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups          17308485                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             298044139                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                333804857                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              25175                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          25171                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  13001756                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             43004891                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            16418786                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           5685881                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          3634471                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  329217927                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               47188                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 249444233                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            790071                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       139538270                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    362161071                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           1972                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     148197153                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.683192                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.761683                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            56041941     37.82%     37.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            22617532     15.26%     53.08% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            24819018     16.75%     69.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            20330052     13.72%     83.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            12543560      8.46%     92.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             6522981      4.40%     96.41% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             4027974      2.72%     99.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             1111240      0.75%     99.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              182855      0.12%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       148197153                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  964308     38.46%     38.46% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                   5601      0.22%     38.68% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     38.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     38.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     38.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     38.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     38.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     38.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     38.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     38.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     38.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     38.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     38.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     38.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     38.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     38.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     38.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     38.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     38.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     38.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd               100      0.00%     38.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     38.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     38.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     38.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     38.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc               48      0.00%     38.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     38.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     38.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     38.69% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                1163168     46.39%     85.08% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                374037     14.92%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             194888705     78.13%     78.13% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               979440      0.39%     78.52% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     78.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     78.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     78.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     78.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     78.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     78.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     78.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     78.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     78.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     78.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     78.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     78.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     78.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     78.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     78.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     78.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     78.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     78.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd           33084      0.01%     78.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     78.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp          164341      0.07%     78.60% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt          254530      0.10%     78.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv           76430      0.03%     78.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc         465703      0.19%     78.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult         206396      0.08%     79.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc        71859      0.03%     79.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt            320      0.00%     79.03% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             38355599     15.38%     94.41% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            13947826      5.59%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              249444233                       # Type of FU issued
system.cpu.iq.rate                           1.682051                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2507262                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.010051                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          646645921                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         466634028                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    237875698                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads             3737031                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes            2187759                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses      1841461                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              250076224                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                 1875271                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          2007740                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     13155407                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        11336                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        18867                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      3774152                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads           17                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked            95                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               20832727                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                   16956                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                   865                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           329282292                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            783571                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              43004891                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             16418786                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              24780                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                    182                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                   273                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          18867                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        3889474                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      3759056                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              7648530                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             242951850                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              36852953                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           6492383                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                         17177                       # number of nop insts executed
system.cpu.iew.exec_refs                     50499895                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 53421871                       # Number of branches executed
system.cpu.iew.exec_stores                   13646942                       # Number of stores executed
system.cpu.iew.exec_rate                     1.638271                       # Inst execution rate
system.cpu.iew.wb_sent                      240774594                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     239717159                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 148465347                       # num instructions producing a value
system.cpu.iew.wb_consumers                 267264848                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.616459                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.555499                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       140611386                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           45216                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           6125994                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    127364426                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.481347                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.186226                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     57685030     45.29%     45.29% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     31666758     24.86%     70.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     13788542     10.83%     80.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      7634444      5.99%     86.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      4378206      3.44%     90.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1321179      1.04%     91.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1702157      1.34%     92.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      1312824      1.03%     93.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      7875286      6.18%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    127364426                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            172317409                       # Number of instructions committed
system.cpu.commit.committedOps              188670891                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       42494118                       # Number of memory references committed
system.cpu.commit.loads                      29849484                       # Number of loads committed
system.cpu.commit.membars                       22408                       # Number of memory barriers committed
system.cpu.commit.branches                   40300311                       # Number of branches committed
system.cpu.commit.fp_insts                    1752310                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 150106217                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1848934                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               7875286                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    448766216                       # The number of ROB reads
system.cpu.rob.rob_writes                   679506166                       # The number of ROB writes
system.cpu.timesIdled                            2556                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          100554                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   172303021                       # Number of Instructions Simulated
system.cpu.committedOps                     188656503                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             172303021                       # Number of Instructions Simulated
system.cpu.cpi                               0.860680                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.860680                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.161872                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.161872                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1079384127                       # number of integer regfile reads
system.cpu.int_regfile_writes               384869699                       # number of integer regfile writes
system.cpu.fp_regfile_reads                   2912697                       # number of floating regfile reads
system.cpu.fp_regfile_writes                  2497246                       # number of floating regfile writes
system.cpu.misc_regfile_reads                54493639                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 820036                       # number of misc regfile writes
system.cpu.icache.replacements                   2375                       # number of replacements
system.cpu.icache.tagsinuse               1350.215949                       # Cycle average of tags in use
system.cpu.icache.total_refs                 36840897                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                   4105                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                8974.639951                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst    1350.215949                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.659285                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.659285                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     36840897                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        36840897                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      36840897                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         36840897                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     36840897                       # number of overall hits
system.cpu.icache.overall_hits::total        36840897                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         5265                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          5265                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         5265                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           5265                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         5265                       # number of overall misses
system.cpu.icache.overall_misses::total          5265                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    158318499                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    158318499                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    158318499                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    158318499                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    158318499                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    158318499                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     36846162                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     36846162                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     36846162                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     36846162                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     36846162                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     36846162                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000143                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000143                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000143                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000143                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000143                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000143                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30069.990313                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 30069.990313                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 30069.990313                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 30069.990313                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 30069.990313                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 30069.990313                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          679                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                18                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    37.722222                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1159                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         1159                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         1159                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         1159                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         1159                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         1159                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4106                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total         4106                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst         4106                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total         4106                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst         4106                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total         4106                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    121527999                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    121527999                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    121527999                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    121527999                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    121527999                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    121527999                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000111                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000111                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000111                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000111                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000111                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000111                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29597.661715                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29597.661715                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29597.661715                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 29597.661715                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29597.661715                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 29597.661715                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.tagsinuse              1964.083296                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                    2132                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                  2732                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  0.780381                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks     4.995038                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   1428.113595                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data    530.974663                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.000152                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.043583                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.016204                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.059939                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst         2043                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data           88                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total           2131                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks           18                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total           18                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data            9                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total            9                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst         2043                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data           97                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total            2140                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         2043                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data           97                       # number of overall hits
system.cpu.l2cache.overall_hits::total           2140                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         2063                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data          677                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         2740                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data         1080                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         1080                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2063                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         1757                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          3820                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2063                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         1757                       # number of overall misses
system.cpu.l2cache.overall_misses::total         3820                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     96979500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data     34478500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    131458000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     46382000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total     46382000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     96979500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data     80860500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    177840000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     96979500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data     80860500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    177840000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst         4106                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data          765                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total         4871                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks           18                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total           18                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data         1089                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         1089                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         4106                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data         1854                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total         5960                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         4106                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data         1854                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total         5960                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.502435                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.884967                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.562513                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.991736                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.991736                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.502435                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.947681                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.640940                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.502435                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.947681                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.640940                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47008.967523                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50928.360414                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 47977.372263                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42946.296296                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42946.296296                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47008.967523                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46021.912351                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 46554.973822                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47008.967523                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46021.912351                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 46554.973822                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            5                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           11                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           16                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            5                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           11                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           16                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            5                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           11                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           16                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2058                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          666                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         2724                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1080                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         1080                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2058                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         1746                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         3804                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2058                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         1746                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total         3804                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     70489427                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     25721458                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     96210885                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     32841183                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     32841183                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     70489427                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     58562641                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    129052068                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     70489427                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     58562641                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    129052068                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.501218                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.870588                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.559228                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.991736                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.991736                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.501218                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.941748                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.638255                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.501218                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.941748                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.638255                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34251.422255                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38620.807808                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35319.708150                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30408.502778                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30408.502778                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34251.422255                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33541.031501                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33925.359621                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34251.422255                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33541.031501                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33925.359621                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                     58                       # number of replacements
system.cpu.dcache.tagsinuse               1406.419520                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 46792514                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                   1854                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs               25238.680690                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    1406.419520                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.343364                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.343364                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     34391106                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        34391106                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     12356535                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       12356535                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        22466                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        22466                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      46747641                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         46747641                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     46747641                       # number of overall hits
system.cpu.dcache.overall_hits::total        46747641                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data         1904                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total          1904                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data         7752                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total         7752                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data         9656                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total           9656                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data         9656                       # number of overall misses
system.cpu.dcache.overall_misses::total          9656                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data     84169500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total     84169500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data    293859496                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total    293859496                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       102000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       102000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data    378028996                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total    378028996                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data    378028996                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total    378028996                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     34393010                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     34393010                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22468                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        22468                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     46757297                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     46757297                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     46757297                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     46757297                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000055                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000055                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000627                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.000627                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000089                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000089                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.000207                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.000207                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.000207                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.000207                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44206.670168                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 44206.670168                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37907.571723                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 37907.571723                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        51000                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        51000                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 39149.647473                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 39149.647473                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39149.647473                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 39149.647473                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          472                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets           34                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                13                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    36.307692                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets           17                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks           18                       # number of writebacks
system.cpu.dcache.writebacks::total                18                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data         1138                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total         1138                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6664                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total         6664                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data         7802                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total         7802                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data         7802                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total         7802                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data          766                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total          766                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1088                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         1088                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data         1854                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total         1854                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data         1854                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total         1854                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     36187000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total     36187000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     47523998                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total     47523998                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data     83710998                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total     83710998                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data     83710998                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total     83710998                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000022                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000022                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000088                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000088                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000040                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.000040                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000040                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.000040                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47241.514360                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47241.514360                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43680.145221                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43680.145221                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45151.563107                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 45151.563107                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45151.563107                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 45151.563107                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------