path: root/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.085986                       # Number of seconds simulated
sim_ticks                                 85986203000                       # Number of ticks simulated
final_tick                                85986203000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 210936                       # Simulator instruction rate (inst/s)
host_op_rate                                   222361                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              105265513                       # Simulator tick rate (ticks/s)
host_mem_usage                                 272504                       # Number of bytes of host memory used
host_seconds                                   816.85                       # Real time elapsed on the host
sim_insts                                   172303022                       # Number of instructions simulated
sim_ops                                     181635954                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED  85986203000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst            651776                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            193408                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher        71680                       # Number of bytes read from this memory
system.physmem.bytes_read::total               916864                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       651776                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          651776                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst              10184                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               3022                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher         1120                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                 14326                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst              7580007                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2249291                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher       833622                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                10662920                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         7580007                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            7580007                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             7580007                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2249291                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher       833622                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               10662920                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                         14327                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                       14327                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                   916928                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                    916928                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                1379                       # Per bank write bursts
system.physmem.perBankRdBursts::1                 501                       # Per bank write bursts
system.physmem.perBankRdBursts::2                5100                       # Per bank write bursts
system.physmem.perBankRdBursts::3                 815                       # Per bank write bursts
system.physmem.perBankRdBursts::4                2265                       # Per bank write bursts
system.physmem.perBankRdBursts::5                 427                       # Per bank write bursts
system.physmem.perBankRdBursts::6                 394                       # Per bank write bursts
system.physmem.perBankRdBursts::7                 623                       # Per bank write bursts
system.physmem.perBankRdBursts::8                 270                       # Per bank write bursts
system.physmem.perBankRdBursts::9                 230                       # Per bank write bursts
system.physmem.perBankRdBursts::10                354                       # Per bank write bursts
system.physmem.perBankRdBursts::11                345                       # Per bank write bursts
system.physmem.perBankRdBursts::12                321                       # Per bank write bursts
system.physmem.perBankRdBursts::13                266                       # Per bank write bursts
system.physmem.perBankRdBursts::14                239                       # Per bank write bursts
system.physmem.perBankRdBursts::15                798                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     85986194000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                   14327                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     12781                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      1074                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       181                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        85                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        61                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        42                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                        35                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                        32                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                        31                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples         8483                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      107.969350                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      86.508882                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     122.734500                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127           5897     69.52%     69.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         2092     24.66%     94.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383          251      2.96%     97.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           65      0.77%     97.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639           38      0.45%     98.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767           36      0.42%     98.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895           15      0.18%     98.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023           10      0.12%     99.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151           79      0.93%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total           8483                       # Bytes accessed per row activation
system.physmem.totQLat                     1497477800                       # Total ticks spent queuing
system.physmem.totMemAccLat                1766109050                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                     71635000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                      104521.38                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                 123271.38                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          10.66                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       10.66                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.08                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.08                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                       5838                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   40.75                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                      6001688.70                       # Average gap between requests
system.physmem.pageHitRate                      40.75                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                   51557940                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                   27392310                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                  82138560                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           5188176240.000001                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             1121049780                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy              275286240                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy       12230933460                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy        8389841280                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy         9251896980                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy              36621408690                       # Total energy per rank (pJ)
system.physmem_0.averagePower              425.898657                       # Core power per rank (mW)
system.physmem_0.totalIdleTime            82802255264                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE      532741000                       # Time in different power states
system.physmem_0.memoryStateTime::REF      2206324000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF    34133171250                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN  21848572364                       # Time in different power states
system.physmem_0.memoryStateTime::ACT       443169236                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN  26822225150                       # Time in different power states
system.physmem_1.actEnergy                    9046380                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                    4800675                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                  20149080                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           880164480.000000                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy              198118890                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy               50592480                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy        1982659500                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy        1381296480                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy        18795083175                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy              23322152130                       # Total energy per rank (pJ)
system.physmem_1.averagePower              271.231327                       # Core power per rank (mW)
system.physmem_1.totalIdleTime            85419499755                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE      100592000                       # Time in different power states
system.physmem_1.memoryStateTime::REF       374546000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF    77474388250                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN   3597111150                       # Time in different power states
system.physmem_1.memoryStateTime::ACT        91565245                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN   4348000355                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED  85986203000                       # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups                85644201                       # Number of BP lookups
system.cpu.branchPred.condPredicted          68263451                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           5948841                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             39900262                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                38156956                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             95.630841                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 3658994                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              81907                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups          654149                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits             629298                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses            24851                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted        40566                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  85986203000                       # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED  85986203000                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  85986203000                       # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED  85986203000                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.numSyscalls                   400                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON     85986203000                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                        171972407                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles            5684699                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      346733793                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    85644201                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           42445248                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     158074641                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                11911485                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                 4331                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingQuiesceStallCycles           80                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles         4750                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  78152122                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                 17905                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          169724243                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.137034                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.057596                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 18311667     10.79%     10.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 29948653     17.65%     28.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 31633861     18.64%     47.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 89830062     52.93%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            169724243                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.498011                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        2.016218                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 17545924                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              18077628                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 121579812                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               6764631                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                5756248                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             32661376                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                214759                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              304427843                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts              27289068                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                5756248                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 37507593                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 8946109                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         602389                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 108088153                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               8823751                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              276998119                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts              13097154                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents               3089202                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 850461                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                2596711                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                  40764                       # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents            26854                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           480912034                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1185877305                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        296009785                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups           3004340                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             292976929                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                187935105                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              23572                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          23567                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  13428642                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             33801265                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            14384966                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           2539582                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          1819756                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  263460878                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               45929                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 214221426                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           5142742                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        81870853                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    215931448                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            713                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     169724243                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.262173                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.018049                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            53012533     31.23%     31.23% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            36041444     21.24%     52.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            65469642     38.57%     91.04% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            13608265      8.02%     99.06% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             1546158      0.91%     99.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5               45935      0.03%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                 266      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            6                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       169724243                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                35637562     66.14%     66.14% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                 153239      0.28%     66.43% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     66.43% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     66.43% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     66.43% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     66.43% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     66.43% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMultAcc                 0      0.00%     66.43% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     66.43% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMisc                    0      0.00%     66.43% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     66.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     66.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     66.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     66.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     66.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     66.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     66.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     66.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     66.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     66.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     66.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     66.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd              1065      0.00%     66.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     66.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp             35742      0.07%     66.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt               263      0.00%     66.50% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv               201      0.00%     66.50% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc              559      0.00%     66.50% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult            40182      0.07%     66.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             4      0.00%     66.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     66.57% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               13886588     25.77%     92.34% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               3846845      7.14%     99.48% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemRead            141772      0.26%     99.75% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemWrite           136229      0.25%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             166877725     77.90%     77.90% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               919560      0.43%     78.33% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     78.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     78.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     78.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     78.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     78.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMultAcc               0      0.00%     78.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     78.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMisc                  0      0.00%     78.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     78.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     78.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     78.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     78.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     78.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     78.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     78.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     78.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     78.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     78.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     78.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     78.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd           33017      0.02%     78.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     78.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp          165187      0.08%     78.42% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt          245719      0.11%     78.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv           76018      0.04%     78.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc         460300      0.21%     78.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult         206641      0.10%     78.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc        71623      0.03%     78.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt            318      0.00%     78.92% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             31220842     14.57%     93.49% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            13220710      6.17%     99.66% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemRead          576371      0.27%     99.93% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemWrite         147395      0.07%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              214221426                       # Type of FU issued
system.cpu.iq.rate                           1.245673                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    53880251                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.251517                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          653198075                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         343375917                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    204156399                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads             3992013                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes            2008700                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses      1806249                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              265928183                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                 2173494                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1586831                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      5905121                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         6947                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation         7000                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1740332                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        25012                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked           810                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                5756248                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 5611049                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                173372                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           263527171                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              33801265                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             14384966                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              23521                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                   3789                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                166382                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents           7000                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        3130012                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      3255540                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              6385552                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             206995589                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              30591856                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           7225837                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                         20364                       # number of nop insts executed
system.cpu.iew.exec_refs                     43730352                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 44853428                       # Number of branches executed
system.cpu.iew.exec_stores                   13138496                       # Number of stores executed
system.cpu.iew.exec_rate                     1.203656                       # Inst execution rate
system.cpu.iew.wb_sent                      206269583                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     205962648                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 129302452                       # num instructions producing a value
system.cpu.iew.wb_consumers                 221536410                       # num instructions consuming a value
system.cpu.iew.wb_rate                       1.197649                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.583662                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts        68402964                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           45216                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           5749347                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    158452610                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.146402                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.651768                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     73893836     46.63%     46.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     41104048     25.94%     72.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     22555911     14.24%     86.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      9496527      5.99%     92.80% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      3557786      2.25%     95.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      2129951      1.34%     96.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1320929      0.83%     97.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      1010558      0.64%     97.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      3383064      2.14%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    158452610                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            172317410                       # Number of instructions committed
system.cpu.commit.committedOps              181650342                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       40540778                       # Number of memory references committed
system.cpu.commit.loads                      27896144                       # Number of loads committed
system.cpu.commit.membars                       22408                       # Number of memory barriers committed
system.cpu.commit.branches                   40300312                       # Number of branches committed
system.cpu.commit.fp_insts                    1752310                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 143085667                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1848934                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        138987813     76.51%     76.51% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          908940      0.50%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMultAcc            0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMisc             0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd        32754      0.02%     77.03% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     77.03% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp       154829      0.09%     77.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt       238880      0.13%     77.25% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv        76016      0.04%     77.29% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc       437591      0.24%     77.53% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult       200806      0.11%     77.64% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc        71617      0.04%     77.68% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt          318      0.00%     77.68% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        27348059     15.06%     92.74% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       12498388      6.88%     99.62% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemRead       548085      0.30%     99.92% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemWrite       146246      0.08%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         181650342                       # Class of committed instruction
system.cpu.commit.bw_lim_events               3383064                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                    405117651                       # The number of ROB reads
system.cpu.rob.rob_writes                   511394543                       # The number of ROB writes
system.cpu.timesIdled                            9924                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         2248164                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   172303022                       # Number of Instructions Simulated
system.cpu.committedOps                     181635954                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.998081                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.998081                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.001922                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.001922                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                218599432                       # number of integer regfile reads
system.cpu.int_regfile_writes               114087616                       # number of integer regfile writes
system.cpu.fp_regfile_reads                   2903991                       # number of floating regfile reads
system.cpu.fp_regfile_writes                  2441715                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 707769294                       # number of cc regfile reads
system.cpu.cc_regfile_writes                229397390                       # number of cc regfile writes
system.cpu.misc_regfile_reads                57427586                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 820036                       # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  85986203000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements             72391                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.400200                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            40997604                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs             72903                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            562.358257                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         554902500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.400200                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.998829                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.998829                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          162                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          230                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3           44                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4           22                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          82292817                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         82292817                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  85986203000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data     28611296                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        28611296                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     12341384                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       12341384                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data          362                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total           362                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        22154                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        22154                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      40952680                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         40952680                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     40953042                       # number of overall hits
system.cpu.dcache.overall_hits::total        40953042                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data        89081                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total         89081                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data        22903                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total        22903                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data          117                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total          117                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data          253                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total          253                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data       111984                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         111984                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       112101                       # number of overall misses
system.cpu.dcache.overall_misses::total        112101                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   1981259500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   1981259500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data    246570499                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total    246570499                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      2257000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total      2257000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data   2227829999                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total   2227829999                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data   2227829999                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total   2227829999                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     28700377                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     28700377                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data          479                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total          479                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22407                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        22407                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     41064664                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     41064664                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     41065143                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     41065143                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003104                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.003104                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001852                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.001852                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.244259                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.244259                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.011291                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.011291                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.002727                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.002727                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.002730                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.002730                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22241.100796                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 22241.100796                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10765.860324                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 10765.860324                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  8920.948617                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  8920.948617                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19894.181303                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 19894.181303                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19873.417713                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 19873.417713                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          180                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets        11209                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets             865                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs           90                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    12.958382                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks        72391                       # number of writebacks
system.cpu.dcache.writebacks::total             72391                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        24849                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        24849                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        14345                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        14345                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          253                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total          253                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data        39194                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total        39194                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data        39194                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total        39194                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data        64232                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total        64232                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         8558                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         8558                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          114                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total          114                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data        72790                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total        72790                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data        72904                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total        72904                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1056234000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   1056234000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     88380499                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total     88380499                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       977000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       977000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data   1144614499                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total   1144614499                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data   1145591499                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total   1145591499                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002238                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002238                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000692                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000692                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.237996                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.237996                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001773                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.001773                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001775                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.001775                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16444.046581                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16444.046581                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10327.237556                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10327.237556                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  8570.175439                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  8570.175439                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15724.886647                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 15724.886647                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15713.698823                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15713.698823                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  85986203000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements             53106                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.578015                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            78094905                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             53618                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs           1456.505371                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       85215430500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.578015                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.997223                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.997223                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           82                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          103                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          276                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4           49                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         156357779                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        156357779                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  85986203000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst     78094905                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        78094905                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      78094905                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         78094905                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     78094905                       # number of overall hits
system.cpu.icache.overall_hits::total        78094905                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        57175                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         57175                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        57175                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          57175                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        57175                       # number of overall misses
system.cpu.icache.overall_misses::total         57175                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   2239186435                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   2239186435                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   2239186435                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   2239186435                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   2239186435                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   2239186435                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     78152080                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     78152080                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     78152080                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     78152080                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     78152080                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     78152080                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000732                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000732                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000732                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000732                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000732                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000732                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39163.733013                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 39163.733013                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 39163.733013                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 39163.733013                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 39163.733013                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 39163.733013                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        91615                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets           88                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs              3140                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               3                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    29.176752                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets    29.333333                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks        53106                       # number of writebacks
system.cpu.icache.writebacks::total             53106                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3554                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         3554                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         3554                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         3554                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         3554                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         3554                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        53621                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        53621                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        53621                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        53621                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        53621                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        53621                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2047106952                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   2047106952                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2047106952                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   2047106952                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2047106952                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   2047106952                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000686                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000686                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000686                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000686                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000686                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000686                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38177.336342                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38177.336342                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38177.336342                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 38177.336342                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38177.336342                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 38177.336342                       # average overall mshr miss latency
system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED  85986203000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.prefetcher.num_hwpf_issued         9132                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified         9132                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage         1308                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  85986203000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse         1811.625085                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs              98153                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs             2844                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            34.512307                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks  1727.578627                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher    84.046457                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.105443                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.005130                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.110573                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022          138                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024         2706                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1           15                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2           46                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4           77                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          135                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          283                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1128                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3          205                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4          955                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.008423                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.165161                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses          3980963                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses         3980963                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  85986203000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks        64558                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total        64558                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks        50469                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total        50469                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         8390                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         8390                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        43430                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total        43430                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data        61482                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total        61482                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst        43430                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data        69872                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          113302                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        43430                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data        69872                       # number of overall hits
system.cpu.l2cache.overall_hits::total         113302                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data            1                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total            1                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data          236                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total          236                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        10190                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        10190                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data         2795                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total         2795                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst        10190                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         3031                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total         13221                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        10190                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         3031                       # number of overall misses
system.cpu.l2cache.overall_misses::total        13221                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     21033000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total     21033000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1708556000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   1708556000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data    553419500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total    553419500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1708556000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data    574452500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   2283008500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1708556000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data    574452500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   2283008500                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks        64558                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total        64558                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks        50469                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total        50469                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data            1                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total            1                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data         8626                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         8626                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        53620                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total        53620                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        64277                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total        64277                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        53620                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data        72903                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       126523                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        53620                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data        72903                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       126523                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.027359                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.027359                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.190041                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.190041                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.043484                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.043484                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.190041                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.041576                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.104495                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.190041                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.041576                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.104495                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89122.881356                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89122.881356                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 167669.872424                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 167669.872424                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 198003.398927                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 198003.398927                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 167669.872424                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 189525.734081                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 172680.470464                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 167669.872424                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 189525.734081                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 172680.470464                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data            1                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total            1                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            5                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            5                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            8                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total            8                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            5                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            9                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           14                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            5                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            9                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           14                       # number of overall MSHR hits
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher         1986                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total         1986                       # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            1                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total            1                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          235                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total          235                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        10185                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        10185                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data         2787                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total         2787                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        10185                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         3022                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total        13207                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        10185                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         3022                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher         1986                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total        15193                       # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher     99174661                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total     99174661                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        16000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        16000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     19399000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     19399000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1646592500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1646592500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data    536158000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total    536158000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1646592500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    555557000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   2202149500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1646592500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    555557000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher     99174661                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   2301324161                       # number of overall MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.027243                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.027243                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.189948                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.189948                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.043359                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.043359                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.189948                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.041452                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.104384                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.189948                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.041452                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.120081                       # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 49936.888721                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 49936.888721                       # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        16000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        16000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82548.936170                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82548.936170                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 161668.384880                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 161668.384880                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 192378.184428                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 192378.184428                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 161668.384880                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 183837.524818                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 166741.084273                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 161668.384880                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 183837.524818                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 49936.888721                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 151472.662476                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests       252022                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests       125518                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        10474                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops          866                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops          865                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            1                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  85986203000                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp        117896                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty        64558                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean        60939                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq         2337                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq            1                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp            1                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq         8626                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp         8626                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq        53621                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq        64277                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       160345                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       218199                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total            378544                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      6830336                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      9298816                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total           16129152                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                        2338                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic                    64                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples       128862                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.088172                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.283573                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0             117501     91.18%     91.18% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1              11360      8.82%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  1      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total         128862                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy      251508000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      80437981                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy     109359491                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.membus.snoop_filter.tot_requests         14328                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests        10478                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED  85986203000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp              14090                       # Transaction distribution
system.membus.trans_dist::UpgradeReq                1                       # Transaction distribution
system.membus.trans_dist::ReadExReq               235                       # Transaction distribution
system.membus.trans_dist::ReadExResp              235                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         14092                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        28653                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                  28653                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       916800                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                  916800                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples             14328                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                   14328    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total               14328                       # Request fanout histogram
system.membus.reqLayer0.occupancy            18011178                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy           77254535                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)

---------- End Simulation Statistics   ----------