path: root/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.088632                       # Number of seconds simulated
sim_ticks                                 88632152500                       # Number of ticks simulated
final_tick                                88632152500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 134694                       # Simulator instruction rate (inst/s)
host_op_rate                                   147478                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               69281557                       # Simulator tick rate (ticks/s)
host_mem_usage                                 227272                       # Number of bytes of host memory used
host_seconds                                  1279.30                       # Real time elapsed on the host
sim_insts                                   172315139                       # Number of instructions simulated
sim_ops                                     188668622                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read                      244352                       # Number of bytes read from this memory
system.physmem.bytes_inst_read                 132032                       # Number of instructions bytes read from this memory
system.physmem.bytes_written                        0                       # Number of bytes written to this memory
system.physmem.num_reads                         3818                       # Number of read requests responded to by this memory
system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
system.physmem.num_other                            0                       # Number of other requests responded to by this memory
system.physmem.bw_read                        2756923                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read                   1489663                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total                       2756923                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  400                       # Number of system calls
system.cpu.numCycles                        177264306                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                 96525090                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted           74749964                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect            6668938                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups              46796658                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                 44215963                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                  4389679                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect              114813                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles           39966229                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      381133369                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    96525090                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           48605642                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      80754991                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                27412697                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               35762422                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                    1                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles          9389                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles            1                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.CacheLines                  36758976                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               1679336                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          177207232                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.350259                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.058598                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 96615622     54.52%     54.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  5430463      3.06%     57.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 10300720      5.81%     63.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 10325695      5.83%     69.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  8756862      4.94%     74.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  6889395      3.89%     78.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  6237128      3.52%     81.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  8634116      4.87%     86.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 24017231     13.55%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            177207232                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.544526                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        2.150085                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 46183847                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              34297054                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  74780894                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               1386206                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               20559231                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             14846637                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                165269                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              392589126                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                748420                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles               20559231                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 52356007                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                  443712                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       29007637                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  69958724                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               4881921                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              367191514                       # Number of instructions processed by rename
system.cpu.rename.IQFullEvents                  92621                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               2515930                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands           627979317                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1558602975                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1541578337                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups          17024638                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             298063528                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                329915789                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            2303042                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts        2294526                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  21773052                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             41898813                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            15562062                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           3360389                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          2124393                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  324040554                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             2103109                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 248819756                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            576048                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       136002156                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    346792965                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         466892                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     177207232                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.404117                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.633607                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            78492090     44.29%     44.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            28577659     16.13%     60.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            26660356     15.04%     75.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            21359445     12.05%     87.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            12490578      7.05%     94.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             5763951      3.25%     97.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             3149996      1.78%     99.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              544249      0.31%     99.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              168908      0.10%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       177207232                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  627952     27.03%     27.03% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                   5535      0.24%     27.27% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     27.27% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     27.27% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     27.27% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     27.27% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     27.27% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     27.27% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     27.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     27.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     27.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     27.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     27.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     27.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     27.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     27.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     27.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     27.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     27.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     27.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                48      0.00%     27.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     27.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     27.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     27.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     27.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                1      0.00%     27.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     27.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     27.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     27.27% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                1223626     52.68%     79.95% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                465789     20.05%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             194916381     78.34%     78.34% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               997256      0.40%     78.74% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     78.74% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     78.74% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     78.74% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     78.74% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     78.74% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     78.74% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     78.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     78.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     78.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     78.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     78.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     78.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     78.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     78.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     78.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     78.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     78.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     78.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd           33202      0.01%     78.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     78.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp          163976      0.07%     78.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt          252533      0.10%     78.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv           76462      0.03%     78.95% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc         463893      0.19%     79.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult         206151      0.08%     79.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc        71843      0.03%     79.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt            321      0.00%     79.25% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             37907135     15.23%     94.48% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            13730603      5.52%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              248819756                       # Type of FU issued
system.cpu.iq.rate                           1.403665                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2322951                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.009336                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          674003670                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         460004017                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    236904190                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads             3742073                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes            2153997                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses      1836768                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              249257876                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                 1884831                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1793335                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     12046906                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        20817                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        12587                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      2915006                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads          150                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               20559231                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                   11749                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                   500                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           326199297                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts           1048998                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              41898813                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             15562062                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            2080622                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                     86                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                   254                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          12587                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        4245338                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      3938864                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              8184202                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             241936044                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              36336721                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           6883712                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                         55634                       # number of nop insts executed
system.cpu.iew.exec_refs                     49775211                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 53836233                       # Number of branches executed
system.cpu.iew.exec_stores                   13438490                       # Number of stores executed
system.cpu.iew.exec_rate                     1.364832                       # Inst execution rate
system.cpu.iew.wb_sent                      239697329                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     238740958                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 143497606                       # num instructions producing a value
system.cpu.iew.wb_consumers                 250089451                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.346808                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.573785                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts      172329527                       # The number of committed instructions
system.cpu.commit.commitCommittedOps        188683010                       # The number of committed instructions
system.cpu.commit.commitSquashedInsts       137516300                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1636217                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           6533063                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    156648002                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.204503                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.917568                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     79778069     50.93%     50.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     37231664     23.77%     74.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     15824405     10.10%     84.80% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      8489087      5.42%     90.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      4756905      3.04%     93.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1480671      0.95%     94.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1767391      1.13%     95.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      1258526      0.80%     96.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      6061284      3.87%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    156648002                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            172329527                       # Number of instructions committed
system.cpu.commit.committedOps              188683010                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       42498963                       # Number of memory references committed
system.cpu.commit.loads                      29851907                       # Number of loads committed
system.cpu.commit.membars                       22408                       # Number of memory barriers committed
system.cpu.commit.branches                   40284105                       # Number of branches committed
system.cpu.commit.fp_insts                    1752310                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 150115913                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1848934                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               6061284                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    476780827                       # The number of ROB reads
system.cpu.rob.rob_writes                   673054212                       # The number of ROB writes
system.cpu.timesIdled                            1680                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           57074                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   172315139                       # Number of Instructions Simulated
system.cpu.committedOps                     188668622                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             172315139                       # Number of Instructions Simulated
system.cpu.cpi                               1.028722                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.028722                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.972080                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.972080                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1073592031                       # number of integer regfile reads
system.cpu.int_regfile_writes               384645437                       # number of integer regfile writes
system.cpu.fp_regfile_reads                   2906196                       # number of floating regfile reads
system.cpu.fp_regfile_writes                  2487132                       # number of floating regfile writes
system.cpu.misc_regfile_reads               464057527                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 824880                       # number of misc regfile writes
system.cpu.icache.replacements                   2566                       # number of replacements
system.cpu.icache.tagsinuse               1366.287383                       # Cycle average of tags in use
system.cpu.icache.total_refs                 36753975                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                   4308                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                8531.563370                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst    1366.287383                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.667133                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.667133                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     36753975                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        36753975                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      36753975                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         36753975                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     36753975                       # number of overall hits
system.cpu.icache.overall_hits::total        36753975                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         5001                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          5001                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         5001                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           5001                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         5001                       # number of overall misses
system.cpu.icache.overall_misses::total          5001                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    108825000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    108825000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    108825000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    108825000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    108825000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    108825000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     36758976                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     36758976                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     36758976                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     36758976                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     36758976                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     36758976                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000136                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000136                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000136                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21760.647870                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21760.647870                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21760.647870                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          692                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          692                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          692                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          692                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          692                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          692                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4309                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total         4309                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst         4309                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total         4309                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst         4309                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total         4309                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     78064500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     78064500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     78064500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     78064500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     78064500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     78064500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000117                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000117                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000117                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18116.616384                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18116.616384                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18116.616384                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                     55                       # number of replacements
system.cpu.dcache.tagsinuse               1415.234721                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 46401176                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                   1864                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs               24893.334764                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    1415.234721                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.345516                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.345516                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     33991693                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        33991693                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     12356758                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       12356758                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        27891                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        27891                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        24829                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        24829                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      46348451                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         46348451                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     46348451                       # number of overall hits
system.cpu.dcache.overall_hits::total        46348451                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data         1783                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total          1783                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data         7529                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total         7529                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data         9312                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total           9312                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data         9312                       # number of overall misses
system.cpu.dcache.overall_misses::total          9312                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data     58909500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total     58909500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data    235574500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total    235574500                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        64000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total        64000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data    294484000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total    294484000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data    294484000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total    294484000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     33993476                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     33993476                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        27893                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        27893                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        24829                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        24829                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     46357763                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     46357763                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     46357763                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     46357763                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000052                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000609                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000072                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.000201                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.000201                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33039.540101                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31288.949396                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        32000                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31624.140893                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31624.140893                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks           20                       # number of writebacks
system.cpu.dcache.writebacks::total                20                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data         1009                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total         1009                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6438                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total         6438                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data         7447                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total         7447                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data         7447                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total         7447                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data          774                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total          774                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1091                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         1091                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data         1865                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total         1865                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data         1865                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total         1865                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     24707500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total     24707500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     38314500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total     38314500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data     63022000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total     63022000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data     63022000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total     63022000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000023                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000088                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000040                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000040                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31921.834625                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35118.698442                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33791.957105                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33791.957105                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.tagsinuse              1978.402021                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                    2325                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                  2747                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  0.846378                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks     4.009293                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   1435.553811                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data    538.838917                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.000122                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.043810                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.016444                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.060376                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst         2242                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data           82                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total           2324                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks           20                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total           20                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data           10                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total           10                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst         2242                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data           92                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total            2334                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         2242                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data           92                       # number of overall hits
system.cpu.l2cache.overall_hits::total           2334                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         2066                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data          692                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         2758                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data            1                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total            1                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data         1080                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         1080                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2066                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         1772                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          3838                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2066                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         1772                       # number of overall misses
system.cpu.l2cache.overall_misses::total         3838                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     70811000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data     23716000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     94527000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     37109500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total     37109500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     70811000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data     60825500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    131636500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     70811000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data     60825500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    131636500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst         4308                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data          774                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total         5082                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks           20                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total           20                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data            1                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total            1                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data         1090                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         1090                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         4308                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data         1864                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total         6172                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         4308                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data         1864                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total         6172                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.479573                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.894057                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.990826                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.479573                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.950644                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.479573                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.950644                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34274.443369                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34271.676301                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34360.648148                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34274.443369                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34325.902935                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34274.443369                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34325.902935                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            3                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           17                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           20                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            3                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           17                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           20                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           17                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           20                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2063                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          675                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         2738                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            1                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total            1                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1080                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         1080                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2063                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         1755                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         3818                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2063                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         1755                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total         3818                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     64062500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     21038500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     85101000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        31000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        31000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     33524500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     33524500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     64062500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     54563000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    118625500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     64062500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     54563000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    118625500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.478877                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.872093                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.990826                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.478877                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.941524                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.478877                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.941524                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31053.078042                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31168.148148                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        31000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31041.203704                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31053.078042                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31090.028490                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31053.078042                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31090.028490                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------