path: root/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.086053                       # Number of seconds simulated
sim_ticks                                 86053034000                       # Number of ticks simulated
final_tick                                86053034000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 114393                       # Simulator instruction rate (inst/s)
host_op_rate                                   120589                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               57131119                       # Simulator tick rate (ticks/s)
host_mem_usage                                 270696                       # Number of bytes of host memory used
host_seconds                                  1506.24                       # Real time elapsed on the host
sim_insts                                   172303022                       # Number of instructions simulated
sim_ops                                     181635954                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst            652224                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            193472                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher        70848                       # Number of bytes read from this memory
system.physmem.bytes_read::total               916544                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       652224                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          652224                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst              10191                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               3023                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher         1107                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                 14321                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst              7579326                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2248288                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher       823306                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                10650920                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         7579326                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            7579326                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             7579326                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2248288                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher       823306                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               10650920                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                         14321                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                       14321                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                   916544                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                    916544                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                1378                       # Per bank write bursts
system.physmem.perBankRdBursts::1                 501                       # Per bank write bursts
system.physmem.perBankRdBursts::2                5089                       # Per bank write bursts
system.physmem.perBankRdBursts::3                 804                       # Per bank write bursts
system.physmem.perBankRdBursts::4                2285                       # Per bank write bursts
system.physmem.perBankRdBursts::5                 424                       # Per bank write bursts
system.physmem.perBankRdBursts::6                 384                       # Per bank write bursts
system.physmem.perBankRdBursts::7                 628                       # Per bank write bursts
system.physmem.perBankRdBursts::8                 270                       # Per bank write bursts
system.physmem.perBankRdBursts::9                 231                       # Per bank write bursts
system.physmem.perBankRdBursts::10                354                       # Per bank write bursts
system.physmem.perBankRdBursts::11                348                       # Per bank write bursts
system.physmem.perBankRdBursts::12                321                       # Per bank write bursts
system.physmem.perBankRdBursts::13                267                       # Per bank write bursts
system.physmem.perBankRdBursts::14                240                       # Per bank write bursts
system.physmem.perBankRdBursts::15                797                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     86052975500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                   14321                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     12787                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      1077                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       178                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        86                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        60                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        38                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                        32                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                        30                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                        29                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples         8480                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      108.022642                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      86.441459                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     123.287712                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127           5899     69.56%     69.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         2101     24.78%     94.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383          209      2.46%     96.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           89      1.05%     97.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639           41      0.48%     98.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767           36      0.42%     98.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895           15      0.18%     98.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023           13      0.15%     99.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151           77      0.91%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total           8480                       # Bytes accessed per row activation
system.physmem.totQLat                     1499260235                       # Total ticks spent queuing
system.physmem.totMemAccLat                1767778985                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                     71605000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                      104689.63                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                 123439.63                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          10.65                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       10.65                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.08                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.08                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                       5837                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   40.76                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                      6008866.39                       # Average gap between requests
system.physmem.pageHitRate                      40.76                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                   51557940                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                   27392310                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                  82060020                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           5180800560.000001                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             1120628550                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy              275264640                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy       12259963560                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy        8345872320                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy         9276913815                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy              36622770765                       # Total energy per rank (pJ)
system.physmem_0.averagePower              425.583720                       # Core power per rank (mW)
system.physmem_0.totalIdleTime            82871785017                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE      531109000                       # Time in different power states
system.physmem_0.memoryStateTime::REF      2203210000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF    34253599252                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN  21734056085                       # Time in different power states
system.physmem_0.memoryStateTime::ACT       445220983                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN  26885838680                       # Time in different power states
system.physmem_1.actEnergy                    9017820                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                    4789290                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                  20191920                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           882623040.000000                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy              198112620                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy               50847360                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy        1971627720                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy        1393669440                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy        18810725700                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy              23341907430                       # Total energy per rank (pJ)
system.physmem_1.averagePower              271.250252                       # Core power per rank (mW)
system.physmem_1.totalIdleTime            85485463257                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE      101360000                       # Time in different power states
system.physmem_1.memoryStateTime::REF       375610000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF    77532398500                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN   3629358146                       # Time in different power states
system.physmem_1.memoryStateTime::ACT        90573993                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN   4323733361                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups                85625838                       # Number of BP lookups
system.cpu.branchPred.condPredicted          68176243                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           5935432                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             39943176                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                38184524                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             95.597115                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 3683485                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              81916                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups          681521                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits             653387                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses            28134                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted        40344                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  400                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON     86053034000                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                        172106069                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles            5685351                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      347171735                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    85625838                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           42521396                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     158200265                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                11884759                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                 4008                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingQuiesceStallCycles           23                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles         4307                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  78326471                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                 18089                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          169836333                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.138878                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.056220                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 18169241     10.70%     10.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 30071574     17.71%     28.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 31598899     18.61%     47.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 89996619     52.99%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            169836333                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.497518                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        2.017196                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 17522714                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              17948295                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 121866676                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               6730979                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                5767669                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             11064280                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                189793                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              304996623                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts              27241409                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                5767669                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 37489750                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 8834769                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         601523                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 108355832                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               8786790                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              277419061                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts              13180458                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents               3061814                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 846087                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                2626546                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                  39334                       # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents            27085                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           481448286                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1187772528                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        296460965                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups           3003847                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             292976929                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                188471357                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              23624                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          23625                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  13352846                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             33915531                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            14406995                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           2538352                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          1801972                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  263797881                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               45980                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 214410891                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           5187410                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        82207907                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    216953193                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            764                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     169836333                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.262456                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.019138                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            53122752     31.28%     31.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            35940807     21.16%     52.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            65514665     38.58%     91.02% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            13639448      8.03%     99.05% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             1571104      0.93%     99.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5               47348      0.03%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                 209      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            6                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       169836333                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                35657368     66.16%     66.16% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                 153250      0.28%     66.44% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     66.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     66.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     66.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     66.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     66.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     66.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     66.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     66.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     66.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     66.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     66.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     66.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     66.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     66.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     66.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     66.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     66.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     66.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd              1065      0.00%     66.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     66.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp             35732      0.07%     66.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt               239      0.00%     66.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv               201      0.00%     66.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc              954      0.00%     66.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult            34277      0.06%     66.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             4      0.00%     66.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     66.58% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               14055726     26.08%     92.66% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               3956441      7.34%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             166991462     77.88%     77.88% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               919191      0.43%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd           33016      0.02%     78.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     78.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp          165181      0.08%     78.40% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt          245709      0.11%     78.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv           76018      0.04%     78.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc         460330      0.21%     78.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult         206622      0.10%     78.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc        71623      0.03%     78.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt            319      0.00%     78.90% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             31869240     14.86%     93.76% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            13372180      6.24%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              214410891                       # Type of FU issued
system.cpu.iq.rate                           1.245807                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    53895257                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.251364                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          653788467                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         344049655                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    204252570                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads             3952315                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes            2009022                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses      1806352                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              266172688                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                 2133460                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1598637                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      6019387                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         7380                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation         7051                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1762361                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        25560                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked           770                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                5767669                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 5624657                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                173600                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           263863986                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              33915531                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             14406995                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              23572                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                   3856                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                166551                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents           7051                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        3148917                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      3246700                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              6395617                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             207126816                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              30634090                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           7284075                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                         20125                       # number of nop insts executed
system.cpu.iew.exec_refs                     43772682                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 44853086                       # Number of branches executed
system.cpu.iew.exec_stores                   13138592                       # Number of stores executed
system.cpu.iew.exec_rate                     1.203484                       # Inst execution rate
system.cpu.iew.wb_sent                      206368979                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     206058922                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 129395738                       # num instructions producing a value
system.cpu.iew.wb_consumers                 221650226                       # num instructions consuming a value
system.cpu.iew.wb_rate                       1.197279                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.583783                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts        68671574                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           45216                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           5760722                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    158539716                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.145772                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.650496                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     73944910     46.64%     46.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     41143540     25.95%     72.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     22534900     14.21%     86.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      9516225      6.00%     92.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      3553894      2.24%     95.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      2144247      1.35%     96.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1327660      0.84%     97.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      1009164      0.64%     97.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      3365176      2.12%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    158539716                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            172317410                       # Number of instructions committed
system.cpu.commit.committedOps              181650342                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       40540778                       # Number of memory references committed
system.cpu.commit.loads                      27896144                       # Number of loads committed
system.cpu.commit.membars                       22408                       # Number of memory barriers committed
system.cpu.commit.branches                   40300312                       # Number of branches committed
system.cpu.commit.fp_insts                    1752310                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 143085667                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1848934                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        138987813     76.51%     76.51% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          908940      0.50%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd        32754      0.02%     77.03% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     77.03% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp       154829      0.09%     77.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt       238880      0.13%     77.25% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv        76016      0.04%     77.29% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc       437591      0.24%     77.53% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult       200806      0.11%     77.64% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc        71617      0.04%     77.68% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt          318      0.00%     77.68% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        27896144     15.36%     93.04% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       12644634      6.96%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         181650342                       # Class of committed instruction
system.cpu.commit.bw_lim_events               3365176                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                    405491255                       # The number of ROB reads
system.cpu.rob.rob_writes                   511954468                       # The number of ROB writes
system.cpu.timesIdled                           10012                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         2269736                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   172303022                       # Number of Instructions Simulated
system.cpu.committedOps                     181635954                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.998857                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.998857                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.001144                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.001144                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                218726711                       # number of integer regfile reads
system.cpu.int_regfile_writes               114168819                       # number of integer regfile writes
system.cpu.fp_regfile_reads                   2904003                       # number of floating regfile reads
system.cpu.fp_regfile_writes                  2441695                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 708199076                       # number of cc regfile reads
system.cpu.cc_regfile_writes                229511616                       # number of cc regfile writes
system.cpu.misc_regfile_reads                57440558                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 820036                       # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements             72579                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.404028                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            41032024                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs             73091                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            561.382715                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         516933500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.404028                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.998836                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.998836                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          161                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          230                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3           44                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4           22                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          82362375                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         82362375                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data     28645802                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        28645802                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     12341304                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       12341304                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data          364                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total           364                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        22147                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        22147                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      40987106                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         40987106                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     40987470                       # number of overall hits
system.cpu.dcache.overall_hits::total        40987470                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data        89259                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total         89259                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data        22983                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total        22983                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data          116                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total          116                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data          260                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total          260                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data       112242                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         112242                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       112358                       # number of overall misses
system.cpu.dcache.overall_misses::total        112358                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   1986737500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   1986737500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data    247540999                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total    247540999                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      2316500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total      2316500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data   2234278499                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total   2234278499                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data   2234278499                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total   2234278499                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     28735061                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     28735061                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data          480                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total          480                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22407                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        22407                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     41099348                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     41099348                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     41099828                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     41099828                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003106                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.003106                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001859                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.001859                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.241667                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.241667                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.011604                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.011604                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.002731                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.002731                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.002734                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.002734                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22258.119629                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 22258.119629                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10770.613018                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 10770.613018                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  8909.615385                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  8909.615385                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19905.904198                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 19905.904198                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19885.353059                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 19885.353059                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          180                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets        11288                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets             865                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs           90                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    13.049711                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks        72579                       # number of writebacks
system.cpu.dcache.writebacks::total             72579                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        24837                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        24837                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        14427                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        14427                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          260                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total          260                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data        39264                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total        39264                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data        39264                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total        39264                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data        64422                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total        64422                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         8556                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         8556                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          113                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total          113                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data        72978                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total        72978                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data        73091                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total        73091                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1062843500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   1062843500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     87501999                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total     87501999                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       969000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       969000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data   1150345499                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total   1150345499                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data   1151314499                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total   1151314499                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002242                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002242                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000692                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000692                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.235417                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.235417                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001776                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.001776                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001778                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.001778                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16498.145044                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16498.145044                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10226.975105                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10226.975105                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  8575.221239                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  8575.221239                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15762.907986                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 15762.907986                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15751.795693                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15751.795693                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements             53612                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.587809                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            78268729                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             54124                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs           1446.100233                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       85282294500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.587809                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.997242                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.997242                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           83                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          102                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          277                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4           49                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         156706996                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        156706996                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst     78268729                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        78268729                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      78268729                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         78268729                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     78268729                       # number of overall hits
system.cpu.icache.overall_hits::total        78268729                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        57707                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         57707                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        57707                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          57707                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        57707                       # number of overall misses
system.cpu.icache.overall_misses::total         57707                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   2245995927                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   2245995927                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   2245995927                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   2245995927                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   2245995927                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   2245995927                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     78326436                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     78326436                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     78326436                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     78326436                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     78326436                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     78326436                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000737                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000737                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000737                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000737                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000737                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000737                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38920.684267                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 38920.684267                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 38920.684267                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 38920.684267                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 38920.684267                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 38920.684267                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        93822                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets           55                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs              3270                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    28.691743                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets    27.500000                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks        53612                       # number of writebacks
system.cpu.icache.writebacks::total             53612                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3582                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         3582                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         3582                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         3582                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         3582                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         3582                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        54125                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        54125                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        54125                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        54125                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        54125                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        54125                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2049967950                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   2049967950                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2049967950                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   2049967950                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2049967950                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   2049967950                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000691                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000691                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000691                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000691                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000691                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000691                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37874.696536                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37874.696536                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37874.696536                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 37874.696536                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37874.696536                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 37874.696536                       # average overall mshr miss latency
system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.prefetcher.num_hwpf_issued         9207                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified         9207                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage         1345                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse         1792.687270                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs              99060                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs             2834                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            34.954128                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks  1727.437863                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher    65.249406                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.105434                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.003983                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.109417                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022          128                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024         2706                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1           26                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2           48                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4           54                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          139                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          283                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1127                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3          200                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4          957                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.007812                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.165161                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses          4003735                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses         4003735                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks        64697                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total        64697                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks        51019                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total        51019                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         8384                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         8384                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        43929                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total        43929                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data        61675                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total        61675                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst        43929                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data        70059                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          113988                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        43929                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data        70059                       # number of overall hits
system.cpu.l2cache.overall_hits::total         113988                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data          239                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total          239                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        10196                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        10196                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data         2793                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total         2793                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst        10196                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         3032                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total         13228                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        10196                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         3032                       # number of overall misses
system.cpu.l2cache.overall_misses::total        13228                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     20303000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total     20303000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1707637000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   1707637000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data    558453500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total    558453500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1707637000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data    578756500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   2286393500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1707637000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data    578756500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   2286393500                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks        64697                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total        64697                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks        51019                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total        51019                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data         8623                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         8623                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        54125                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total        54125                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        64468                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total        64468                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        54125                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data        73091                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       127216                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        54125                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data        73091                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       127216                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.027717                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.027717                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.188379                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.188379                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.043324                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.043324                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.188379                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.041483                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.103981                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.188379                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.041483                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.103981                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84949.790795                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84949.790795                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 167481.071008                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 167481.071008                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 199947.547440                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 199947.547440                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 167481.071008                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 190882.750660                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 172844.987904                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 167481.071008                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 190882.750660                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 172844.987904                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data            1                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total            1                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            5                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            5                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            8                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total            8                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            5                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            9                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           14                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            5                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            9                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           14                       # number of overall MSHR hits
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher         2057                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total         2057                       # number of HardPFReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          238                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total          238                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        10191                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        10191                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data         2785                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total         2785                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        10191                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         3023                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total        13214                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        10191                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         3023                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher         2057                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total        15271                       # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher     97518621                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total     97518621                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     18660000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     18660000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1645631000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1645631000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data    541204500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total    541204500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1645631000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    559864500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   2205495500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1645631000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    559864500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher     97518621                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   2303014121                       # number of overall MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.027601                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.027601                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.188286                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.188286                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.043200                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.043200                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.188286                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.041359                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.103871                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.188286                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.041359                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.120040                       # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47408.177443                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 47408.177443                       # average HardPFReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78403.361345                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78403.361345                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 161478.853891                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 161478.853891                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 194328.366248                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 194328.366248                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 161478.853891                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185201.620906                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 166905.970940                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 161478.853891                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185201.620906                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47408.177443                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 150809.647109                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests       253407                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests       126211                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        10475                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops          950                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops          949                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            1                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp        118592                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty        64697                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean        61494                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq         2394                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq         8623                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp         8623                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq        54125                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq        64468                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       161861                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       218761                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total            380622                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      6895104                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      9322880                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total           16217984                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                        2394                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples       129610                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.088311                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.283775                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0             118165     91.17%     91.17% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1              11444      8.83%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  1      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total         129610                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy      252894500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      81192487                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy     109641490                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.membus.snoop_filter.tot_requests         14321                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests        10482                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED  86053034000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp              14082                       # Transaction distribution
system.membus.trans_dist::ReadExReq               238                       # Transaction distribution
system.membus.trans_dist::ReadExResp              238                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         14083                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        28641                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                  28641                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       916480                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                  916480                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples             14321                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                   14321    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total               14321                       # Request fanout histogram
system.membus.reqLayer0.occupancy            18093154                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy           77218560                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)

---------- End Simulation Statistics   ----------