path: root/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.071387                       # Number of seconds simulated
sim_ticks                                 71387376000                       # Number of ticks simulated
final_tick                                71387376000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  91858                       # Simulator instruction rate (inst/s)
host_op_rate                                    96834                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               38058123                       # Simulator tick rate (ticks/s)
host_mem_usage                                 257304                       # Number of bytes of host memory used
host_seconds                                  1875.75                       # Real time elapsed on the host
sim_insts                                   172303021                       # Number of instructions simulated
sim_ops                                     181635953                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            130496                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            111040                       # Number of bytes read from this memory
system.physmem.bytes_read::total               241536                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       130496                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          130496                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst               2039                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               1735                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                  3774                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst              1827998                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1555457                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3383455                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         1827998                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            1827998                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             1827998                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1555457                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3383455                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                          3774                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                        3774                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                   241536                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                    241536                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs             60                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                 313                       # Per bank write bursts
system.physmem.perBankRdBursts::1                 214                       # Per bank write bursts
system.physmem.perBankRdBursts::2                 128                       # Per bank write bursts
system.physmem.perBankRdBursts::3                 306                       # Per bank write bursts
system.physmem.perBankRdBursts::4                 297                       # Per bank write bursts
system.physmem.perBankRdBursts::5                 299                       # Per bank write bursts
system.physmem.perBankRdBursts::6                 265                       # Per bank write bursts
system.physmem.perBankRdBursts::7                 217                       # Per bank write bursts
system.physmem.perBankRdBursts::8                 243                       # Per bank write bursts
system.physmem.perBankRdBursts::9                 220                       # Per bank write bursts
system.physmem.perBankRdBursts::10                282                       # Per bank write bursts
system.physmem.perBankRdBursts::11                189                       # Per bank write bursts
system.physmem.perBankRdBursts::12                184                       # Per bank write bursts
system.physmem.perBankRdBursts::13                208                       # Per bank write bursts
system.physmem.perBankRdBursts::14                212                       # Per bank write bursts
system.physmem.perBankRdBursts::15                197                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     71387262500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                    3774                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                      2817                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       790                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       125                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        31                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        10                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples          730                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      328.591781                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     199.502533                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     324.063907                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127            243     33.29%     33.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255          162     22.19%     55.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           95     13.01%     68.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           41      5.62%     74.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639           34      4.66%     78.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767           29      3.97%     82.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895           36      4.93%     87.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023           21      2.88%     90.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151           69      9.45%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total            730                       # Bytes accessed per row activation
system.physmem.totQLat                       27328250                       # Total ticks spent queuing
system.physmem.totMemAccLat                  98090750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                     18870000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        7241.19                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  25991.19                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.38                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.38                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                       3037                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   80.47                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                     18915543.85                       # Average gap between requests
system.physmem.pageHitRate                      80.47                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE      68189011250                       # Time in different power states
system.physmem.memoryStateTime::REF        2383680000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT         812104750                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.membus.throughput                      3383455                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq                2699                       # Transaction distribution
system.membus.trans_dist::ReadResp               2699                       # Transaction distribution
system.membus.trans_dist::UpgradeReq               60                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              60                       # Transaction distribution
system.membus.trans_dist::ReadExReq              1075                       # Transaction distribution
system.membus.trans_dist::ReadExResp             1075                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         7668                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                   7668                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       241536                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total              241536                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus                 241536                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy             4574500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy           35380947                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups               106458293                       # Number of BP lookups
system.cpu.branchPred.condPredicted          82706448                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           6339444                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             50217715                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                48291708                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             96.164686                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 5164625                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              84625                       # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  400                       # Number of system calls
system.cpu.numCycles                        142774753                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           44808389                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      429802861                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   106458293                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           53456333                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      91468493                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                12731388                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                   27                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles          5563                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles            1                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles           99                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  41753796                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               1912042                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          142648266                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              3.160575                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.133574                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 53718645     37.66%     37.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  6357410      4.46%     42.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 10351894      7.26%     49.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 14920250     10.46%     59.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 10655390      7.47%     67.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  3891108      2.73%     70.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  7883355      5.53%     75.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  9310317      6.53%     82.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 25559897     17.92%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            142648266                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.745638                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        3.010356                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 37233141                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              23853545                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  68602562                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               6747325                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                6211693                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             15955000                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                160395                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              420485829                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                828178                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                6211693                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 42171212                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                18551410                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         713419                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  69222818                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               5777714                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              398176302                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                    59                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                1614739                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                2816561                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                  62575                       # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents              202                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           691997012                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1704697725                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        425662370                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups           3491733                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             292976929                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                399020083                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              28576                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          28600                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  15636023                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             44518617                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            18120521                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           7204434                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          5193927                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  353303303                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               50659                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 249217571                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            532732                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       170449002                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    473050896                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           5443                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     142648266                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.747077                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.881809                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            54008982     37.86%     37.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            21782256     15.27%     53.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            24530872     17.20%     70.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            16106640     11.29%     81.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            11858342      8.31%     89.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             6781839      4.75%     94.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             5090438      3.57%     98.26% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             1742716      1.22%     99.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              746181      0.52%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       142648266                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 1599616     44.61%     44.61% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                   5629      0.16%     44.77% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     44.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     44.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     44.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     44.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     44.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     44.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     44.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     44.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     44.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     44.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     44.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     44.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     44.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     44.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     44.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     44.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     44.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     44.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                43      0.00%     44.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     44.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     44.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                26      0.00%     44.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     44.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc             2425      0.07%     44.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     44.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     44.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     44.84% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                1462989     40.80%     85.64% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                515010     14.36%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             192832828     77.38%     77.38% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult              1041370      0.42%     77.79% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     77.79% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     77.79% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     77.79% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     77.79% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     77.79% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     77.79% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     77.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     77.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     77.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     77.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     77.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     77.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     77.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     77.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     77.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     77.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     77.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     77.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd           33133      0.01%     77.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     77.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp          164691      0.07%     77.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt          264054      0.11%     77.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv           76936      0.03%     78.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc         473853      0.19%     78.20% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult         207040      0.08%     78.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc        72084      0.03%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt            323      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             39374798     15.80%     94.11% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            14676461      5.89%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              249217571                       # Type of FU issued
system.cpu.iq.rate                           1.745530                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     3585738                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.014388                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          641399049                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         521384383                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    237201307                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads             3802829                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes            2450137                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses      1875104                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              250898873                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                 1904436                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1999527                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     16622473                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        18079                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        32569                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      5475887                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads       334532                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked           126                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                6211693                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                18514097                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                 29892                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           353371291                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            723756                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              44518617                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             18120521                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              28251                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                   2286                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 27735                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          32569                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        3999566                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      3827175                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              7826741                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             243157329                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              37609930                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           6060242                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                         17329                       # number of nop insts executed
system.cpu.iew.exec_refs                     51859202                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 55857945                       # Number of branches executed
system.cpu.iew.exec_stores                   14249272                       # Number of stores executed
system.cpu.iew.exec_rate                     1.703084                       # Inst execution rate
system.cpu.iew.wb_sent                      240511751                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     239076411                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 145760285                       # num instructions producing a value
system.cpu.iew.wb_consumers                 269855272                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.674501                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.540142                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       171723245                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           45216                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           6185443                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    117932320                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.540293                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.243745                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     51372616     43.56%     43.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     31468321     26.68%     70.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     11935963     10.12%     80.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      6951478      5.89%     86.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      3813624      3.23%     89.49% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1418078      1.20%     90.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1525333      1.29%     91.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      1616480      1.37%     93.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      7830427      6.64%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    117932320                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            172317409                       # Number of instructions committed
system.cpu.commit.committedOps              181650341                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       40540778                       # Number of memory references committed
system.cpu.commit.loads                      27896144                       # Number of loads committed
system.cpu.commit.membars                       22408                       # Number of memory barriers committed
system.cpu.commit.branches                   40300311                       # Number of branches committed
system.cpu.commit.fp_insts                    1752310                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 143085667                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1848934                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        138987812     76.51%     76.51% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          908940      0.50%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd        32754      0.02%     77.03% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     77.03% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp       154829      0.09%     77.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt       238880      0.13%     77.25% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv        76016      0.04%     77.29% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc       437591      0.24%     77.53% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult       200806      0.11%     77.64% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc        71617      0.04%     77.68% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt          318      0.00%     77.68% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        27896144     15.36%     93.04% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       12644634      6.96%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         181650341                       # Class of committed instruction
system.cpu.commit.bw_lim_events               7830427                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    463470278                       # The number of ROB reads
system.cpu.rob.rob_writes                   731648814                       # The number of ROB writes
system.cpu.timesIdled                            1645                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          126487                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   172303021                       # Number of Instructions Simulated
system.cpu.committedOps                     181635953                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.828626                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.828626                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.206817                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.206817                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                248213314                       # number of integer regfile reads
system.cpu.int_regfile_writes               133191535                       # number of integer regfile writes
system.cpu.fp_regfile_reads                   2934311                       # number of floating regfile reads
system.cpu.fp_regfile_writes                  2552498                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 830988511                       # number of cc regfile reads
system.cpu.cc_regfile_writes                255127381                       # number of cc regfile writes
system.cpu.misc_regfile_reads                66039150                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 820036                       # number of misc regfile writes
system.cpu.toL2Bus.throughput                 5345035                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq           4859                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp          4858                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback           17                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           61                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           61                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq         1087                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp         1087                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         8146                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3823                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total             11969                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       258688                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       118976                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total         377664                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus            377664                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus         3904                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy        3029000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       6522997                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy       3106540                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.icache.tags.replacements              2317                       # number of replacements
system.cpu.icache.tags.tagsinuse          1337.456920                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            41747829                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs              4039                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          10336.179500                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1337.456920                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.653055                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.653055                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1722                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           87                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          528                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3           30                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1033                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.840820                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          83511695                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         83511695                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     41748272                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        41748272                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      41748272                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         41748272                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     41748272                       # number of overall hits
system.cpu.icache.overall_hits::total        41748272                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         5524                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          5524                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         5524                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           5524                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         5524                       # number of overall misses
system.cpu.icache.overall_misses::total          5524                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    227823494                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    227823494                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    227823494                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    227823494                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    227823494                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    227823494                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     41753796                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     41753796                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     41753796                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     41753796                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     41753796                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     41753796                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000132                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000132                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000132                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000132                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000132                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000132                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41242.486242                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 41242.486242                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 41242.486242                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 41242.486242                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 41242.486242                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 41242.486242                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          857                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                18                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    47.611111                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1420                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         1420                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         1420                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         1420                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         1420                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         1420                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4104                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total         4104                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst         4104                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total         4104                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst         4104                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total         4104                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    164891501                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    164891501                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    164891501                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    164891501                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    164891501                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    164891501                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000098                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000098                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000098                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000098                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000098                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000098                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40178.240984                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40178.240984                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40178.240984                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 40178.240984                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40178.240984                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 40178.240984                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse         1935.733118                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs               2084                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs             2703                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.770995                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks     3.025142                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  1410.130158                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data   522.577818                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.000092                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.043034                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.015948                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.059074                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024         2703                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           99                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          599                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3           30                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1935                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.082489                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses            51495                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses           51495                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst         2000                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data           83                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total           2083                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks           17                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total           17                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data           12                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total           12                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst         2000                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data           95                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total            2095                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         2000                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data           95                       # number of overall hits
system.cpu.l2cache.overall_hits::total           2095                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         2043                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data          672                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         2715                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data           60                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           60                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data         1075                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         1075                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2043                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         1747                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          3790                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2043                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         1747                       # number of overall misses
system.cpu.l2cache.overall_misses::total         3790                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    140715500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data     47433250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    188148750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     74164250                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total     74164250                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    140715500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data    121597500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    262313000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    140715500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data    121597500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    262313000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst         4043                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data          755                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total         4798                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks           17                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total           17                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           61                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           61                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data         1087                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         1087                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         4043                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data         1842                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total         5885                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         4043                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data         1842                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total         5885                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.505318                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.890066                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.565861                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.983607                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.983607                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.988960                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.988960                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.505318                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.948426                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.644010                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.505318                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.948426                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.644010                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68876.896721                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70585.193452                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69299.723757                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        68990                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total        68990                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68876.896721                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69603.606182                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 69211.873351                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68876.896721                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69603.606182                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 69211.873351                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            3                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           12                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           15                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            3                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           12                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           15                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           12                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           15                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2040                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          660                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         2700                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           60                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           60                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1075                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         1075                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2040                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         1735                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         3775                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2040                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         1735                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total         3775                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    114933000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     38476250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    153409250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       623553                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       623553                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     60696250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     60696250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    114933000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     99172500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    214105500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    114933000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     99172500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    214105500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.504576                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.874172                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.562734                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.983607                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.983607                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.988960                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.988960                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.504576                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.941911                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.641461                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.504576                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.941911                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.641461                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56339.705882                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58297.348485                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56818.240741                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10392.550000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10392.550000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56461.627907                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56461.627907                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56339.705882                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57159.942363                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56716.688742                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56339.705882                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57159.942363                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56716.688742                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements                56                       # number of replacements
system.cpu.dcache.tags.tagsinuse          1395.016190                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            47368346                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs              1842                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs          25715.714441                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  1395.016190                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.340580                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.340580                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         1786                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           36                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          353                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4         1369                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.436035                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          94757994                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         94757994                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     34966407                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        34966407                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     12356440                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       12356440                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data          545                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total           545                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        22480                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        22480                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      47322847                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         47322847                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     47323392                       # number of overall hits
system.cpu.dcache.overall_hits::total        47323392                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data         1942                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total          1942                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data         7847                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total         7847                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data            6                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total            6                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data         9789                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total           9789                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data         9795                       # number of overall misses
system.cpu.dcache.overall_misses::total          9795                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data    120282480                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total    120282480                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data    504727051                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total    504727051                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       143500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       143500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data    625009531                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total    625009531                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data    625009531                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total    625009531                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     34968349                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     34968349                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data          551                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total          551                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22482                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        22482                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     47332636                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     47332636                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     47333187                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     47333187                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000056                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000056                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000635                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.000635                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.010889                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.010889                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000089                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000089                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.000207                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.000207                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.000207                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.000207                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61937.425335                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 61937.425335                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64321.020900                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 64321.020900                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        71750                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        71750                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 63848.149045                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 63848.149045                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 63809.038387                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 63809.038387                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          848                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets           85                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                16                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs           53                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    42.500000                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks           17                       # number of writebacks
system.cpu.dcache.writebacks::total                17                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data         1189                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total         1189                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6701                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total         6701                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data         7890                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total         7890                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data         7890                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total         7890                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data          753                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total          753                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1146                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         1146                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            4                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total            4                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data         1899                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total         1899                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data         1903                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total         1903                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     48859513                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total     48859513                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     76658945                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total     76658945                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       305000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       305000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data    125518458                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total    125518458                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data    125823458                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total    125823458                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000022                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000022                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000093                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000093                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.007260                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.007260                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000040                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.000040                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000040                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.000040                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64886.471448                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64886.471448                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66892.622164                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66892.622164                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        76250                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        76250                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66097.134281                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66097.134281                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66118.475039                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66118.475039                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------