path: root/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.087734                       # Number of seconds simulated
sim_ticks                                 87734048000                       # Number of ticks simulated
final_tick                                87734048000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 104988                       # Simulator instruction rate (inst/s)
host_op_rate                                   175969                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               69742772                       # Simulator tick rate (ticks/s)
host_mem_usage                                 239080                       # Number of bytes of host memory used
host_seconds                                  1257.97                       # Real time elapsed on the host
sim_insts                                   132071227                       # Number of instructions simulated
sim_ops                                     221363017                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            219520                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            125504                       # Number of bytes read from this memory
system.physmem.bytes_read::total               345024                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       219520                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          219520                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst               3430                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               1961                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                  5391                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst              2502107                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1430505                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3932612                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         2502107                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            2502107                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             2502107                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1430505                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3932612                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls                  400                       # Number of system calls
system.cpu.numCycles                        175468097                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                 20936810                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted           20936810                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect            2209025                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups              15519452                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                 13863485                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles           27317448                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      226954156                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    20936810                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           13863485                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      59860939                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                19465594                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               71226359                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                  837                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles          7164                       # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines                  25821692                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                473022                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          175391237                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.137569                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.300907                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                117206877     66.83%     66.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  3231358      1.84%     68.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  2482815      1.42%     70.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  3136542      1.79%     71.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  3542923      2.02%     73.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  3767949      2.15%     76.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  4531829      2.58%     78.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  2825666      1.61%     80.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 34665278     19.76%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            175391237                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.119320                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.293421                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 40660130                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              61009372                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  46541390                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              10201855                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               16978490                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              366073396                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles               16978490                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 48547252                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                16251189                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          23056                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  48155491                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              45435759                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              356858942                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                    31                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents               20674050                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents              22523448                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents             2249                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           506627728                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1130775437                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1120479419                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups          10296018                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             320143989                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                186483739                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               1903                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           1897                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  95061023                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             89836107                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            33126554                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          59108509                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         19466725                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  344545895                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                7937                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 270906839                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            256776                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       122697293                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    297019638                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           6691                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     175391237                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.544586                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.467556                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            49119269     28.01%     28.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            52565616     29.97%     57.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            34331484     19.57%     77.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            18982131     10.82%     88.37% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            12721464      7.25%     95.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             4942775      2.82%     98.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             2076613      1.18%     99.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              542627      0.31%     99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              109258      0.06%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       175391237                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   90563      3.50%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.50% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                2225289     85.92%     89.42% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                273998     10.58%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass           1212985      0.45%      0.45% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             176266302     65.07%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    0      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd             1595268      0.59%     66.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.10% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             68329319     25.22%     91.32% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            23502965      8.68%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              270906839                       # Type of FU issued
system.cpu.iq.rate                           1.543909                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2589850                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.009560                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          714739567                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         462675137                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    263287653                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads             5311974                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes            4876750                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses      2553148                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              269622080                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                 2661624                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         18915593                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     33186517                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        30708                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       305892                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     12610838                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        47515                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               16978490                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                  517280                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                233874                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           344553832                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            297077                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              89836107                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             33126554                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               1857                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 147591                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 33364                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         305892                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        1298592                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      1028927                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              2327519                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             267790575                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              67240366                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           3116264                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     90351837                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 14775060                       # Number of branches executed
system.cpu.iew.exec_stores                   23111471                       # Number of stores executed
system.cpu.iew.exec_rate                     1.526150                       # Inst execution rate
system.cpu.iew.wb_sent                      266714598                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     265840801                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 214478617                       # num instructions producing a value
system.cpu.iew.wb_consumers                 504376698                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.515038                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.425235                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts      132071227                       # The number of committed instructions
system.cpu.commit.commitCommittedOps        221363017                       # The number of committed instructions
system.cpu.commit.commitSquashedInsts       123301880                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls            1246                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           2209791                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    158412747                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.397381                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.795092                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     54206628     34.22%     34.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     60400758     38.13%     72.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     15586261      9.84%     82.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     12707072      8.02%     90.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      4534557      2.86%     93.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      2957745      1.87%     94.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      2082808      1.31%     96.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      1250624      0.79%     97.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      4686294      2.96%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    158412747                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            132071227                       # Number of instructions committed
system.cpu.commit.committedOps              221363017                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       77165306                       # Number of memory references committed
system.cpu.commit.loads                      56649590                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                   12326943                       # Number of branches committed
system.cpu.commit.fp_insts                    2162459                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 220339606                       # Number of committed integer instructions.
system.cpu.commit.function_calls                    0                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               4686294                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    498391350                       # The number of ROB reads
system.cpu.rob.rob_writes                   706346628                       # The number of ROB writes
system.cpu.timesIdled                            1678                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           76860                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   132071227                       # Number of Instructions Simulated
system.cpu.committedOps                     221363017                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             132071227                       # Number of Instructions Simulated
system.cpu.cpi                               1.328587                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.328587                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.752679                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.752679                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                657568441                       # number of integer regfile reads
system.cpu.int_regfile_writes               365395599                       # number of integer regfile writes
system.cpu.fp_regfile_reads                   3514318                       # number of floating regfile reads
system.cpu.fp_regfile_writes                  2225520                       # number of floating regfile writes
system.cpu.misc_regfile_reads               139440665                       # number of misc regfile reads
system.cpu.misc_regfile_writes                    844                       # number of misc regfile writes
system.cpu.icache.replacements                   5526                       # number of replacements
system.cpu.icache.tagsinuse               1631.257386                       # Cycle average of tags in use
system.cpu.icache.total_refs                 25812694                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                   7496                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                3443.529082                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst    1631.257386                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.796512                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.796512                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     25812694                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        25812694                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      25812694                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         25812694                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     25812694                       # number of overall hits
system.cpu.icache.overall_hits::total        25812694                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         8998                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          8998                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         8998                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           8998                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         8998                       # number of overall misses
system.cpu.icache.overall_misses::total          8998                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    186818500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    186818500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    186818500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    186818500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    186818500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    186818500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     25821692                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     25821692                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     25821692                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     25821692                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     25821692                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     25821692                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000348                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000348                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000348                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000348                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000348                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000348                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20762.224939                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 20762.224939                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20762.224939                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 20762.224939                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20762.224939                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 20762.224939                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1359                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         1359                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         1359                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         1359                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         1359                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         1359                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst         7639                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total         7639                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst         7639                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total         7639                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst         7639                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total         7639                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    130438500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    130438500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    130438500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    130438500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    130438500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    130438500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000296                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000296                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000296                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000296                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000296                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000296                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17075.337086                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17075.337086                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17075.337086                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 17075.337086                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17075.337086                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 17075.337086                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                     57                       # number of replacements
system.cpu.dcache.tagsinuse               1425.887115                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 68669194                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                   1998                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs               34368.965966                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    1425.887115                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.348117                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.348117                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     48154983                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        48154983                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     20514026                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       20514026                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      68669009                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         68669009                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     68669009                       # number of overall hits
system.cpu.dcache.overall_hits::total        68669009                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data          768                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total           768                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data         1704                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total         1704                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data         2472                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total           2472                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data         2472                       # number of overall misses
system.cpu.dcache.overall_misses::total          2472                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data     24800000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total     24800000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data     64672500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total     64672500                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data     89472500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     89472500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data     89472500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     89472500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     48155751                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     48155751                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     20515730                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     20515730                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     68671481                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     68671481                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     68671481                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     68671481                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000016                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000016                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000083                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.000083                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.000036                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.000036                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.000036                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.000036                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32291.666667                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 32291.666667                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37953.345070                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 37953.345070                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 36194.377023                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 36194.377023                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 36194.377023                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 36194.377023                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks           14                       # number of writebacks
system.cpu.dcache.writebacks::total                14                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data          326                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total          326                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data            3                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total            3                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data          329                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total          329                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data          329                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total          329                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data          442                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total          442                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1701                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         1701                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data         2143                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total         2143                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data         2143                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total         2143                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     14580500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total     14580500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     59464500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total     59464500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data     74045000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total     74045000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data     74045000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total     74045000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000009                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000009                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000083                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000083                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000031                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.000031                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000031                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.000031                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32987.556561                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32987.556561                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34958.553792                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34958.553792                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34552.029865                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 34552.029865                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34552.029865                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 34552.029865                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.tagsinuse              2578.525319                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                    4100                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                  3842                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  1.067153                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks     1.139953                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   2280.306781                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data    297.078586                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.000035                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.069589                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.009066                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.078690                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst         4066                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data           31                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total           4097                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks           14                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total           14                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data            8                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total            8                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst         4066                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data           39                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total            4105                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         4066                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data           39                       # number of overall hits
system.cpu.l2cache.overall_hits::total           4105                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3430                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data          410                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         3840                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data          143                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total          143                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data         1551                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         1551                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3430                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         1961                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          5391                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3430                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         1961                       # number of overall misses
system.cpu.l2cache.overall_misses::total         5391                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    117492500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data     14011500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    131504000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     52997000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total     52997000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    117492500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data     67008500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    184501000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    117492500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data     67008500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    184501000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst         7496                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data          441                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total         7937                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks           14                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total           14                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data          143                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total          143                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data         1559                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         1559                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         7496                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data         2000                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total         9496                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         7496                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data         2000                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total         9496                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.457577                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.929705                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.483810                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.994869                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.994869                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.457577                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.980500                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.567713                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.457577                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.980500                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.567713                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34254.373178                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34174.390244                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34245.833333                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34169.568021                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34169.568021                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34254.373178                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34170.576237                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34223.891671                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34254.373178                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34170.576237                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34223.891671                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3430                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          410                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         3840                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          143                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total          143                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1551                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         1551                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3430                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         1961                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         5391                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3430                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         1961                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total         5391                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    106414500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     12709500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    119124000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      4433000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      4433000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     48110500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     48110500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    106414500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     60820000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    167234500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    106414500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     60820000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    167234500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.457577                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.929705                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.483810                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994869                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994869                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.457577                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.980500                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.567713                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.457577                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.980500                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.567713                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31024.635569                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30998.780488                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31021.875000                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        31000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        31000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31019.019987                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31019.019987                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31024.635569                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31014.788373                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31021.053608                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31024.635569                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31014.788373                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31021.053608                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------