path: root/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.082776                       # Number of seconds simulated
sim_ticks                                 82776043000                       # Number of ticks simulated
final_tick                                82776043000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  77695                       # Simulator instruction rate (inst/s)
host_op_rate                                   130224                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               48695604                       # Simulator tick rate (ticks/s)
host_mem_usage                                 276624                       # Number of bytes of host memory used
host_seconds                                  1699.87                       # Real time elapsed on the host
sim_insts                                   132071192                       # Number of instructions simulated
sim_ops                                     221362961                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            217984                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            124288                       # Number of bytes read from this memory
system.physmem.bytes_read::total               342272                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       217984                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          217984                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst               3406                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               1942                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                  5348                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst              2633419                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1501497                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4134916                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         2633419                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            2633419                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             2633419                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1501497                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4134916                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                          5350                       # Total number of read requests seen
system.physmem.writeReqs                            0                       # Total number of write requests seen
system.physmem.cpureqs                           5531                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                       342272                       # Total number of bytes read from memory
system.physmem.bytesWritten                         0                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd                 342272                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite                181                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                   306                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                   318                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                   315                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                   319                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                   307                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                   368                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                   327                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                   305                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                   257                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                   278                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                  361                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                  436                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                  435                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                  352                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                  369                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                  297                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                    0                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
system.physmem.totGap                     82776014000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                    5350                       # Categorize read packet sizes
system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # categorize write packet sizes
system.physmem.writePktSize::1                      0                       # categorize write packet sizes
system.physmem.writePktSize::2                      0                       # categorize write packet sizes
system.physmem.writePktSize::3                      0                       # categorize write packet sizes
system.physmem.writePktSize::4                      0                       # categorize write packet sizes
system.physmem.writePktSize::5                      0                       # categorize write packet sizes
system.physmem.writePktSize::6                      0                       # categorize write packet sizes
system.physmem.writePktSize::7                      0                       # categorize write packet sizes
system.physmem.writePktSize::8                      0                       # categorize write packet sizes
system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::6                  181                       # categorize neither packet sizes
system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
system.physmem.rdQLenPdf::0                      4186                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       931                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       196                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        33                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                       13963836                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                 119601836                       # Sum of mem lat for all requests
system.physmem.totBusLat                     21400000                       # Total cycles spent in databus access
system.physmem.totBankLat                    84238000                       # Total cycles spent in bank access
system.physmem.avgQLat                        2610.06                       # Average queueing delay per request
system.physmem.avgBankLat                    15745.42                       # Average bank access latency per request
system.physmem.avgBusLat                      4000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  22355.48                       # Average memory access latency
system.physmem.avgRdBW                           4.13                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                   4.13                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   0.00                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        16000.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
system.physmem.avgWrQLen                         0.00                       # Average write queue length over time
system.physmem.readRowHits                       4744                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   88.67                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                     15472152.15                       # Average gap between requests
system.cpu.workload.num_syscalls                  400                       # Number of system calls
system.cpu.numCycles                        165552087                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                 19937507                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted           19937507                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect            2011224                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups              13844585                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                 13082184                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles           25823167                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      218797366                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    19937507                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           13082184                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      57543253                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                17618129                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               66723129                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                  278                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles          2032                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           86                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  24434096                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                426892                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          165432321                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.185723                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.325531                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                109484552     66.18%     66.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  3053467      1.85%     68.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  2384541      1.44%     69.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  2897248      1.75%     71.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  3448185      2.08%     73.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  3564782      2.15%     75.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  4309445      2.60%     78.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  2719256      1.64%     79.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 33570845     20.29%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            165432321                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.120430                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.321623                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 38724148                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              56736512                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  44639960                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               9991325                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               15340376                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              353466965                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles               15340376                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 46189093                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                15008557                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          23078                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  46492003                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              42379214                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              345094521                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                    78                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents               18065019                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents              22190556                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents              104                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           398767810                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             960056051                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        950296029                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups           9760022                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             259428604                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                139339206                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               1674                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           1663                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  90597841                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             86592813                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            31744520                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          57837693                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         18834679                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  333487648                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                3580                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 267379172                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            250437                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       111676069                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    229742853                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           2335                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     165432321                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.616245                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.503217                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            45038788     27.22%     27.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            46767309     28.27%     55.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            32846173     19.85%     75.35% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            19795888     11.97%     87.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            13207626      7.98%     95.30% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             4774334      2.89%     98.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             2327149      1.41%     99.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              533647      0.32%     99.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              141407      0.09%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       165432321                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  133618      5.04%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      5.04% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                2250761     84.95%     90.00% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                265061     10.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass           1212134      0.45%      0.45% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             174135882     65.13%     65.58% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    0      0.00%     65.58% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.58% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd             1593779      0.60%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             67177367     25.12%     91.30% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            23260010      8.70%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              267379172                       # Type of FU issued
system.cpu.iq.rate                           1.615076                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2649440                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.009909                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          697750591                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         440878444                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    260170034                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads             5339951                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes            4579505                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses      2570780                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              266131077                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                 2685401                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         19003165                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     29943227                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        28980                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       295958                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     11228803                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        49224                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked            13                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               15340376                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                  584172                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                263019                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           333491228                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            190803                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              86592813                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             31744520                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               1661                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 148723                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 30980                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         295958                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        1176359                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       917156                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              2093515                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             264503897                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              66194002                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           2875275                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     89062868                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 14601707                       # Number of branches executed
system.cpu.iew.exec_stores                   22868866                       # Number of stores executed
system.cpu.iew.exec_rate                     1.597708                       # Inst execution rate
system.cpu.iew.wb_sent                      263570746                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     262740814                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 211979430                       # num instructions producing a value
system.cpu.iew.wb_consumers                 374947027                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.587058                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.565358                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       112163051                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls            1245                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           2011438                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    150091945                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.474849                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.942132                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     50831007     33.87%     33.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     57256127     38.15%     72.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     13834026      9.22%     81.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     12065346      8.04%     89.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      4152706      2.77%     92.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      2955841      1.97%     94.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1060436      0.71%     94.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      1001549      0.67%     95.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      6934907      4.62%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    150091945                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            132071192                       # Number of instructions committed
system.cpu.commit.committedOps              221362961                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       77165303                       # Number of memory references committed
system.cpu.commit.loads                      56649586                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                   12326938                       # Number of branches committed
system.cpu.commit.fp_insts                    2162459                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 220339551                       # Number of committed integer instructions.
system.cpu.commit.function_calls                    0                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               6934907                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    476683050                       # The number of ROB reads
system.cpu.rob.rob_writes                   682427429                       # The number of ROB writes
system.cpu.timesIdled                            2933                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          119766                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   132071192                       # Number of Instructions Simulated
system.cpu.committedOps                     221362961                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             132071192                       # Number of Instructions Simulated
system.cpu.cpi                               1.253506                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.253506                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.797762                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.797762                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                562448945                       # number of integer regfile reads
system.cpu.int_regfile_writes               298656184                       # number of integer regfile writes
system.cpu.fp_regfile_reads                   3520617                       # number of floating regfile reads
system.cpu.fp_regfile_writes                  2230281                       # number of floating regfile writes
system.cpu.misc_regfile_reads               136958061                       # number of misc regfile reads
system.cpu.misc_regfile_writes                    844                       # number of misc regfile writes
system.cpu.icache.replacements                   4787                       # number of replacements
system.cpu.icache.tagsinuse               1623.671048                       # Cycle average of tags in use
system.cpu.icache.total_refs                 24425061                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                   6754                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                3616.384513                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst    1623.671048                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.792808                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.792808                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     24425061                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        24425061                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      24425061                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         24425061                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     24425061                       # number of overall hits
system.cpu.icache.overall_hits::total        24425061                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         9035                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          9035                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         9035                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           9035                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         9035                       # number of overall misses
system.cpu.icache.overall_misses::total          9035                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    258546498                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    258546498                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    258546498                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    258546498                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    258546498                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    258546498                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     24434096                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     24434096                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     24434096                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     24434096                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     24434096                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     24434096                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000370                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000370                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000370                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000370                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000370                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000370                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28616.103818                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 28616.103818                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 28616.103818                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 28616.103818                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 28616.103818                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 28616.103818                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          770                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                22                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs           35                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2099                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         2099                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         2099                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         2099                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         2099                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         2099                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst         6936                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total         6936                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst         6936                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total         6936                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst         6936                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total         6936                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    197636498                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    197636498                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    197636498                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    197636498                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    197636498                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    197636498                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000284                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000284                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000284                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000284                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000284                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000284                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28494.304787                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28494.304787                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28494.304787                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 28494.304787                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28494.304787                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 28494.304787                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.tagsinuse              2513.899297                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                    3380                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                  3793                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  0.891115                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks     1.852274                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   2239.000678                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data    273.046345                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.000057                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.068329                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.008333                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.076718                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst         3349                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data           28                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total           3377                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks           13                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total           13                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data            7                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total            7                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst         3349                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data           35                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total            3384                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         3349                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data           35                       # number of overall hits
system.cpu.l2cache.overall_hits::total           3384                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3406                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data          384                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         3790                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data          181                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total          181                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data         1560                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         1560                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3406                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         1944                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          5350                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3406                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         1944                       # number of overall misses
system.cpu.l2cache.overall_misses::total         5350                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    157031500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data     20920500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    177952000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     67559500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total     67559500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    157031500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data     88480000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    245511500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    157031500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data     88480000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    245511500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst         6755                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data          412                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total         7167                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks           13                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total           13                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data          181                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total          181                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data         1567                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         1567                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         6755                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data         1979                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total         8734                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         6755                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data         1979                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total         8734                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.504219                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.932039                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.528813                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.995533                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.995533                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.504219                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.982314                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.612549                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.504219                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.982314                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.612549                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46104.374633                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54480.468750                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 46953.034301                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43307.371795                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43307.371795                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46104.374633                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 45514.403292                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total        45890                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46104.374633                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 45514.403292                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total        45890                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3406                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          384                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         3790                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          181                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total          181                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1560                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         1560                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3406                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         1944                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         5350                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3406                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         1944                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total         5350                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    114067502                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     16106596                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    130174098                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      1810181                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      1810181                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     47662994                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     47662994                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    114067502                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     63769590                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    177837092                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    114067502                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     63769590                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    177837092                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.504219                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.932039                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.528813                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.995533                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.995533                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.504219                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.982314                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.612549                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.504219                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.982314                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.612549                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33490.165003                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41944.260417                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34346.727704                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30553.201282                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30553.201282                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33490.165003                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32803.287037                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33240.577944                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33490.165003                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32803.287037                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33240.577944                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                     54                       # number of replacements
system.cpu.dcache.tagsinuse               1408.542073                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 67546144                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                   1977                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs               34165.980779                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    1408.542073                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.343882                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.343882                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     47031922                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        47031922                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     20513982                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       20513982                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      67545904                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         67545904                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     67545904                       # number of overall hits
system.cpu.dcache.overall_hits::total        67545904                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data          820                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total           820                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data         1749                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total         1749                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data         2569                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total           2569                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data         2569                       # number of overall misses
system.cpu.dcache.overall_misses::total          2569                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data     36866000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total     36866000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data     76858000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total     76858000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data    113724000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total    113724000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data    113724000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total    113724000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     47032742                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     47032742                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     20515731                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     20515731                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     67548473                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     67548473                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     67548473                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     67548473                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000017                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000017                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000085                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.000085                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.000038                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.000038                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.000038                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.000038                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44958.536585                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 44958.536585                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43943.967982                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 43943.967982                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 44267.808486                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 44267.808486                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 44267.808486                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 44267.808486                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs           86                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs           43                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks           13                       # number of writebacks
system.cpu.dcache.writebacks::total                13                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data          407                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total          407                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data            2                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total            2                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data          409                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total          409                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data          409                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total          409                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data          413                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total          413                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1747                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         1747                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data         2160                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total         2160                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data         2160                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total         2160                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     21692000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total     21692000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     73250500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total     73250500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data     94942500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total     94942500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data     94942500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total     94942500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000009                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000009                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000085                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000085                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000032                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.000032                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000032                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.000032                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52523.002421                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52523.002421                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41929.307384                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41929.307384                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43954.861111                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 43954.861111                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43954.861111                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 43954.861111                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------