path: root/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.103324                       # Number of seconds simulated
sim_ticks                                103323995500                       # Number of ticks simulated
final_tick                               103323995500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 113414                       # Simulator instruction rate (inst/s)
host_op_rate                                   190092                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               88727502                       # Simulator tick rate (ticks/s)
host_mem_usage                                 308112                       # Number of bytes of host memory used
host_seconds                                  1164.51                       # Real time elapsed on the host
sim_insts                                   132071192                       # Number of instructions simulated
sim_ops                                     221363384                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 103323995500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst            232832                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            130880                       # Number of bytes read from this memory
system.physmem.bytes_read::total               363712                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       232832                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          232832                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst               3638                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               2045                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                  5683                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst              2253417                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1266695                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3520112                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         2253417                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            2253417                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             2253417                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1266695                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3520112                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                          5683                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                        5683                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                   363712                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                    363712                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                 307                       # Per bank write bursts
system.physmem.perBankRdBursts::1                 383                       # Per bank write bursts
system.physmem.perBankRdBursts::2                 475                       # Per bank write bursts
system.physmem.perBankRdBursts::3                 366                       # Per bank write bursts
system.physmem.perBankRdBursts::4                 364                       # Per bank write bursts
system.physmem.perBankRdBursts::5                 336                       # Per bank write bursts
system.physmem.perBankRdBursts::6                 422                       # Per bank write bursts
system.physmem.perBankRdBursts::7                 392                       # Per bank write bursts
system.physmem.perBankRdBursts::8                 390                       # Per bank write bursts
system.physmem.perBankRdBursts::9                 296                       # Per bank write bursts
system.physmem.perBankRdBursts::10                255                       # Per bank write bursts
system.physmem.perBankRdBursts::11                273                       # Per bank write bursts
system.physmem.perBankRdBursts::12                229                       # Per bank write bursts
system.physmem.perBankRdBursts::13                485                       # Per bank write bursts
system.physmem.perBankRdBursts::14                425                       # Per bank write bursts
system.physmem.perBankRdBursts::15                285                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    103323737000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                    5683                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                      4460                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       973                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       211                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        30                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         9                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples         1258                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      287.745628                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     162.611559                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     323.712964                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127            571     45.39%     45.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255          250     19.87%     65.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           94      7.47%     72.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           65      5.17%     77.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639           43      3.42%     81.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767           57      4.53%     85.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895           29      2.31%     88.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023           22      1.75%     89.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151          127     10.10%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total           1258                       # Bytes accessed per row activation
system.physmem.totQLat                      187208250                       # Total ticks spent queuing
system.physmem.totMemAccLat                 293764500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                     28415000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       32941.80                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  51691.80                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.52                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.52                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                       4417                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   77.72                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                     18181196.02                       # Average gap between requests
system.physmem.pageHitRate                      77.72                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                    5404980                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                    2853840                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                  21741300                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           298715040.000000                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy               95918460                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy               16609440                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy         744016440                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy         410144160                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy        24152474700                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy              25747878360                       # Total energy per rank (pJ)
system.physmem_0.averagePower              249.195533                       # Core power per rank (mW)
system.physmem_0.totalIdleTime           103070096750                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE       32003500                       # Time in different power states
system.physmem_0.memoryStateTime::REF       127050000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF   100370697500                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN   1068078250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT        94522250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN   1631644000                       # Time in different power states
system.physmem_1.actEnergy                    3634260                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                    1920270                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                  18835320                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           228031440.000000                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy               73672500                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy               12688320                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy         586536840                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy         299079840                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy        24303470280                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy              25527869070                       # Total energy per rank (pJ)
system.physmem_1.averagePower              247.066219                       # Core power per rank (mW)
system.physmem_1.totalIdleTime           103129135750                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE       24348000                       # Time in different power states
system.physmem_1.memoryStateTime::REF        96994000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF   101064274500                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN    778849000                       # Time in different power states
system.physmem_1.memoryStateTime::ACT        73295500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN   1286234500                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 103323995500                       # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups                40855234                       # Number of BP lookups
system.cpu.branchPred.condPredicted          40855234                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           6727710                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             35293159                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                       0                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct              0.000000                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 3199678                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             605841                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups        35293159                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits            9878902                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses         25414257                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted      5019418                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 103323995500                       # Cumulative time (in ticks) in various power states
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 103323995500                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 103323995500                       # Cumulative time (in ticks) in various power states
system.cpu.workload.num_syscalls                  400                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON    103323995500                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                        206647992                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           46314104                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      419677545                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    40855234                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           13078580                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     152558577                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                14911731                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                        146                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                 6162                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         75545                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles          535                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          173                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  41227932                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               1521125                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                      10                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          206411107                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              3.413574                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.660203                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 99253613     48.09%     48.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  5140686      2.49%     50.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  5371591      2.60%     53.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  5329252      2.58%     55.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  6011005      2.91%     58.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  5851603      2.83%     61.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  5726027      2.77%     64.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  4748810      2.30%     66.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 68978520     33.42%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            206411107                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.197704                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        2.030881                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 32267820                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              86650194                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  62332865                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              17704363                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                7455865                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              590435256                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles                7455865                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 42053837                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                46607662                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          29929                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  68827187                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              41436627                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              551754102                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  1587                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents               36503796                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                4817365                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                 169314                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           629088770                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1485013522                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        974082903                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups          15054868                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             259429450                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                369659320                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               2323                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           2340                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  89508181                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            128738720                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            45872059                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          77414851                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         25246681                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  490126112                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               61893                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 338153574                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           1099180                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       268824621                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    526308720                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved          60648                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     206411107                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.638253                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.802953                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            73313522     35.52%     35.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            46679908     22.62%     58.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            32876430     15.93%     74.06% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            20896006     10.12%     84.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            15048824      7.29%     91.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             8392050      4.07%     95.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             5201413      2.52%     98.06% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             2354868      1.14%     99.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             1648086      0.80%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       206411107                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  756912     19.27%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMultAcc                 0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMisc                    0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     19.27% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                2690839     68.51%     87.78% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                431049     10.97%     98.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemRead             45501      1.16%     99.91% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemWrite             3340      0.09%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass           1211791      0.36%      0.36% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             216412325     64.00%     64.36% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               800256      0.24%     64.59% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv               7047583      2.08%     66.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd             1802667      0.53%     67.21% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.21% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.21% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.21% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMultAcc               0      0.00%     67.21% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.21% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMisc                  0      0.00%     67.21% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.21% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             82552665     24.41%     91.62% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            26471074      7.83%     99.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemRead         1726255      0.51%     99.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemWrite         128958      0.04%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              338153574                       # Type of FU issued
system.cpu.iq.rate                           1.636375                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     3927641                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.011615                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          879585731                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         744431622                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    315835107                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads             8159345                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes           15410519                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses      3544176                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              336768258                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                 4101166                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         18155454                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     72089133                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        55091                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       866955                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     25356342                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        50448                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked            55                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                7455865                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                35715167                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                589866                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           490188005                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts           1248811                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             128738720                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             45872059                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              22561                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 546009                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 38338                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         866955                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        1295323                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      6857589                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              8152912                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             326241588                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              80652390                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          11911986                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                    106269865                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 18918443                       # Number of branches executed
system.cpu.iew.exec_stores                   25617475                       # Number of stores executed
system.cpu.iew.exec_rate                     1.578731                       # Inst execution rate
system.cpu.iew.wb_sent                      322387752                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     319379283                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 256328359                       # num instructions producing a value
system.cpu.iew.wb_consumers                 435429845                       # num instructions consuming a value
system.cpu.iew.wb_rate                       1.545523                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.588679                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts       268850223                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls            1245                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           6732902                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    163914906                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.350477                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.932475                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     67189595     40.99%     40.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     54970007     33.54%     74.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     13274329      8.10%     82.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     10696589      6.53%     89.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      5450081      3.32%     92.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      3128441      1.91%     94.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1086544      0.66%     95.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      1161401      0.71%     95.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      6957919      4.24%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    163914906                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            132071192                       # Number of instructions committed
system.cpu.commit.committedOps              221363384                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       77165304                       # Number of memory references committed
system.cpu.commit.loads                      56649587                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                   12326938                       # Number of branches committed
system.cpu.commit.fp_insts                    2162459                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 219019985                       # Number of committed integer instructions.
system.cpu.commit.function_calls               797818                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass      1176721      0.53%      0.53% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        134111832     60.58%     61.12% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          772953      0.35%     61.47% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv          7031501      3.18%     64.64% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd        1105073      0.50%     65.14% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     65.14% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     65.14% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     65.14% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMultAcc            0      0.00%     65.14% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     65.14% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMisc             0      0.00%     65.14% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     65.14% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        55945136     25.27%     90.41% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       20410230      9.22%     99.63% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemRead       704451      0.32%     99.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemWrite       105487      0.05%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         221363384                       # Class of committed instruction
system.cpu.commit.bw_lim_events               6957919                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                    647170594                       # The number of ROB reads
system.cpu.rob.rob_writes                  1023323556                       # The number of ROB writes
system.cpu.timesIdled                            2853                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          236885                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   132071192                       # Number of Instructions Simulated
system.cpu.committedOps                     221363384                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.564671                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.564671                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.639112                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.639112                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                524350393                       # number of integer regfile reads
system.cpu.int_regfile_writes               288862618                       # number of integer regfile writes
system.cpu.fp_regfile_reads                   4510095                       # number of floating regfile reads
system.cpu.fp_regfile_writes                  3309705                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 106995415                       # number of cc regfile reads
system.cpu.cc_regfile_writes                 65768687                       # number of cc regfile writes
system.cpu.misc_regfile_reads               176729824                       # number of misc regfile reads
system.cpu.misc_regfile_writes                   1689                       # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 103323995500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements                82                       # number of replacements
system.cpu.dcache.tags.tagsinuse          1514.501359                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            82730891                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs              2127                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs          38895.576399                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  1514.501359                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.369751                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.369751                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         2045                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           17                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           29                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          111                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3          418                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4         1470                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.499268                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         165469279                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        165469279                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 103323995500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data     62216578                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        62216578                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     20513684                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       20513684                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      82730262                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         82730262                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     82730262                       # number of overall hits
system.cpu.dcache.overall_hits::total        82730262                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data         1267                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total          1267                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data         2047                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total         2047                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data         3314                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total           3314                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data         3314                       # number of overall misses
system.cpu.dcache.overall_misses::total          3314                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data    112642500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total    112642500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data    136500000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total    136500000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data    249142500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total    249142500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data    249142500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total    249142500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     62217845                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     62217845                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     20515731                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     20515731                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     82733576                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     82733576                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     82733576                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     82733576                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000020                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000020                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000100                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.000100                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.000040                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.000040                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.000040                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.000040                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88904.893449                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 88904.893449                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66682.950660                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 66682.950660                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 75178.786964                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 75178.786964                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 75178.786964                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 75178.786964                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          331                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets          143                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 4                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    82.750000                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    71.500000                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks           17                       # number of writebacks
system.cpu.dcache.writebacks::total                17                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data          658                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total          658                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data            6                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total            6                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data          664                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total          664                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data          664                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total          664                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data          609                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total          609                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2041                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         2041                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data         2650                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total         2650                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data         2650                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total         2650                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     70639000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total     70639000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    134072000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total    134072000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data    204711000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total    204711000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data    204711000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total    204711000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000010                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000099                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000099                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000032                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.000032                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000032                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.000032                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115991.789819                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115991.789819                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65689.367957                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65689.367957                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77249.433962                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 77249.433962                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77249.433962                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 77249.433962                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 103323995500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements              6640                       # number of replacements
system.cpu.icache.tags.tagsinuse          1671.571610                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            41214631                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs              8628                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs           4776.846430                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1671.571610                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.816197                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.816197                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1988                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           96                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          156                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          860                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          163                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          713                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.970703                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          82465000                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         82465000                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 103323995500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst     41214631                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        41214631                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      41214631                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         41214631                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     41214631                       # number of overall hits
system.cpu.icache.overall_hits::total        41214631                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        13297                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         13297                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        13297                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          13297                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        13297                       # number of overall misses
system.cpu.icache.overall_misses::total         13297                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    657223000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    657223000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    657223000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    657223000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    657223000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    657223000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     41227928                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     41227928                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     41227928                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     41227928                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     41227928                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     41227928                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000323                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000323                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000323                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000323                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000323                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000323                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49426.411973                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 49426.411973                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 49426.411973                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 49426.411973                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49426.411973                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 49426.411973                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         2020                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          107                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                32                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    63.125000                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          107                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks         6640                       # number of writebacks
system.cpu.icache.writebacks::total              6640                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4152                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         4152                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         4152                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         4152                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         4152                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         4152                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst         9145                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total         9145                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst         9145                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total         9145                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst         9145                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total         9145                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    457240000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    457240000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    457240000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    457240000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    457240000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    457240000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000222                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000222                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000222                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000222                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000222                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000222                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49998.906506                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49998.906506                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49998.906506                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 49998.906506                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49998.906506                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 49998.906506                       # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 103323995500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse         3890.572014                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs              12247                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs             5683                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             2.155024                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst  2409.860843                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  1480.711171                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.073543                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.045188                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.118731                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024         5683                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          172                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1019                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3          527                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3926                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.173431                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses           149123                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses          149123                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 103323995500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks           17                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total           17                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks         6583                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total         6583                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          523                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          523                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data            7                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total            7                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         4982                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total         4982                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data           75                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total           75                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst         4982                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data           82                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total            5064                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         4982                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data           82                       # number of overall hits
system.cpu.l2cache.overall_hits::total           5064                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data         1513                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         1513                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3638                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         3638                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data          532                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total          532                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3638                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         2045                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          5683                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3638                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         2045                       # number of overall misses
system.cpu.l2cache.overall_misses::total         5683                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    125080500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total    125080500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    390212000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    390212000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     68692500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total     68692500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    390212000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data    193773000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    583985000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    390212000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data    193773000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    583985000                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks           17                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total           17                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks         6583                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total         6583                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data          523                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total          523                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data         1520                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         1520                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         8620                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total         8620                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          607                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total          607                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         8620                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data         2127                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total        10747                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         8620                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data         2127                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total        10747                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.995395                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.995395                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.422042                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.422042                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.876442                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.876442                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.422042                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.961448                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.528799                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.422042                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.961448                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.528799                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82670.522141                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82670.522141                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107260.032985                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107260.032985                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 129121.240602                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 129121.240602                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107260.032985                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94754.523227                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 102759.985923                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107260.032985                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94754.523227                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 102759.985923                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1513                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         1513                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3638                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3638                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          532                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total          532                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3638                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         2045                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         5683                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3638                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         2045                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total         5683                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    109950500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    109950500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    353832000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    353832000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     63372500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     63372500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    353832000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    173323000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    527155000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    353832000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    173323000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    527155000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.995395                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.995395                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.422042                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.422042                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.876442                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.876442                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.422042                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.961448                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.528799                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.422042                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.961448                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.528799                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72670.522141                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72670.522141                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97260.032985                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97260.032985                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 119121.240602                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 119121.240602                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97260.032985                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84754.523227                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 92759.985923                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97260.032985                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84754.523227                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 92759.985923                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests        18517                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests         6823                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1046                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 103323995500                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp          9751                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty           17                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean         6640                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict           65                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq          523                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp          523                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq         1520                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp         1520                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq         9145                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq          607                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        24404                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         5382                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total             29786                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       976576                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       137216                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total            1113792                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                         525                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic                 33600                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples        11795                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.096651                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.295495                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0              10655     90.33%     90.33% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1               1140      9.67%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total          11795                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy       15915500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      13716000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy       3452000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.membus.snoop_filter.tot_requests          5683                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 103323995500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp               4170                       # Transaction distribution
system.membus.trans_dist::ReadExReq              1513                       # Transaction distribution
system.membus.trans_dist::ReadExResp             1513                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq          4170                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        11366                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total        11366                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                  11366                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       363712                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total       363712                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                  363712                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples              5683                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                    5683    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                5683                       # Request fanout histogram
system.membus.reqLayer0.occupancy             6909500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy           30126750                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------