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---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 615 # Number of BTB hits
global.BPredUnit.BTBLookups 1663 # Number of BTB lookups
global.BPredUnit.RASInCorrect 78 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 439 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 1180 # Number of conditional branches predicted
global.BPredUnit.lookups 2032 # Number of BP lookups
global.BPredUnit.usedRAS 304 # Number of times the RAS was used to get a target.
host_inst_rate 15105 # Simulator instruction rate (inst/s)
host_mem_usage 154056 # Number of bytes of host memory used
host_seconds 0.37 # Real time elapsed on the host
host_tick_rate 3572881 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 24 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 13 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 2144 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5623 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated
sim_ticks 1331134 # Number of ticks simulated
system.cpu.commit.COM:branches 862 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 101 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 30311
system.cpu.commit.COM:committed_per_cycle.min_value 0
0 27595 9103.96%
1 1579 520.93%
2 482 159.02%
3 232 76.54%
4 131 43.22%
5 104 34.31%
6 60 19.79%
7 27 8.91%
8 101 33.32%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
system.cpu.commit.COM:count 5640 # Number of instructions committed
system.cpu.commit.COM:loads 979 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 1791 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 370 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 4834 # The number of squashed insts skipped by commit
system.cpu.committedInsts 5623 # Number of Instructions Simulated
system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
system.cpu.cpi 236.730215 # CPI: Cycles Per Instruction
system.cpu.cpi_total 236.730215 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 1606 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 7256.076023 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7095.200000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 1435 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 1240789 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.106476 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 171 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 71 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 709520 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.062267 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 8026.070225 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7200.452055 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 456 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 2857281 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.438424 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 356 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 525633 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 10.930636 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 2418 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 7776.223909 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 7139.612717 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1891 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 4098070 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.217949 # miss rate for demand accesses
system.cpu.dcache.demand_misses 527 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 354 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 1235153 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.071547 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 173 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 2418 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 7776.223909 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 7139.612717 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1891 # number of overall hits
system.cpu.dcache.overall_miss_latency 4098070 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.217949 # miss rate for overall accesses
system.cpu.dcache.overall_misses 527 # number of overall misses
system.cpu.dcache.overall_mshr_hits 354 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 1235153 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.071547 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 173 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 102.478227 # Cycle average of tags in use
system.cpu.dcache.total_refs 1891 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 17469 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 70 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 169 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 11765 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 10684 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 2098 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 907 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 200 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 61 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 2032 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 1710 # Number of cache lines fetched
system.cpu.fetch.Cycles 3962 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 268 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 12603 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 472 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.065089 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 1710 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 919 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 0.403696 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 31219
system.cpu.fetch.rateDist.min_value 0
0 28979 9282.49%
1 197 63.10%
2 198 63.42%
3 167 53.49%
4 197 63.10%
5 187 59.90%
6 222 71.11%
7 122 39.08%
8 950 304.30%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 1710 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 5139.251163 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4349.151613 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1280 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 2209878 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.251462 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 430 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 120 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 1348237 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.181287 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 310 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 4.129032 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 1710 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 5139.251163 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 4349.151613 # average overall mshr miss latency
system.cpu.icache.demand_hits 1280 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 2209878 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.251462 # miss rate for demand accesses
system.cpu.icache.demand_misses 430 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 120 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 1348237 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.181287 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 310 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 1710 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 5139.251163 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 4349.151613 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 1280 # number of overall hits
system.cpu.icache.overall_miss_latency 2209878 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.251462 # miss rate for overall accesses
system.cpu.icache.overall_misses 430 # number of overall misses
system.cpu.icache.overall_mshr_hits 120 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 1348237 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.181287 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 310 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 310 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 148.421347 # Cycle average of tags in use
system.cpu.icache.total_refs 1280 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 1299916 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 1267 # Number of branches executed
system.cpu.iew.EXEC:nop 48 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.270476 # Inst execution rate
system.cpu.iew.EXEC:refs 2748 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 1031 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 5354 # num instructions consuming a value
system.cpu.iew.WB:count 8160 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.757378 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 4055 # num instructions producing a value
system.cpu.iew.WB:rate 0.261379 # insts written-back per cycle
system.cpu.iew.WB:sent 8228 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 404 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 7230 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 2144 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 10469 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 1717 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 299 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 8444 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 907 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 81 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 60 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 1165 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 60 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 279 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.004224 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.004224 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 8743 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
(null) 2 0.02% # Type of FU issued
IntAlu 5868 67.12% # Type of FU issued
IntMult 1 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 2 0.02% # Type of FU issued
FloatCmp 0 0.00% # Type of FU issued
FloatCvt 0 0.00% # Type of FU issued
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
MemRead 1809 20.69% # Type of FU issued
MemWrite 1061 12.14% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 87 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.009951 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
IntAlu 1 1.15% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
FloatCmp 0 0.00% # attempts to use FU when none available
FloatCvt 0 0.00% # attempts to use FU when none available
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 54 62.07% # attempts to use FU when none available
MemWrite 32 36.78% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 31219
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 27042 8662.03%
1 1845 590.99%
2 1151 368.69%
3 572 183.22%
4 318 101.86%
5 182 58.30%
6 76 24.34%
7 22 7.05%
8 11 3.52%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 0.280054 # Inst issue rate
system.cpu.iq.iqInstsAdded 10397 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 8743 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 4378 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 68 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 2580 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadReq_accesses 481 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4807.594595 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2390.114345 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_miss_latency 2312453 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 481 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1149645 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 481 # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4807.594595 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2390.114345 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 2312453 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 481 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 1149645 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 481 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4807.594595 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2390.114345 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits
system.cpu.l2cache.overall_miss_latency 2312453 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 481 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 1149645 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 481 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 481 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 250.999286 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 31219 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 7810 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 2 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 10837 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 465 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 6 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 14384 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 11306 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 8499 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 2010 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 907 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 491 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 4448 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 9164 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 825 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
system.cpu.timesIdled 365 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------
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