blob: c07021f5aca91bb13c04d43c6026ba8a90a8dccf (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
|
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 524 # Number of BTB hits
global.BPredUnit.BTBLookups 1590 # Number of BTB lookups
global.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 422 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 1093 # Number of conditional branches predicted
global.BPredUnit.lookups 1843 # Number of BP lookups
global.BPredUnit.usedRAS 241 # Number of times the RAS was used to get a target.
host_inst_rate 54565 # Simulator instruction rate (inst/s)
host_mem_usage 154084 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
host_tick_rate 44392410 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 17 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 127 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 1876 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 1144 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5623 # Number of instructions simulated
sim_seconds 0.000005 # Number of seconds simulated
sim_ticks 4588000 # Number of ticks simulated
system.cpu.commit.COM:branches 862 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 104 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 8514
system.cpu.commit.COM:committed_per_cycle.min_value 0
0 6195 7276.25%
1 1158 1360.11%
2 469 550.86%
3 176 206.72%
4 131 153.86%
5 99 116.28%
6 109 128.02%
7 73 85.74%
8 104 122.15%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
system.cpu.commit.COM:count 5640 # Number of instructions committed
system.cpu.commit.COM:loads 979 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 1791 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 350 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 3588 # The number of squashed insts skipped by commit
system.cpu.committedInsts 5623 # Number of Instructions Simulated
system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
system.cpu.cpi 1.635604 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.635604 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 1475 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 5928.571429 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5385 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 1342 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 788500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.090169 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 133 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 33 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 538500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.067797 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 4501.457726 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5116.438356 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 469 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 1544000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.422414 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 343 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 270 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 373500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 10.468208 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 2287 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 4900.210084 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 5271.676301 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1811 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 2332500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.208133 # miss rate for demand accesses
system.cpu.dcache.demand_misses 476 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 303 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 912000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.075645 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 173 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 2287 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 4900.210084 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 5271.676301 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1811 # number of overall hits
system.cpu.dcache.overall_miss_latency 2332500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.208133 # miss rate for overall accesses
system.cpu.dcache.overall_misses 476 # number of overall misses
system.cpu.dcache.overall_mshr_hits 303 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 912000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.075645 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 173 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 112.670676 # Cycle average of tags in use
system.cpu.dcache.total_refs 1811 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 389 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 75 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 144 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 10499 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 6230 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 1848 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 682 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 228 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 48 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 1843 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 1471 # Number of cache lines fetched
system.cpu.fetch.Cycles 3451 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 11450 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 455 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.200391 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 1471 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 765 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.244971 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 9197
system.cpu.fetch.rateDist.min_value 0
0 7219 7849.30%
1 167 181.58%
2 147 159.83%
3 129 140.26%
4 200 217.46%
5 139 151.14%
6 181 196.80%
7 99 107.64%
8 916 995.98%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 1471 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 5375.757576 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4524.038462 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1141 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 1774000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.224337 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 330 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 1411500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.212101 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 312 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 3.657051 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 1471 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 5375.757576 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 4524.038462 # average overall mshr miss latency
system.cpu.icache.demand_hits 1141 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 1774000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.224337 # miss rate for demand accesses
system.cpu.icache.demand_misses 330 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 18 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 1411500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.212101 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 312 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 1471 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 5375.757576 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 4524.038462 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 1141 # number of overall hits
system.cpu.icache.overall_miss_latency 1774000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.224337 # miss rate for overall accesses
system.cpu.icache.overall_misses 330 # number of overall misses
system.cpu.icache.overall_mshr_hits 18 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 1411500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.212101 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 312 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 312 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 165.938349 # Cycle average of tags in use
system.cpu.icache.total_refs 1141 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 2475 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 1148 # Number of branches executed
system.cpu.iew.EXEC:nop 40 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.837338 # Inst execution rate
system.cpu.iew.EXEC:refs 2524 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 977 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 5205 # num instructions consuming a value
system.cpu.iew.WB:count 7402 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.742747 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 3866 # num instructions producing a value
system.cpu.iew.WB:rate 0.804828 # insts written-back per cycle
system.cpu.iew.WB:sent 7467 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 374 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 1876 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 315 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 1144 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 9245 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 1547 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 280 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 7701 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 682 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 50 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 63 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 897 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 332 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 63 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 111 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.611395 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.611395 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 7981 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
(null) 2 0.03% # Type of FU issued
IntAlu 5322 66.68% # Type of FU issued
IntMult 1 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 2 0.03% # Type of FU issued
FloatCmp 0 0.00% # Type of FU issued
FloatCvt 0 0.00% # Type of FU issued
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
MemRead 1662 20.82% # Type of FU issued
MemWrite 992 12.43% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 106 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.013282 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
IntAlu 0 0.00% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
FloatCmp 0 0.00% # attempts to use FU when none available
FloatCvt 0 0.00% # attempts to use FU when none available
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 71 66.98% # attempts to use FU when none available
MemWrite 35 33.02% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 9197
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 5952 6471.68%
1 1107 1203.65%
2 919 999.24%
3 442 480.59%
4 375 407.74%
5 250 271.83%
6 115 125.04%
7 26 28.27%
8 11 11.96%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 0.867783 # Inst issue rate
system.cpu.iq.iqInstsAdded 9183 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 7981 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 3171 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 22 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 2045 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadReq_accesses 483 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4639.751553 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2463.768116 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_miss_latency 2241000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 483 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1190000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 483 # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 483 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4639.751553 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2463.768116 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 2241000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 483 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 1190000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 483 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 483 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4639.751553 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2463.768116 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits
system.cpu.l2cache.overall_miss_latency 2241000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 483 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 1190000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 483 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 483 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 278.222582 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 9197 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 15 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
system.cpu.rename.RENAME:IdleCycles 6383 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 70 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 12854 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 10031 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 7485 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 1746 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 682 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 101 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 3434 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 270 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 380 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed
system.cpu.timesIdled 25 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------
|
