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---------- Begin Simulation Statistics ----------
host_inst_rate                                  53715                       # Simulator instruction rate (inst/s)
host_mem_usage                                 201548                       # Number of bytes of host memory used
host_seconds                                     0.04                       # Real time elapsed on the host
host_tick_rate                              160751052                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                        2387                       # Number of instructions simulated
sim_seconds                                  0.000007                       # Number of seconds simulated
sim_ticks                                     7183000                       # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits                      198                       # Number of BTB hits
system.cpu.BPredUnit.BTBLookups                   684                       # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect                  35                       # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect                209                       # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted                447                       # Number of conditional branches predicted
system.cpu.BPredUnit.lookups                      859                       # Number of BP lookups
system.cpu.BPredUnit.usedRAS                      165                       # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches                    396                       # Number of branches committed
system.cpu.commit.COM:bw_lim_events                38                       # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples         6196                      
system.cpu.commit.COM:committed_per_cycle::min_value            0                      
system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%           
system.cpu.commit.COM:committed_per_cycle::0-1         5239     84.55%           
system.cpu.commit.COM:committed_per_cycle::1-2          263      4.24%           
system.cpu.commit.COM:committed_per_cycle::2-3          334      5.39%           
system.cpu.commit.COM:committed_per_cycle::3-4          134      2.16%           
system.cpu.commit.COM:committed_per_cycle::4-5           73      1.18%           
system.cpu.commit.COM:committed_per_cycle::5-6           63      1.02%           
system.cpu.commit.COM:committed_per_cycle::6-7           32      0.52%           
system.cpu.commit.COM:committed_per_cycle::7-8           20      0.32%           
system.cpu.commit.COM:committed_per_cycle::8           38      0.61%           
system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%           
system.cpu.commit.COM:committed_per_cycle::total         6196                      
system.cpu.commit.COM:committed_per_cycle::max_value            8                      
system.cpu.commit.COM:committed_per_cycle::mean     0.415752                      
system.cpu.commit.COM:committed_per_cycle::stdev     1.208059                      
system.cpu.commit.COM:count                      2576                       # Number of instructions committed
system.cpu.commit.COM:loads                       415                       # Number of loads committed
system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
system.cpu.commit.COM:refs                        709                       # Number of memory references committed
system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts               132                       # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts           2576                       # The number of committed instructions
system.cpu.commit.commitNonSpecStalls               4                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts            1733                       # The number of squashed insts skipped by commit
system.cpu.committedInsts                        2387                       # Number of Instructions Simulated
system.cpu.committedInsts_total                  2387                       # Number of Instructions Simulated
system.cpu.cpi                               6.018852                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         6.018852                       # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses                573                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 35755.813953                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35680.327869                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits                    487                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency        3075000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.150087                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses                   86                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits                25                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency      2176500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.106457                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses              61                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses               294                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 37200.934579                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37675.675676                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits                   187                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency       3980500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.363946                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses                 107                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits               70                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency      1394000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.125850                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses             37                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs                   8.411765                       # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses                 867                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 36556.994819                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 36433.673469                       # average overall mshr miss latency
system.cpu.dcache.demand_hits                     674                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency         7055500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.222607                       # miss rate for demand accesses
system.cpu.dcache.demand_misses                   193                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits                 95                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency      3570500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.113033                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses               98                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses                867                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 36556.994819                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 36433.673469                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits                    674                       # number of overall hits
system.cpu.dcache.overall_miss_latency        7055500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.222607                       # miss rate for overall accesses
system.cpu.dcache.overall_misses                  193                       # number of overall misses
system.cpu.dcache.overall_mshr_hits                95                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency      3570500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.113033                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses              98                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements                      0                       # number of replacements
system.cpu.dcache.sampled_refs                     85                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse                 45.884316                       # Cycle average of tags in use
system.cpu.dcache.total_refs                      715                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                        0                       # number of writebacks
system.cpu.decode.DECODE:BlockedCycles            171                       # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred             79                       # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved           127                       # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts            4722                       # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles              5096                       # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles                929                       # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles             331                       # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts            284                       # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles              1                       # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses                      971                       # DTB accesses
system.cpu.dtb.data_acv                             1                       # DTB access violations
system.cpu.dtb.data_hits                          946                       # DTB hits
system.cpu.dtb.data_misses                         25                       # DTB misses
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.read_accesses                      611                       # DTB read accesses
system.cpu.dtb.read_acv                             1                       # DTB read access violations
system.cpu.dtb.read_hits                          600                       # DTB read hits
system.cpu.dtb.read_misses                         11                       # DTB read misses
system.cpu.dtb.write_accesses                     360                       # DTB write accesses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_hits                         346                       # DTB write hits
system.cpu.dtb.write_misses                        14                       # DTB write misses
system.cpu.fetch.Branches                         859                       # Number of branches that fetch encountered
system.cpu.fetch.CacheLines                       747                       # Number of cache lines fetched
system.cpu.fetch.Cycles                          1709                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes                   115                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts                           5393                       # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles                     240                       # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate                  0.059790                       # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles                747                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches                363                       # Number of branches that fetch has predicted taken
system.cpu.fetch.rate                        0.375374                       # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples               6528                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%            # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0-1                   5595     85.71%            # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1-2                     36      0.55%            # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2-3                    100      1.53%            # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3-4                     69      1.06%            # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4-5                    130      1.99%            # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5-6                     72      1.10%            # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6-7                     45      0.69%            # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7-8                     48      0.74%            # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                      433      6.63%            # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%            # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total                 6528                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.826134                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.219931                       # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses                747                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 35989.361702                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35298.342541                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits                    512                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency        8457500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate          0.314592                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses                  235                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits                54                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency      6389000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.242303                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses             181                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs                   2.828729                       # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses                 747                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 35989.361702                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35298.342541                       # average overall mshr miss latency
system.cpu.icache.demand_hits                     512                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency         8457500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate           0.314592                       # miss rate for demand accesses
system.cpu.icache.demand_misses                   235                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits                 54                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency      6389000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate      0.242303                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses              181                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.overall_accesses                747                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 35989.361702                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35298.342541                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits                    512                       # number of overall hits
system.cpu.icache.overall_miss_latency        8457500                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate          0.314592                       # miss rate for overall accesses
system.cpu.icache.overall_misses                  235                       # number of overall misses
system.cpu.icache.overall_mshr_hits                54                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency      6389000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate     0.242303                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses             181                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.replacements                      0                       # number of replacements
system.cpu.icache.sampled_refs                    181                       # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse                 88.727286                       # Cycle average of tags in use
system.cpu.icache.total_refs                      512                       # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks                        0                       # number of writebacks
system.cpu.idleCycles                            7839                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches                      584                       # Number of branches executed
system.cpu.iew.EXEC:nop                           286                       # number of nop insts executed
system.cpu.iew.EXEC:rate                     0.236862                       # Inst execution rate
system.cpu.iew.EXEC:refs                          974                       # number of memory reference insts executed
system.cpu.iew.EXEC:stores                        360                       # Number of stores executed
system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
system.cpu.iew.WB:consumers                      1896                       # num instructions consuming a value
system.cpu.iew.WB:count                          3311                       # cumulative count of insts written-back
system.cpu.iew.WB:fanout                     0.795886                       # average fanout of values written-back
system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers                      1509                       # num instructions producing a value
system.cpu.iew.WB:rate                       0.230459                       # insts written-back per cycle
system.cpu.iew.WB:sent                           3349                       # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts                  151                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles                      10                       # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts                   738                       # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts                  6                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts                57                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts                  411                       # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts                4323                       # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts                   614                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts               111                       # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts                  3403                       # Number of executed instructions
system.cpu.iew.iewIQFullEvents                      1                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles                    331                       # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles                     1                       # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads              27                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation           16                       # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads          323                       # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores          117                       # Number of stores squashed
system.cpu.iew.memOrderViolationEvents             16                       # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect           97                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect             54                       # Number of branches that were predicted taken incorrectly
system.cpu.ipc                               0.166145                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.166145                       # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0                    3514                       # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
                      No_OpClass            0      0.00%            # Type of FU issued
                          IntAlu         2506     71.31%            # Type of FU issued
                         IntMult            1      0.03%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd            0      0.00%            # Type of FU issued
                        FloatCmp            0      0.00%            # Type of FU issued
                        FloatCvt            0      0.00%            # Type of FU issued
                       FloatMult            0      0.00%            # Type of FU issued
                        FloatDiv            0      0.00%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead          639     18.18%            # Type of FU issued
                        MemWrite          368     10.47%            # Type of FU issued
                       IprAccess            0      0.00%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt                    34                       # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate             0.009676                       # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
                      No_OpClass            0      0.00%            # attempts to use FU when none available
                          IntAlu            1      2.94%            # attempts to use FU when none available
                         IntMult            0      0.00%            # attempts to use FU when none available
                          IntDiv            0      0.00%            # attempts to use FU when none available
                        FloatAdd            0      0.00%            # attempts to use FU when none available
                        FloatCmp            0      0.00%            # attempts to use FU when none available
                        FloatCvt            0      0.00%            # attempts to use FU when none available
                       FloatMult            0      0.00%            # attempts to use FU when none available
                        FloatDiv            0      0.00%            # attempts to use FU when none available
                       FloatSqrt            0      0.00%            # attempts to use FU when none available
                         MemRead           11     32.35%            # attempts to use FU when none available
                        MemWrite           22     64.71%            # attempts to use FU when none available
                       IprAccess            0      0.00%            # attempts to use FU when none available
                    InstPrefetch            0      0.00%            # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle::samples         6528                      
system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                      
system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%           
system.cpu.iq.ISSUE:issued_per_cycle::0-1         5051     77.37%           
system.cpu.iq.ISSUE:issued_per_cycle::1-2          569      8.72%           
system.cpu.iq.ISSUE:issued_per_cycle::2-3          331      5.07%           
system.cpu.iq.ISSUE:issued_per_cycle::3-4          253      3.88%           
system.cpu.iq.ISSUE:issued_per_cycle::4-5          172      2.63%           
system.cpu.iq.ISSUE:issued_per_cycle::5-6           97      1.49%           
system.cpu.iq.ISSUE:issued_per_cycle::6-7           39      0.60%           
system.cpu.iq.ISSUE:issued_per_cycle::7-8           11      0.17%           
system.cpu.iq.ISSUE:issued_per_cycle::8             5      0.08%           
system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%           
system.cpu.iq.ISSUE:issued_per_cycle::total         6528                      
system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                      
system.cpu.iq.ISSUE:issued_per_cycle::mean     0.538297                      
system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.220228                      
system.cpu.iq.ISSUE:rate                     0.244588                       # Inst issue rate
system.cpu.iq.iqInstsAdded                       4031                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued                      3514                       # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded                   6                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined            1447                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued                15                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved              2                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined          766                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.fetch_accesses                     776                       # ITB accesses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_hits                         747                       # ITB hits
system.cpu.itb.fetch_misses                        29                       # ITB misses
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.l2cache.ReadExReq_accesses              24                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34604.166667                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        31500                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency       830500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses                24                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency       756000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses           24                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses               242                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34316.115702                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31130.165289                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_miss_latency       8304500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate                1                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses                 242                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency      7533500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate            1                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses            242                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses             14                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34178.571429                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency       478500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses               14                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency       434500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses           14                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs                         0                       # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses                266                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34342.105263                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31163.533835                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits                      0                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency        9135000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate                 1                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses                  266                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency      8289500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses             266                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses               266                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34342.105263                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.533835                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits                     0                       # number of overall hits
system.cpu.l2cache.overall_miss_latency       9135000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate                1                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses                 266                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency      8289500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses            266                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.sampled_refs                   228                       # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse               110.762790                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                       0                       # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks                       0                       # number of writebacks
system.cpu.memDep0.conflictingLoads                 7                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores                7                       # Number of conflicting stores.
system.cpu.memDep0.insertedLoads                  738                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores                 411                       # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles                            14367                       # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles               14                       # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps           1768                       # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents               1                       # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles              5170                       # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents              2                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups           5184                       # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts            4576                       # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands         3269                       # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles                856                       # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles             331                       # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles             11                       # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps              1501                       # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles          146                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts            8                       # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts                 65                       # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts            6                       # count of temporary serializing insts renamed
system.cpu.timesIdled                             154                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls               4                       # Number of system calls

---------- End Simulation Statistics   ----------