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|
---------- Begin Simulation Statistics ----------
host_inst_rate 48300 # Simulator instruction rate (inst/s)
host_mem_usage 226820 # Number of bytes of host memory used
host_seconds 0.20 # Real time elapsed on the host
host_tick_rate 67673766 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 9809 # Number of instructions simulated
sim_seconds 0.000014 # Number of seconds simulated
sim_ticks 13766000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 772 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 1892 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 458 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 1920 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 1920 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 1214 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 37 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 15124 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 0.648572 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.100130 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 9612 63.55% 63.55% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 3088 20.42% 83.97% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 1220 8.07% 92.04% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 836 5.53% 97.57% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 232 1.53% 99.10% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 57 0.38% 99.48% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 30 0.20% 99.68% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 12 0.08% 99.76% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 37 0.24% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 15124 # Number of insts commited each cycle
system.cpu.commit.COM:count 9809 # Number of instructions committed
system.cpu.commit.COM:loads 1056 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 1990 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 462 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 9809 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 3832 # The number of squashed insts skipped by commit
system.cpu.committedInsts 9809 # Number of Instructions Simulated
system.cpu.committedInsts_total 9809 # Number of Instructions Simulated
system.cpu.cpi 2.806912 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.806912 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 1244 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 37105.263158 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35048.387097 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 1168 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 2820000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.061093 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 76 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 2173000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.049839 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 62 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 33138.977636 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35775.641026 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 621 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 10372500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.335118 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 313 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 235 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 2790500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.083512 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 78 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 12.870504 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 2178 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 33913.881748 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 35453.571429 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1789 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 13192500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.178604 # miss rate for demand accesses
system.cpu.dcache.demand_misses 389 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 249 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 4963500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.064279 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 140 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.020744 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 84.965644 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 2178 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 33913.881748 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35453.571429 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1789 # number of overall hits
system.cpu.dcache.overall_miss_latency 13192500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.178604 # miss rate for overall accesses
system.cpu.dcache.overall_misses 389 # number of overall misses
system.cpu.dcache.overall_mshr_hits 249 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 4963500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.064279 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 140 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 139 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 84.965644 # Cycle average of tags in use
system.cpu.dcache.total_refs 1789 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 464 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 15304 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 6233 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 8371 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 721 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 56 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 1920 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 1255 # Number of cache lines fetched
system.cpu.fetch.Cycles 9031 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 117 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 8830 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 469 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.069735 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 1255 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 772 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 0.320706 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 15845 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.002083 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.178869 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 7129 44.99% 44.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4489 28.33% 73.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1878 11.85% 85.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 2046 12.91% 98.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 57 0.36% 98.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 227 1.43% 99.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 6 0.04% 99.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 8 0.05% 99.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 5 0.03% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 15845 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 1255 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 37417.543860 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35040.697674 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 970 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 10664000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.227092 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 285 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 9040500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.205578 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 258 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 3.759690 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 1255 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 37417.543860 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35040.697674 # average overall mshr miss latency
system.cpu.icache.demand_hits 970 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 10664000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.227092 # miss rate for demand accesses
system.cpu.icache.demand_misses 285 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 27 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 9040500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.205578 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 258 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.061525 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 126.002915 # Average occupied blocks per context
system.cpu.icache.overall_accesses 1255 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 37417.543860 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35040.697674 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 970 # number of overall hits
system.cpu.icache.overall_miss_latency 10664000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.227092 # miss rate for overall accesses
system.cpu.icache.overall_misses 285 # number of overall misses
system.cpu.icache.overall_mshr_hits 27 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 9040500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.205578 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 258 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 258 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 126.002915 # Cycle average of tags in use
system.cpu.icache.total_refs 970 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 11688 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 1318 # Number of branches executed
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.434678 # Inst execution rate
system.cpu.iew.EXEC:refs 2353 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 1060 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 10358 # num instructions consuming a value
system.cpu.iew.WB:count 11818 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.702935 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 7281 # num instructions producing a value
system.cpu.iew.WB:rate 0.429230 # insts written-back per cycle
system.cpu.iew.WB:sent 11866 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 487 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 58 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 1535 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 17 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 418 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 1238 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 13635 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 1293 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 536 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 11968 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 721 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 21 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 7 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 479 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 304 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 390 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.356263 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.356263 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 10018 80.12% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 1360 10.88% 91.02% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1123 8.98% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 12504 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 4 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.000320 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 3 75.00% 75.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 1 25.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 15845 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.789145 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.977935 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 8160 51.50% 51.50% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 4079 25.74% 77.24% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 2594 16.37% 93.61% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 834 5.26% 98.88% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 157 0.99% 99.87% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 19 0.12% 99.99% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 2 0.01% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 6 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 15845 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 0.454146 # Inst issue rate
system.cpu.iq.iqInstsAdded 13618 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 12504 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 17 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 3342 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 5066 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 78 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34493.589744 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31326.923077 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 2690500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 78 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2443500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 78 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 320 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34188.679245 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.716981 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 10872000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.993750 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 318 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 9859500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.993750 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 318 # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.006309 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 398 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34248.737374 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31068.181818 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 13562500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.994975 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 396 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 12303000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.994975 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 396 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.004816 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 157.820330 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 398 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34248.737374 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31068.181818 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 2 # number of overall hits
system.cpu.l2cache.overall_miss_latency 13562500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.994975 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 396 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 12303000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.994975 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 396 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 317 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 157.820330 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 1535 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1238 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 27533 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 105 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 9368 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 6603 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 15 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 38664 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 14745 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 13787 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 8027 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 721 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 108 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 4419 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 281 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 20 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 169 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 17 # count of temporary serializing insts renamed
system.cpu.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
---------- End Simulation Statistics ----------
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