blob: 805380c676aea25c4e962d9f53a6d364c1267b1d (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
|
---------- Begin Simulation Statistics ----------
host_inst_rate 74664 # Simulator instruction rate (inst/s)
host_mem_usage 228156 # Number of bytes of host memory used
host_seconds 0.13 # Real time elapsed on the host
host_tick_rate 103594447 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 9809 # Number of instructions simulated
sim_seconds 0.000014 # Number of seconds simulated
sim_ticks 13637500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 715 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 1829 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 455 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 1876 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 1876 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 1214 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 22 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 15018 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 0.653150 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.090994 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 9552 63.60% 63.60% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 2996 19.95% 83.55% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 1196 7.96% 91.52% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 909 6.05% 97.57% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 244 1.62% 99.19% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 60 0.40% 99.59% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 31 0.21% 99.80% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 8 0.05% 99.85% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 22 0.15% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 15018 # Number of insts commited each cycle
system.cpu.commit.COM:count 9809 # Number of instructions committed
system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:int_insts 9714 # Number of committed integer instructions.
system.cpu.commit.COM:loads 1056 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 1990 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 455 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 9809 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 3810 # The number of squashed insts skipped by commit
system.cpu.committedInsts 9809 # Number of Instructions Simulated
system.cpu.committedInsts_total 9809 # Number of Instructions Simulated
system.cpu.cpi 2.780712 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.780712 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 1299 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 34989.361702 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34992.307692 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 1205 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 3289000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.072363 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 94 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 29 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 2274500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.050038 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 65 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 33138.977636 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35814.102564 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 621 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 10372500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.335118 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 313 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 235 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 2793500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.083512 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 78 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 12.859155 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 2233 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 33566.339066 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 35440.559441 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1826 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 13661500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.182266 # miss rate for demand accesses
system.cpu.dcache.demand_misses 407 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 264 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 5068000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.064039 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 143 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.021266 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 87.104239 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 2233 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 33566.339066 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35440.559441 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1826 # number of overall hits
system.cpu.dcache.overall_miss_latency 13661500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.182266 # miss rate for overall accesses
system.cpu.dcache.overall_misses 407 # number of overall misses
system.cpu.dcache.overall_mshr_hits 264 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 5068000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.064039 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 143 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 87.104239 # Cycle average of tags in use
system.cpu.dcache.total_refs 1826 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 420 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 15296 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 6181 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 8360 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 701 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 57 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 1876 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 1264 # Number of cache lines fetched
system.cpu.fetch.Cycles 9026 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 121 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 8825 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 464 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.068778 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 1264 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 715 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 0.323545 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 15719 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.009352 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.179835 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 7007 44.58% 44.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4504 28.65% 73.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1838 11.69% 84.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 2072 13.18% 98.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 57 0.36% 98.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 222 1.41% 99.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 6 0.04% 99.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 8 0.05% 99.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 5 0.03% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 15719 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 2 # number of floating regfile reads
system.cpu.icache.ReadReq_accesses 1264 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 37405.594406 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35046.332046 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 978 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 10698000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.226266 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 286 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 9077000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.204905 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 259 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 3.776062 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 1264 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 37405.594406 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35046.332046 # average overall mshr miss latency
system.cpu.icache.demand_hits 978 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 10698000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.226266 # miss rate for demand accesses
system.cpu.icache.demand_misses 286 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 27 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 9077000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.204905 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 259 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.062320 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 127.631724 # Average occupied blocks per context
system.cpu.icache.overall_accesses 1264 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 37405.594406 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35046.332046 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 978 # number of overall hits
system.cpu.icache.overall_miss_latency 10698000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.226266 # miss rate for overall accesses
system.cpu.icache.overall_misses 286 # number of overall misses
system.cpu.icache.overall_mshr_hits 27 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 9077000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.204905 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 259 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 259 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 127.631724 # Cycle average of tags in use
system.cpu.icache.total_refs 978 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 11557 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 1339 # Number of branches executed
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.445373 # Inst execution rate
system.cpu.iew.EXEC:refs 2437 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 1088 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 9392 # num instructions consuming a value
system.cpu.iew.WB:count 11991 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.786095 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 7383 # num instructions producing a value
system.cpu.iew.WB:rate 0.439617 # insts written-back per cycle
system.cpu.iew.WB:sent 12024 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 474 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 40 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 1510 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 16 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 424 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 1230 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 13620 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 1349 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 556 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 12148 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 701 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 23 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 10 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 454 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 296 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 385 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 89 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 21267 # number of integer regfile reads
system.cpu.int_regfile_writes 11326 # number of integer regfile writes
system.cpu.ipc 0.359620 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.359620 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 10141 79.83% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 79.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 1414 11.13% 90.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1146 9.02% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 12704 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 4 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.000315 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 4 100.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 15719 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.808194 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.980491 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 7896 50.23% 50.23% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 4146 26.38% 76.61% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 2688 17.10% 93.71% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 806 5.13% 98.84% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 156 0.99% 99.83% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 22 0.14% 99.97% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 5 0.03% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 6 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 15719 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 0.465757 # Inst issue rate
system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 12701 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 41124 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 11989 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 16903 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 13604 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 12704 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 16 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 3282 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 4201 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 78 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34512.820513 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31358.974359 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 2692000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 78 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2446000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 78 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 324 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34181.677019 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 30998.447205 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 11006500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.993827 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 322 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 9981500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.993827 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 322 # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.006231 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 402 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34246.250000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31068.750000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 13698500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.995025 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 400 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 12427500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.995025 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 400 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.004917 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 161.123348 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 402 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34246.250000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31068.750000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 2 # number of overall hits
system.cpu.l2cache.overall_miss_latency 13698500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.995025 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 400 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 12427500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.995025 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 400 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 321 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 161.123348 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 1510 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1230 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 5444 # number of misc regfile reads
system.cpu.numCycles 27276 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 87 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 9368 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 6548 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 15 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 33593 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 14729 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 13866 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 8021 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 701 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 105 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 4498 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 16 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 33577 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 257 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 19 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 159 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 16 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 28615 # The number of ROB reads
system.cpu.rob.rob_writes 27943 # The number of ROB writes
system.cpu.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
---------- End Simulation Statistics ----------
|