blob: 6cf4d180e6cbf8e155132c596451f4535c9b4bc3 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
|
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 706 # Number of BTB hits
global.BPredUnit.BTBLookups 3499 # Number of BTB lookups
global.BPredUnit.RASInCorrect 117 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 1092 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 2350 # Number of conditional branches predicted
global.BPredUnit.lookups 4075 # Number of BP lookups
global.BPredUnit.usedRAS 561 # Number of times the RAS was used to get a target.
host_inst_rate 92493 # Simulator instruction rate (inst/s)
host_mem_usage 197924 # Number of bytes of host memory used
host_seconds 0.12 # Real time elapsed on the host
host_tick_rate 47019704 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 14 # Number of conflicting loads.
memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 35 # Number of conflicting stores.
memdepunit.memDep.conflictingStores 38 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 1959 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedLoads 1940 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 1118 # Number of stores inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 1140 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 11247 # Number of instructions simulated
sim_seconds 0.000006 # Number of seconds simulated
sim_ticks 5727000 # Number of ticks simulated
system.cpu.commit.COM:branches 1724 # Number of branches committed
system.cpu.commit.COM:branches_0 862 # Number of branches committed
system.cpu.commit.COM:branches_1 862 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 161 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 11403
system.cpu.commit.COM:committed_per_cycle.min_value 0
0 6781 5946.68%
1 2144 1880.21%
2 950 833.11%
3 495 434.10%
4 331 290.27%
5 216 189.42%
6 215 188.55%
7 110 96.47%
8 161 141.19%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
system.cpu.commit.COM:count 11281 # Number of instructions committed
system.cpu.commit.COM:count_0 5640 # Number of instructions committed
system.cpu.commit.COM:count_1 5641 # Number of instructions committed
system.cpu.commit.COM:loads 1958 # Number of loads committed
system.cpu.commit.COM:loads_0 979 # Number of loads committed
system.cpu.commit.COM:loads_1 979 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:membars_0 0 # Number of memory barriers committed
system.cpu.commit.COM:membars_1 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 3582 # Number of memory references committed
system.cpu.commit.COM:refs_0 1791 # Number of memory references committed
system.cpu.commit.COM:refs_1 1791 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed
system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 854 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 11281 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 8053 # The number of squashed insts skipped by commit
system.cpu.committedInsts_0 5623 # Number of Instructions Simulated
system.cpu.committedInsts_1 5624 # Number of Instructions Simulated
system.cpu.committedInsts_total 11247 # Number of Instructions Simulated
system.cpu.cpi_0 2.037169 # CPI: Cycles Per Instruction
system.cpu.cpi_1 2.036807 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.018494 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 2934 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses_0 2934 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency_0 12119.897959 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 7403.061224 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 2738 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits_0 2738 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 2375500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency_0 2375500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate_0 0.066803 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 196 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses_0 196 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 81 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits_0 81 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1451000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency_0 1451000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.066803 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 196 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses_0 196 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 1240 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses_0 1240 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency_0 21692.528736 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 6310.344828 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 1066 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits_0 1066 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 3774500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency_0 3774500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate_0 0.140323 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 174 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses_0 174 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 384 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits_0 384 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 1098000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency_0 1098000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.140323 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 174 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses_0 174 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 11.276471 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 4174 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses_0 4174 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency <err: div-0> # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency_0 16621.621622 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency_0 6889.189189 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
system.cpu.dcache.demand_hits 3804 # number of demand (read+write) hits
system.cpu.dcache.demand_hits_0 3804 # number of demand (read+write) hits
system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 6150000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency_0 6150000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate <err: div-0> # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate_0 0.088644 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
system.cpu.dcache.demand_misses 370 # number of demand (read+write) misses
system.cpu.dcache.demand_misses_0 370 # number of demand (read+write) misses
system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 465 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits_0 465 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 2549000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency_0 2549000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate_0 0.088644 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 370 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses_0 370 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated
system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 4174 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses_0 4174 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency <err: div-0> # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency_0 16621.621622 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency_0 6889.189189 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 3804 # number of overall hits
system.cpu.dcache.overall_hits_0 3804 # number of overall hits
system.cpu.dcache.overall_hits_1 0 # number of overall hits
system.cpu.dcache.overall_miss_latency 6150000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency_0 6150000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate <err: div-0> # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate_0 0.088644 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
system.cpu.dcache.overall_misses 370 # number of overall misses
system.cpu.dcache.overall_misses_0 370 # number of overall misses
system.cpu.dcache.overall_misses_1 0 # number of overall misses
system.cpu.dcache.overall_mshr_hits 465 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits_0 465 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 2549000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency_0 2549000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate_0 0.088644 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 370 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses_0 370 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.replacements_0 0 # number of replacements
system.cpu.dcache.replacements_1 0 # number of replacements
system.cpu.dcache.sampled_refs 340 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 215.589336 # Cycle average of tags in use
system.cpu.dcache.total_refs 3834 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.dcache.writebacks_0 0 # number of writebacks
system.cpu.dcache.writebacks_1 0 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 1981 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 247 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 354 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 22591 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 15034 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 3799 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 1569 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 329 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 215 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 5095 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 4970 # DTB hits
system.cpu.dtb.misses 125 # DTB misses
system.cpu.dtb.read_accesses 3183 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 3106 # DTB read hits
system.cpu.dtb.read_misses 77 # DTB read misses
system.cpu.dtb.write_accesses 1912 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 1864 # DTB write hits
system.cpu.dtb.write_misses 48 # DTB write misses
system.cpu.fetch.Branches 4075 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 3019 # Number of cache lines fetched
system.cpu.fetch.Cycles 7174 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 439 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 24770 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 1207 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.355740 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 3019 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 1267 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.162375 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 11446
system.cpu.fetch.rateDist.min_value 0
0 7343 6415.34%
1 306 267.34%
2 243 212.30%
3 264 230.65%
4 343 299.67%
5 290 253.36%
6 316 276.08%
7 260 227.15%
8 2081 1818.10%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 2953 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses_0 2953 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency_0 8345.528455 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 5903.252033 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 2338 # number of ReadReq hits
system.cpu.icache.ReadReq_hits_0 2338 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 5132500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency_0 5132500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate_0 0.208263 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 615 # number of ReadReq misses
system.cpu.icache.ReadReq_misses_0 615 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 66 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits_0 66 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 3630500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency_0 3630500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate_0 0.208263 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 615 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses_0 615 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 3.801626 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 2953 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses_0 2953 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency <err: div-0> # average overall miss latency
system.cpu.icache.demand_avg_miss_latency_0 8345.528455 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency_0 5903.252033 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
system.cpu.icache.demand_hits 2338 # number of demand (read+write) hits
system.cpu.icache.demand_hits_0 2338 # number of demand (read+write) hits
system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 5132500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency_0 5132500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate <err: div-0> # miss rate for demand accesses
system.cpu.icache.demand_miss_rate_0 0.208263 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
system.cpu.icache.demand_misses 615 # number of demand (read+write) misses
system.cpu.icache.demand_misses_0 615 # number of demand (read+write) misses
system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 66 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits_0 66 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 3630500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency_0 3630500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate_0 0.208263 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 615 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses_0 615 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated
system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 2953 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses_0 2953 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency <err: div-0> # average overall miss latency
system.cpu.icache.overall_avg_miss_latency_0 8345.528455 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency_0 5903.252033 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 2338 # number of overall hits
system.cpu.icache.overall_hits_0 2338 # number of overall hits
system.cpu.icache.overall_hits_1 0 # number of overall hits
system.cpu.icache.overall_miss_latency 5132500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency_0 5132500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles
system.cpu.icache.overall_miss_rate <err: div-0> # miss rate for overall accesses
system.cpu.icache.overall_miss_rate_0 0.208263 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
system.cpu.icache.overall_misses 615 # number of overall misses
system.cpu.icache.overall_misses_0 615 # number of overall misses
system.cpu.icache.overall_misses_1 0 # number of overall misses
system.cpu.icache.overall_mshr_hits 66 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits_0 66 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 3630500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency_0 3630500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate_0 0.208263 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 615 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses_0 615 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 7 # number of replacements
system.cpu.icache.replacements_0 7 # number of replacements
system.cpu.icache.replacements_1 0 # number of replacements
system.cpu.icache.sampled_refs 615 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 319.122278 # Cycle average of tags in use
system.cpu.icache.total_refs 2338 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.writebacks_0 0 # number of writebacks
system.cpu.icache.writebacks_1 0 # number of writebacks
system.cpu.idleCycles 9 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 2386 # Number of branches executed
system.cpu.iew.EXEC:branches_0 1188 # Number of branches executed
system.cpu.iew.EXEC:branches_1 1198 # Number of branches executed
system.cpu.iew.EXEC:nop 127 # number of nop insts executed
system.cpu.iew.EXEC:nop_0 66 # number of nop insts executed
system.cpu.iew.EXEC:nop_1 61 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.377041 # Inst execution rate
system.cpu.iew.EXEC:refs 5110 # number of memory reference insts executed
system.cpu.iew.EXEC:refs_0 2531 # number of memory reference insts executed
system.cpu.iew.EXEC:refs_1 2579 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 1925 # Number of stores executed
system.cpu.iew.EXEC:stores_0 958 # Number of stores executed
system.cpu.iew.EXEC:stores_1 967 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed
system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed
system.cpu.iew.WB:consumers 10281 # num instructions consuming a value
system.cpu.iew.WB:consumers_0 5147 # num instructions consuming a value
system.cpu.iew.WB:consumers_1 5134 # num instructions consuming a value
system.cpu.iew.WB:count 15145 # cumulative count of insts written-back
system.cpu.iew.WB:count_0 7584 # cumulative count of insts written-back
system.cpu.iew.WB:count_1 7561 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 1.539346 # average fanout of values written-back
system.cpu.iew.WB:fanout_0 0.768992 # average fanout of values written-back
system.cpu.iew.WB:fanout_1 0.770354 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 7913 # num instructions producing a value
system.cpu.iew.WB:producers_0 3958 # num instructions producing a value
system.cpu.iew.WB:producers_1 3955 # num instructions producing a value
system.cpu.iew.WB:rate 1.322130 # insts written-back per cycle
system.cpu.iew.WB:rate_0 0.662069 # insts written-back per cycle
system.cpu.iew.WB:rate_1 0.660061 # insts written-back per cycle
system.cpu.iew.WB:sent 15343 # cumulative count of insts sent to commit
system.cpu.iew.WB:sent_0 7675 # cumulative count of insts sent to commit
system.cpu.iew.WB:sent_1 7668 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 991 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 60 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 3899 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 46 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 435 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 2258 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 19501 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 3185 # Number of load instructions executed
system.cpu.iew.iewExecLoadInsts_0 1573 # Number of load instructions executed
system.cpu.iew.iewExecLoadInsts_1 1612 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 923 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 15774 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 16 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 1569 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 39 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 62 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 980 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 306 # Number of stores squashed
system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.1.forwLoads 50 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.1.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.1.memOrderViolation 63 # Number of memory ordering violations
system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.1.squashedLoads 961 # Number of loads squashed
system.cpu.iew.lsq.thread.1.squashedStores 328 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 125 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 788 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 203 # Number of branches that were predicted taken incorrectly
system.cpu.ipc_0 0.490877 # IPC: Instructions Per Cycle
system.cpu.ipc_1 0.490965 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.981842 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 8365 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 2 0.02% # Type of FU issued
IntAlu 5650 67.54% # Type of FU issued
IntMult 1 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 2 0.02% # Type of FU issued
FloatCmp 0 0.00% # Type of FU issued
FloatCvt 0 0.00% # Type of FU issued
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
MemRead 1721 20.57% # Type of FU issued
MemWrite 989 11.82% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:FU_type_1 8332 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_1.start_dist
No_OpClass 2 0.02% # Type of FU issued
IntAlu 5594 67.14% # Type of FU issued
IntMult 1 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 2 0.02% # Type of FU issued
FloatCmp 0 0.00% # Type of FU issued
FloatCvt 0 0.00% # Type of FU issued
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
MemRead 1734 20.81% # Type of FU issued
MemWrite 999 11.99% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_1.end_dist
system.cpu.iq.ISSUE:FU_type 16697 # Type of FU issued
system.cpu.iq.ISSUE:FU_type.start_dist
No_OpClass 4 0.02% # Type of FU issued
IntAlu 11244 67.34% # Type of FU issued
IntMult 2 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 4 0.02% # Type of FU issued
FloatCmp 0 0.00% # Type of FU issued
FloatCvt 0 0.00% # Type of FU issued
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
MemRead 3455 20.69% # Type of FU issued
MemWrite 1988 11.91% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 193 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_cnt_0 88 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_cnt_1 105 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.011559 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_busy_rate_0 0.005270 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_busy_rate_1 0.006289 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available
IntAlu 13 6.74% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
FloatCmp 0 0.00% # attempts to use FU when none available
FloatCvt 0 0.00% # attempts to use FU when none available
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 111 57.51% # attempts to use FU when none available
MemWrite 69 35.75% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 11446
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 5082 4439.98%
1 1881 1643.37%
2 1650 1441.55%
3 1151 1005.59%
4 829 724.27%
5 503 439.45%
6 239 208.81%
7 90 78.63%
8 21 18.35%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 1.457617 # Inst issue rate
system.cpu.iq.iqInstsAdded 19328 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 16697 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 7298 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 4495 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 3071 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 3019 # ITB hits
system.cpu.itb.misses 52 # ITB misses
system.cpu.l2cache.ReadExReq_accesses 144 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses_0 144 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency_0 4743.055556 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 2743.055556 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 683000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency_0 683000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate_0 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 144 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses_0 144 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 395000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 395000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate_0 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 144 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses_0 144 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 811 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses_0 811 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency_0 4691.831683 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 2691.831683 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits_0 3 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 3791000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency_0 3791000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate_0 0.996301 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 808 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses_0 808 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 2175000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2175000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.996301 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 808 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses_0 808 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 30 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses_0 30 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 4500 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 2500 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 135000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency_0 135000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate_0 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 30 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses_0 30 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 75000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 75000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate_0 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 30 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses_0 30 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.003856 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 955 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses_0 955 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency <err: div-0> # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency_0 4699.579832 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency_0 2699.579832 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits_0 3 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 4474000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency_0 4474000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate <err: div-0> # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate_0 0.996859 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
system.cpu.l2cache.demand_misses 952 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses_0 952 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 2570000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency_0 2570000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate_0 0.996859 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 952 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses_0 952 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated
system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 955 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses_0 955 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency <err: div-0> # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency_0 4699.579832 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency_0 2699.579832 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 3 # number of overall hits
system.cpu.l2cache.overall_hits_0 3 # number of overall hits
system.cpu.l2cache.overall_hits_1 0 # number of overall hits
system.cpu.l2cache.overall_miss_latency 4474000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency_0 4474000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate <err: div-0> # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate_0 0.996859 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
system.cpu.l2cache.overall_misses 952 # number of overall misses
system.cpu.l2cache.overall_misses_0 952 # number of overall misses
system.cpu.l2cache.overall_misses_1 0 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 2570000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency_0 2570000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate_0 0.996859 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 952 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses_0 952 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.replacements_0 0 # number of replacements
system.cpu.l2cache.replacements_1 0 # number of replacements
system.cpu.l2cache.sampled_refs 778 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 424.676856 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.writebacks_0 0 # number of writebacks
system.cpu.l2cache.writebacks_1 0 # number of writebacks
system.cpu.numCycles 11455 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 641 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 8102 # Number of HB maps that are committed
system.cpu.rename.RENAME:IdleCycles 15417 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 776 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 27043 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 21312 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 15958 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 3623 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 1569 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 844 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 7856 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 504 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 2318 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 36 # count of temporary serializing insts renamed
system.cpu.timesIdled 4 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls
system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------
|