path: root/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt

---------- Begin Simulation Statistics ----------
host_inst_rate                                2244323                       # Simulator instruction rate (inst/s)
host_mem_usage                                 293120                       # Number of bytes of host memory used
host_seconds                                    28.14                       # Real time elapsed on the host
host_tick_rate                            66466128576                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                    63154034                       # Number of instructions simulated
sim_seconds                                  1.870336                       # Number of seconds simulated
sim_ticks                                1870335522500                       # Number of ticks simulated
system.cpu0.dcache.LoadLockedReq_accesses::0       188297                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       188297                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_hits::0       172138                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       172138                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.085817                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_misses::0        16159                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        16159                       # number of LoadLockedReq misses
system.cpu0.dcache.ReadReq_accesses::0        8981669                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      8981669                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_hits::0            7298106                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        7298106                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_miss_rate::0      0.187444                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_misses::0          1683563                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1683563                       # number of ReadReq misses
system.cpu0.dcache.StoreCondReq_accesses::0       187338                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       187338                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_hits::0        165851                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       165851                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_miss_rate::0     0.114696                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_misses::0        21487                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        21487                       # number of StoreCondReq misses
system.cpu0.dcache.WriteReq_accesses::0       5748261                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      5748261                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_hits::0           5400040                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       5400040                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_miss_rate::0     0.060578                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_misses::0          348221                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       348221                       # number of WriteReq misses
system.cpu0.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_refs                  6.629793                       # Average number of references to valid blocks.
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.demand_accesses::0        14729930                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     14729930                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_avg_miss_latency::0            0                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.cpu0.dcache.demand_hits::0            12698146                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        12698146                       # number of demand (read+write) hits
system.cpu0.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_rate::0       0.137936                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu0.dcache.demand_misses::0           2031784                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       2031784                       # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.occ_%::0                  0.985990                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_blocks::0           504.827058                       # Average occupied blocks per context
system.cpu0.dcache.overall_accesses::0       14729930                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     14729930                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_avg_miss_latency::0            0                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_hits::0           12698146                       # number of overall hits
system.cpu0.dcache.overall_hits::1                  0                       # number of overall hits
system.cpu0.dcache.overall_hits::total       12698146                       # number of overall hits
system.cpu0.dcache.overall_miss_latency             0                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_rate::0      0.137936                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu0.dcache.overall_misses::0          2031784                       # number of overall misses
system.cpu0.dcache.overall_misses::1                0                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2031784                       # number of overall misses
system.cpu0.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.replacements               1978962                       # number of replacements
system.cpu0.dcache.sampled_refs               1979474                       # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.dcache.tagsinuse               504.827058                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                13123502                       # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              10840000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.writebacks                  419022                       # number of writebacks
system.cpu0.dtb.data_accesses                  698037                       # DTB accesses
system.cpu0.dtb.data_acv                          251                       # DTB access violations
system.cpu0.dtb.data_hits                    15091429                       # DTB hits
system.cpu0.dtb.data_misses                      7805                       # DTB misses
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.read_accesses                  508987                       # DTB read accesses
system.cpu0.dtb.read_acv                          152                       # DTB read access violations
system.cpu0.dtb.read_hits                     9154530                       # DTB read hits
system.cpu0.dtb.read_misses                      7079                       # DTB read misses
system.cpu0.dtb.write_accesses                 189050                       # DTB write accesses
system.cpu0.dtb.write_acv                          99                       # DTB write access violations
system.cpu0.dtb.write_hits                    5936899                       # DTB write hits
system.cpu0.dtb.write_misses                      726                       # DTB write misses
system.cpu0.icache.ReadReq_accesses::0       57230132                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     57230132                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_hits::0           56345132                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       56345132                       # number of ReadReq hits
system.cpu0.icache.ReadReq_miss_rate::0      0.015464                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_misses::0           885000                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       885000                       # number of ReadReq misses
system.cpu0.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu0.icache.avg_refs                 63.672859                       # Average number of references to valid blocks.
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.demand_accesses::0        57230132                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     57230132                       # number of demand (read+write) accesses
system.cpu0.icache.demand_avg_miss_latency::0            0                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.cpu0.icache.demand_hits::0            56345132                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        56345132                       # number of demand (read+write) hits
system.cpu0.icache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_rate::0       0.015464                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu0.icache.demand_misses::0            885000                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        885000                       # number of demand (read+write) misses
system.cpu0.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.occ_%::0                  0.998525                       # Average percentage of cache occupancy
system.cpu0.icache.occ_blocks::0           511.244754                       # Average occupied blocks per context
system.cpu0.icache.overall_accesses::0       57230132                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     57230132                       # number of overall (read+write) accesses
system.cpu0.icache.overall_avg_miss_latency::0            0                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_hits::0           56345132                       # number of overall hits
system.cpu0.icache.overall_hits::1                  0                       # number of overall hits
system.cpu0.icache.overall_hits::total       56345132                       # number of overall hits
system.cpu0.icache.overall_miss_latency             0                       # number of overall miss cycles
system.cpu0.icache.overall_miss_rate::0      0.015464                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu0.icache.overall_misses::0           885000                       # number of overall misses
system.cpu0.icache.overall_misses::1                0                       # number of overall misses
system.cpu0.icache.overall_misses::total       885000                       # number of overall misses
system.cpu0.icache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_misses              0                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.icache.replacements                884404                       # number of replacements
system.cpu0.icache.sampled_refs                884916                       # Sample count of references to valid blocks.
system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.icache.tagsinuse               511.244754                       # Cycle average of tags in use
system.cpu0.icache.total_refs                56345132                       # Total number of references to valid blocks.
system.cpu0.icache.warmup_cycle            9786576500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.writebacks                       0                       # number of writebacks
system.cpu0.idle_fraction                    0.984700                       # Percentage of idle cycles
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.fetch_accesses                3859041                       # ITB accesses
system.cpu0.itb.fetch_acv                         127                       # ITB acv
system.cpu0.itb.fetch_hits                    3855556                       # ITB hits
system.cpu0.itb.fetch_misses                     3485                       # ITB misses
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                  110      0.06%      0.06% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.06% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.06% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.06% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3762      2.05%      2.11% # number of callpals executed
system.cpu0.kern.callpal::tbi                      38      0.02%      2.14% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.14% # number of callpals executed
system.cpu0.kern.callpal::swpipl               168035     91.68%     93.82% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6150      3.36%     97.17% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.17% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     3      0.00%     97.17% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     7      0.00%     97.18% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     97.18% # number of callpals executed
system.cpu0.kern.callpal::rti                    4673      2.55%     99.73% # number of callpals executed
system.cpu0.kern.callpal::callsys                 357      0.19%     99.92% # number of callpals executed
system.cpu0.kern.callpal::imb                     142      0.08%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                183291                       # number of callpals executed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.hwrei                    197120                       # number of hwrei instructions executed
system.cpu0.kern.inst.quiesce                    6283                       # number of quiesce instructions executed
system.cpu0.kern.ipl_count::0                   71004     40.60%     40.60% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    243      0.14%     40.74% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1908      1.09%     41.83% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                      8      0.00%     41.84% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                 101705     58.16%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              174868                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    69637     49.24%     49.24% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     243      0.17%     49.41% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1908      1.35%     50.76% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                       8      0.01%     50.77% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   69629     49.23%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               141425                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1852989766500     99.07%     99.07% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               20110000      0.00%     99.07% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22               82044000      0.00%     99.08% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30                 949500      0.00%     99.08% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            17242445000      0.92%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1870335315000                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.980748                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.684617                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.mode_good::kernel               1157                      
system.cpu0.kern.mode_good::user                 1158                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch::kernel             7091                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1158                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_switch_good::kernel     0.163165                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle      no_value                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     no_value                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1869378305000     99.95%     99.95% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user           957009000      0.05%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3763                       # number of times the context was actually changed
system.cpu0.kern.syscall::2                         6      2.65%      2.65% # number of syscalls executed
system.cpu0.kern.syscall::3                        19      8.41%     11.06% # number of syscalls executed
system.cpu0.kern.syscall::4                         2      0.88%     11.95% # number of syscalls executed
system.cpu0.kern.syscall::6                        32     14.16%     26.11% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.44%     26.55% # number of syscalls executed
system.cpu0.kern.syscall::15                        1      0.44%     26.99% # number of syscalls executed
system.cpu0.kern.syscall::17                        9      3.98%     30.97% # number of syscalls executed
system.cpu0.kern.syscall::19                        8      3.54%     34.51% # number of syscalls executed
system.cpu0.kern.syscall::20                        6      2.65%     37.17% # number of syscalls executed
system.cpu0.kern.syscall::23                        2      0.88%     38.05% # number of syscalls executed
system.cpu0.kern.syscall::24                        4      1.77%     39.82% # number of syscalls executed
system.cpu0.kern.syscall::33                        7      3.10%     42.92% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.88%     43.81% # number of syscalls executed
system.cpu0.kern.syscall::45                       37     16.37%     60.18% # number of syscalls executed
system.cpu0.kern.syscall::47                        4      1.77%     61.95% # number of syscalls executed
system.cpu0.kern.syscall::48                        8      3.54%     65.49% # number of syscalls executed
system.cpu0.kern.syscall::54                       10      4.42%     69.91% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.44%     70.35% # number of syscalls executed
system.cpu0.kern.syscall::59                        4      1.77%     72.12% # number of syscalls executed
system.cpu0.kern.syscall::71                       30     13.27%     85.40% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.33%     86.73% # number of syscalls executed
system.cpu0.kern.syscall::74                        8      3.54%     90.27% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.44%     90.71% # number of syscalls executed
system.cpu0.kern.syscall::90                        2      0.88%     91.59% # number of syscalls executed
system.cpu0.kern.syscall::92                        9      3.98%     95.58% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.88%     96.46% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.88%     97.35% # number of syscalls executed
system.cpu0.kern.syscall::132                       2      0.88%     98.23% # number of syscalls executed
system.cpu0.kern.syscall::144                       2      0.88%     99.12% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.88%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   226                       # number of syscalls executed
system.cpu0.not_idle_fraction                0.015300                       # Percentage of non-idle cycles
system.cpu0.numCycles                      3740670933                       # number of cpu cycles simulated
system.cpu0.num_insts                        57222076                       # Number of instructions executed
system.cpu0.num_refs                         15330887                       # Number of memory references
system.cpu1.dcache.LoadLockedReq_accesses::0        16418                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        16418                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_hits::0        15129                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        15129                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.078511                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_misses::0         1289                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         1289                       # number of LoadLockedReq misses
system.cpu1.dcache.ReadReq_accesses::0        1150965                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      1150965                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_hits::0            1109315                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        1109315                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_miss_rate::0      0.036187                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_misses::0            41650                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total        41650                       # number of ReadReq misses
system.cpu1.dcache.StoreCondReq_accesses::0        16345                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        16345                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_hits::0         13853                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        13853                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_miss_rate::0     0.152463                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_misses::0         2492                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total         2492                       # number of StoreCondReq misses
system.cpu1.dcache.WriteReq_accesses::0        733305                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total       733305                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_hits::0            703732                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total        703732                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_miss_rate::0     0.040328                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_misses::0           29573                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total        29573                       # number of WriteReq misses
system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_refs                 29.279155                       # Average number of references to valid blocks.
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.demand_accesses::0         1884270                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      1884270                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_avg_miss_latency::0            0                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.cpu1.dcache.demand_hits::0             1813047                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         1813047                       # number of demand (read+write) hits
system.cpu1.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_rate::0       0.037799                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu1.dcache.demand_misses::0             71223                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total         71223                       # number of demand (read+write) misses
system.cpu1.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.occ_%::0                  0.765530                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_blocks::0           391.951263                       # Average occupied blocks per context
system.cpu1.dcache.overall_accesses::0        1884270                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      1884270                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_avg_miss_latency::0            0                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_hits::0            1813047                       # number of overall hits
system.cpu1.dcache.overall_hits::1                  0                       # number of overall hits
system.cpu1.dcache.overall_hits::total        1813047                       # number of overall hits
system.cpu1.dcache.overall_miss_latency             0                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_rate::0      0.037799                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu1.dcache.overall_misses::0            71223                       # number of overall misses
system.cpu1.dcache.overall_misses::1                0                       # number of overall misses
system.cpu1.dcache.overall_misses::total        71223                       # number of overall misses
system.cpu1.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.replacements                 62338                       # number of replacements
system.cpu1.dcache.sampled_refs                 62657                       # Sample count of references to valid blocks.
system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.dcache.tagsinuse               391.951263                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                 1834544                       # Total number of references to valid blocks.
system.cpu1.dcache.warmup_cycle          1851267520500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.writebacks                   31228                       # number of writebacks
system.cpu1.dtb.data_accesses                  323622                       # DTB accesses
system.cpu1.dtb.data_acv                          116                       # DTB access violations
system.cpu1.dtb.data_hits                     1914885                       # DTB hits
system.cpu1.dtb.data_misses                      3692                       # DTB misses
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.read_accesses                  220342                       # DTB read accesses
system.cpu1.dtb.read_acv                           58                       # DTB read access violations
system.cpu1.dtb.read_hits                     1163439                       # DTB read hits
system.cpu1.dtb.read_misses                      3277                       # DTB read misses
system.cpu1.dtb.write_accesses                 103280                       # DTB write accesses
system.cpu1.dtb.write_acv                          58                       # DTB write access violations
system.cpu1.dtb.write_hits                     751446                       # DTB write hits
system.cpu1.dtb.write_misses                      415                       # DTB write misses
system.cpu1.icache.ReadReq_accesses::0        5935766                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      5935766                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_hits::0            5832136                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        5832136                       # number of ReadReq hits
system.cpu1.icache.ReadReq_miss_rate::0      0.017459                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_misses::0           103630                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       103630                       # number of ReadReq misses
system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.icache.avg_refs                 56.293119                       # Average number of references to valid blocks.
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.demand_accesses::0         5935766                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      5935766                       # number of demand (read+write) accesses
system.cpu1.icache.demand_avg_miss_latency::0            0                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.cpu1.icache.demand_hits::0             5832136                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         5832136                       # number of demand (read+write) hits
system.cpu1.icache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_rate::0       0.017459                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu1.icache.demand_misses::0            103630                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        103630                       # number of demand (read+write) misses
system.cpu1.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.occ_%::0                  0.834231                       # Average percentage of cache occupancy
system.cpu1.icache.occ_blocks::0           427.126317                       # Average occupied blocks per context
system.cpu1.icache.overall_accesses::0        5935766                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      5935766                       # number of overall (read+write) accesses
system.cpu1.icache.overall_avg_miss_latency::0            0                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_hits::0            5832136                       # number of overall hits
system.cpu1.icache.overall_hits::1                  0                       # number of overall hits
system.cpu1.icache.overall_hits::total        5832136                       # number of overall hits
system.cpu1.icache.overall_miss_latency             0                       # number of overall miss cycles
system.cpu1.icache.overall_miss_rate::0      0.017459                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu1.icache.overall_misses::0           103630                       # number of overall misses
system.cpu1.icache.overall_misses::1                0                       # number of overall misses
system.cpu1.icache.overall_misses::total       103630                       # number of overall misses
system.cpu1.icache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_misses              0                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.icache.replacements                103091                       # number of replacements
system.cpu1.icache.sampled_refs                103603                       # Sample count of references to valid blocks.
system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.icache.tagsinuse               427.126317                       # Cycle average of tags in use
system.cpu1.icache.total_refs                 5832136                       # Total number of references to valid blocks.
system.cpu1.icache.warmup_cycle          1868933059000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.writebacks                       0                       # number of writebacks
system.cpu1.idle_fraction                    0.998413                       # Percentage of idle cycles
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.fetch_accesses                1469938                       # ITB accesses
system.cpu1.itb.fetch_acv                          57                       # ITB acv
system.cpu1.itb.fetch_hits                    1468399                       # ITB hits
system.cpu1.itb.fetch_misses                     1539                       # ITB misses
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                    8      0.02%      0.03% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal::swpctx                  470      1.46%      1.50% # number of callpals executed
system.cpu1.kern.callpal::tbi                      15      0.05%      1.54% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.02%      1.57% # number of callpals executed
system.cpu1.kern.callpal::swpipl                26238     81.66%     83.22% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2576      8.02%     91.24% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     91.25% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     4      0.01%     91.26% # number of callpals executed
system.cpu1.kern.callpal::rdusp                     2      0.01%     91.26% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.01%     91.27% # number of callpals executed
system.cpu1.kern.callpal::rti                    2607      8.11%     99.39% # number of callpals executed
system.cpu1.kern.callpal::callsys                 158      0.49%     99.88% # number of callpals executed
system.cpu1.kern.callpal::imb                      38      0.12%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 32131                       # number of callpals executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.hwrei                     39554                       # number of hwrei instructions executed
system.cpu1.kern.inst.quiesce                    2204                       # number of quiesce instructions executed
system.cpu1.kern.ipl_count::0                   10328     33.46%     33.46% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1907      6.18%     39.64% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                    110      0.36%     40.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  18518     60.00%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               30863                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                    10318     45.77%     45.77% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1907      8.46%     54.23% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                     110      0.49%     54.72% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                   10208     45.28%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                22543                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1859123008500     99.41%     99.41% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22               82001000      0.00%     99.42% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30               14064500      0.00%     99.42% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            10905353000      0.58%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1870124427000                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.999032                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.551247                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.mode_good::kernel                612                      
system.cpu1.kern.mode_good::user                  580                      
system.cpu1.kern.mode_good::idle                   32                      
system.cpu1.kern.mode_switch::kernel             1033                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                580                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2046                       # number of protection mode switches
system.cpu1.kern.mode_switch_good::kernel     0.592449                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.015640                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     1.608089                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel        1373917500      0.07%      0.07% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user           508289000      0.03%      0.10% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1868002549000     99.90%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                     471                       # number of times the context was actually changed
system.cpu1.kern.syscall::2                         2      2.00%      2.00% # number of syscalls executed
system.cpu1.kern.syscall::3                        11     11.00%     13.00% # number of syscalls executed
system.cpu1.kern.syscall::4                         2      2.00%     15.00% # number of syscalls executed
system.cpu1.kern.syscall::6                        10     10.00%     25.00% # number of syscalls executed
system.cpu1.kern.syscall::17                        6      6.00%     31.00% # number of syscalls executed
system.cpu1.kern.syscall::19                        2      2.00%     33.00% # number of syscalls executed
system.cpu1.kern.syscall::23                        2      2.00%     35.00% # number of syscalls executed
system.cpu1.kern.syscall::24                        2      2.00%     37.00% # number of syscalls executed
system.cpu1.kern.syscall::33                        4      4.00%     41.00% # number of syscalls executed
system.cpu1.kern.syscall::45                       17     17.00%     58.00% # number of syscalls executed
system.cpu1.kern.syscall::47                        2      2.00%     60.00% # number of syscalls executed
system.cpu1.kern.syscall::48                        2      2.00%     62.00% # number of syscalls executed
system.cpu1.kern.syscall::59                        3      3.00%     65.00% # number of syscalls executed
system.cpu1.kern.syscall::71                       24     24.00%     89.00% # number of syscalls executed
system.cpu1.kern.syscall::74                        8      8.00%     97.00% # number of syscalls executed
system.cpu1.kern.syscall::90                        1      1.00%     98.00% # number of syscalls executed
system.cpu1.kern.syscall::132                       2      2.00%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                   100                       # number of syscalls executed
system.cpu1.not_idle_fraction                0.001587                       # Percentage of non-idle cycles
system.cpu1.numCycles                      3740248881                       # number of cpu cycles simulated
system.cpu1.num_insts                         5931958                       # Number of instructions executed
system.cpu1.num_refs                          1926645                       # Number of memory references
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.iocache.ReadReq_accesses::1                175                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            175                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_misses::1                  175                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              175                       # number of ReadReq misses
system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
system.iocache.demand_accesses::1               41727                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41727                       # number of demand (read+write) accesses
system.iocache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
system.iocache.demand_avg_miss_latency::1            0                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
system.iocache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
system.iocache.demand_misses::1                 41727                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41727                       # number of demand (read+write) misses
system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_rate::0      no_value                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1             0                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.iocache.occ_%::1                      0.027215                       # Average percentage of cache occupancy
system.iocache.occ_blocks::1                 0.435437                       # Average occupied blocks per context
system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
system.iocache.overall_accesses::1              41727                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41727                       # number of overall (read+write) accesses
system.iocache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
system.iocache.overall_avg_miss_latency::1            0                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
system.iocache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.iocache.overall_hits::0                      0                       # number of overall hits
system.iocache.overall_hits::1                      0                       # number of overall hits
system.iocache.overall_hits::total                  0                       # number of overall hits
system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
system.iocache.overall_misses::0                    0                       # number of overall misses
system.iocache.overall_misses::1                41727                       # number of overall misses
system.iocache.overall_misses::total            41727                       # number of overall misses
system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1            0                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.iocache.replacements                     41695                       # number of replacements
system.iocache.sampled_refs                     41711                       # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
system.iocache.tagsinuse                     0.435437                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.warmup_cycle              1685787165017                       # Cycle when the warmup percentage was hit.
system.iocache.writebacks                       41520                       # number of writebacks
system.l2c.ReadExReq_accesses::0               282023                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::1                24224                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           306247                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_hits::0                     1653                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::1                      139                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 1792                       # number of ReadExReq hits
system.l2c.ReadExReq_miss_rate::0            0.994139                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::1            0.994262                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses::0                 280370                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::1                  24085                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             304455                       # number of ReadExReq misses
system.l2c.ReadReq_accesses::0                2581832                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1                 142288                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2724120                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_hits::0                    1623623                       # number of ReadReq hits
system.l2c.ReadReq_hits::1                     136766                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1760389                       # number of ReadReq hits
system.l2c.ReadReq_miss_rate::0              0.371135                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1              0.038809                       # miss rate for ReadReq accesses
system.l2c.ReadReq_misses::0                   958209                       # number of ReadReq misses
system.l2c.ReadReq_misses::1                     5522                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               963731                       # number of ReadReq misses
system.l2c.SCUpgradeReq_accesses::0             20901                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::1              1879                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total         22780                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_hits::0                     3                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::1                     4                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                 7                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_miss_rate::0         0.999856                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::1         0.997871                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_misses::0               20898                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::1                1875                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total           22773                       # number of SCUpgradeReq misses
system.l2c.UpgradeReq_accesses::0               64914                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::1                4352                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           69266                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_hits::0                      12                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::1                       3                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  15                       # number of UpgradeReq hits
system.l2c.UpgradeReq_miss_rate::0           0.999815                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::1           0.999311                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses::0                 64902                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::1                  4349                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             69251                       # number of UpgradeReq misses
system.l2c.Writeback_accesses::0               450250                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           450250                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits::0                   450250                       # number of Writeback hits
system.l2c.Writeback_hits::total               450250                       # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.l2c.avg_refs                          1.817381                       # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.demand_accesses::0                 2863855                       # number of demand (read+write) accesses
system.l2c.demand_accesses::1                  166512                       # number of demand (read+write) accesses
system.l2c.demand_accesses::2                       0                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             3030367                       # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency::0               0                       # average overall miss latency
system.l2c.demand_avg_miss_latency::1               0                       # average overall miss latency
system.l2c.demand_avg_miss_latency::2        no_value                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total     no_value                       # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency      no_value                       # average overall mshr miss latency
system.l2c.demand_hits::0                     1625276                       # number of demand (read+write) hits
system.l2c.demand_hits::1                      136905                       # number of demand (read+write) hits
system.l2c.demand_hits::2                           0                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1762181                       # number of demand (read+write) hits
system.l2c.demand_miss_latency                      0                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate::0               0.432487                       # miss rate for demand accesses
system.l2c.demand_miss_rate::1               0.177807                       # miss rate for demand accesses
system.l2c.demand_miss_rate::2               no_value                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
system.l2c.demand_misses::0                   1238579                       # number of demand (read+write) misses
system.l2c.demand_misses::1                     29607                       # number of demand (read+write) misses
system.l2c.demand_misses::2                         0                       # number of demand (read+write) misses
system.l2c.demand_misses::total               1268186                       # number of demand (read+write) misses
system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency                 0                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate::0                 0                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1                 0                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::2          no_value                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      no_value                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses                       0                       # number of demand (read+write) MSHR misses
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.l2c.occ_%::0                          0.144031                       # Average percentage of cache occupancy
system.l2c.occ_%::1                          0.004095                       # Average percentage of cache occupancy
system.l2c.occ_%::2                          0.343441                       # Average percentage of cache occupancy
system.l2c.occ_blocks::0                  9439.247714                       # Average occupied blocks per context
system.l2c.occ_blocks::1                   268.394267                       # Average occupied blocks per context
system.l2c.occ_blocks::2                 22507.731761                       # Average occupied blocks per context
system.l2c.overall_accesses::0                2863855                       # number of overall (read+write) accesses
system.l2c.overall_accesses::1                 166512                       # number of overall (read+write) accesses
system.l2c.overall_accesses::2                      0                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            3030367                       # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency::0              0                       # average overall miss latency
system.l2c.overall_avg_miss_latency::1              0                       # average overall miss latency
system.l2c.overall_avg_miss_latency::2       no_value                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total     no_value                       # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.l2c.overall_hits::0                    1625276                       # number of overall hits
system.l2c.overall_hits::1                     136905                       # number of overall hits
system.l2c.overall_hits::2                          0                       # number of overall hits
system.l2c.overall_hits::total                1762181                       # number of overall hits
system.l2c.overall_miss_latency                     0                       # number of overall miss cycles
system.l2c.overall_miss_rate::0              0.432487                       # miss rate for overall accesses
system.l2c.overall_miss_rate::1              0.177807                       # miss rate for overall accesses
system.l2c.overall_miss_rate::2              no_value                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
system.l2c.overall_misses::0                  1238579                       # number of overall misses
system.l2c.overall_misses::1                    29607                       # number of overall misses
system.l2c.overall_misses::2                        0                       # number of overall misses
system.l2c.overall_misses::total              1268186                       # number of overall misses
system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency                0                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate::0                0                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1                0                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::2         no_value                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses                      0                       # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.l2c.replacements                       1055565                       # number of replacements
system.l2c.sampled_refs                       1090545                       # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
system.l2c.tagsinuse                     32215.373742                       # Cycle average of tags in use
system.l2c.total_refs                         1981936                       # Total number of references to valid blocks.
system.l2c.warmup_cycle                     990121000                       # Cycle when the warmup percentage was hit.
system.l2c.writebacks                          123249                       # number of writebacks
system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.coalescedRxOrn       no_value                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.coalescedSwi         no_value                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.coalescedTotal       no_value                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.coalescedTxDesc      no_value                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.coalescedTxIdle      no_value                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.coalescedTxOk        no_value                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR

---------- End Simulation Statistics   ----------