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---------- Begin Simulation Statistics ----------
host_inst_rate 4370209 # Simulator instruction rate (inst/s)
host_mem_usage 276044 # Number of bytes of host memory used
host_seconds 13.74 # Real time elapsed on the host
host_tick_rate 133154437863 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 60038305 # Number of instructions simulated
sim_seconds 1.829332 # Number of seconds simulated
sim_ticks 1829332258000 # Number of ticks simulated
system.cpu.dcache.LoadLockedReq_accesses 200303 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 183141 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_rate 0.085680 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses 17162 # number of LoadLockedReq misses
system.cpu.dcache.ReadReq_accesses 9529487 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_hits 7807782 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_rate 0.180671 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1721705 # number of ReadReq misses
system.cpu.dcache.StoreCondReq_accesses 199282 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits 169415 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_miss_rate 0.149873 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_misses 29867 # number of StoreCondReq misses
system.cpu.dcache.WriteReq_accesses 6152574 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_hits 5753150 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_rate 0.064920 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 399424 # number of WriteReq misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 6.870767 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 15682061 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu.dcache.demand_hits 13560932 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.135258 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2121129 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 15682061 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 13560932 # number of overall hits
system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.135258 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2121129 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 2042700 # number of replacements
system.cpu.dcache.sampled_refs 2043212 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use
system.cpu.dcache.total_refs 14038433 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 428893 # number of writebacks
system.cpu.dtb.data_accesses 1020787 # DTB accesses
system.cpu.dtb.data_acv 367 # DTB access violations
system.cpu.dtb.data_hits 16062925 # DTB hits
system.cpu.dtb.data_misses 11471 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 728856 # DTB read accesses
system.cpu.dtb.read_acv 210 # DTB read access violations
system.cpu.dtb.read_hits 9710427 # DTB read hits
system.cpu.dtb.read_misses 10329 # DTB read misses
system.cpu.dtb.write_accesses 291931 # DTB write accesses
system.cpu.dtb.write_acv 157 # DTB write access violations
system.cpu.dtb.write_hits 6352498 # DTB write hits
system.cpu.dtb.write_misses 1142 # DTB write misses
system.cpu.icache.ReadReq_accesses 60050143 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_hits 59129922 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_rate 0.015324 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 920221 # number of ReadReq misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 64.264250 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 60050143 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu.icache.demand_hits 59129922 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.015324 # miss rate for demand accesses
system.cpu.icache.demand_misses 920221 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 60050143 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 59129922 # number of overall hits
system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.015324 # miss rate for overall accesses
system.cpu.icache.overall_misses 920221 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 919594 # number of replacements
system.cpu.icache.sampled_refs 920106 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 511.215243 # Cycle average of tags in use
system.cpu.icache.total_refs 59129922 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0.983585 # Percentage of idle cycles
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 4979654 # ITB accesses
system.cpu.itb.fetch_acv 184 # ITB acv
system.cpu.itb.fetch_hits 4974648 # ITB hits
system.cpu.itb.fetch_misses 5006 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed
system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed
system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed
system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed
system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
system.cpu.kern.callpal::total 192180 # number of callpals executed
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed
system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed
system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl
system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0 1811927407500 99.05% 99.05% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total 1829332050500 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.mode_good::kernel 1909
system.cpu.kern.mode_good::user 1738
system.cpu.kern.mode_good::idle 171
system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches
system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 1.402439 # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
system.cpu.kern.syscall::total 326 # number of syscalls executed
system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles
system.cpu.numCycles 3658664408 # number of cpu cycles simulated
system.cpu.num_insts 60038305 # Number of instructions executed
system.cpu.num_refs 16311238 # Number of memory references
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.iocache.ReadReq_accesses 174 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_misses 174 # number of ReadReq misses
system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_misses 41552 # number of WriteReq misses
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_accesses 41726 # number of demand (read+write) accesses
system.iocache.demand_avg_miss_latency 0 # average overall miss latency
system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.iocache.demand_hits 0 # number of demand (read+write) hits
system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.iocache.demand_miss_rate 1 # miss rate for demand accesses
system.iocache.demand_misses 41726 # number of demand (read+write) misses
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.overall_accesses 41726 # number of overall (read+write) accesses
system.iocache.overall_avg_miss_latency 0 # average overall miss latency
system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.iocache.overall_hits 0 # number of overall hits
system.iocache.overall_miss_latency 0 # number of overall miss cycles
system.iocache.overall_miss_rate 1 # miss rate for overall accesses
system.iocache.overall_misses 41726 # number of overall misses
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.iocache.replacements 41686 # number of replacements
system.iocache.sampled_refs 41702 # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.iocache.tagsinuse 1.225570 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit.
system.iocache.writebacks 41512 # number of writebacks
system.l2c.ReadExReq_accesses 304346 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses 304346 # number of ReadExReq misses
system.l2c.ReadReq_accesses 2659071 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_hits 1696652 # number of ReadReq hits
system.l2c.ReadReq_miss_rate 0.361938 # miss rate for ReadReq accesses
system.l2c.ReadReq_misses 962419 # number of ReadReq misses
system.l2c.UpgradeReq_accesses 124945 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses 124945 # number of UpgradeReq misses
system.l2c.Writeback_accesses 428893 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits 428893 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.avg_refs 1.727246 # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.demand_accesses 2963417 # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency 0 # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.l2c.demand_hits 1696652 # number of demand (read+write) hits
system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate 0.427468 # miss rate for demand accesses
system.l2c.demand_misses 1266765 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.overall_accesses 2963417 # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency 0 # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.l2c.overall_hits 1696652 # number of overall hits
system.l2c.overall_miss_latency 0 # number of overall miss cycles
system.l2c.overall_miss_rate 0.427468 # miss rate for overall accesses
system.l2c.overall_misses 1266765 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.replacements 1050724 # number of replacements
system.l2c.sampled_refs 1081067 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.l2c.tagsinuse 30228.585605 # Cycle average of tags in use
system.l2c.total_refs 1867269 # Total number of references to valid blocks.
system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit.
system.l2c.writebacks 119147 # number of writebacks
system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post
system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post
system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
---------- End Simulation Statistics ----------
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