path: root/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt

---------- Begin Simulation Statistics ----------
host_inst_rate                                 737386                       # Simulator instruction rate (inst/s)
host_mem_usage                                 319080                       # Number of bytes of host memory used
host_seconds                                    85.79                       # Real time elapsed on the host
host_tick_rate                            22995378041                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                    63257216                       # Number of instructions simulated
sim_seconds                                  1.972680                       # Number of seconds simulated
sim_ticks                                1972679592000                       # Number of ticks simulated
system.cpu0.dcache.LoadLockedReq_accesses       192278                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_avg_miss_latency 13965.504894                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10965.504894                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_hits          175522                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_miss_latency    234006000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_rate     0.087145                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_misses         16756                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    183738000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate     0.087145                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_misses        16756                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.ReadReq_accesses           9119152                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_avg_miss_latency 21251.410270                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 18251.386941                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_hits               7426037                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_miss_latency   35981081500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_rate         0.185666                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_misses             1693115                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_mshr_miss_latency  30901697000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate     0.185666                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_misses        1693115                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    857399000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_accesses       191314                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_avg_miss_latency 26686.254525                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 23686.254525                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_hits           162861                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_miss_latency    759304000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_rate     0.148724                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_misses          28453                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_mshr_miss_latency    673945000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_rate     0.148724                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_misses        28453                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.WriteReq_accesses          5834436                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_avg_miss_latency 26949.612638                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 23949.612638                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_hits              5455075                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_miss_latency  10223632000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_rate        0.065021                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_misses             379361                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_mshr_miss_latency   9085549000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_rate     0.065021                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_misses        379361                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1211657000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_refs                  6.692591                       # Average number of references to valid blocks.
system.cpu0.dcache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.demand_accesses           14953588                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_avg_miss_latency 22294.450454                       # average overall miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency 19294.431395                       # average overall mshr miss latency
system.cpu0.dcache.demand_hits               12881112                       # number of demand (read+write) hits
system.cpu0.dcache.demand_miss_latency    46204713500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_rate          0.138594                       # miss rate for demand accesses
system.cpu0.dcache.demand_misses              2072476                       # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_miss_latency  39987246000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_rate     0.138594                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_misses         2072476                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.overall_accesses          14953588                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_avg_miss_latency 22294.450454                       # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency 19294.431395                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_hits              12881112                       # number of overall hits
system.cpu0.dcache.overall_miss_latency   46204713500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_rate         0.138594                       # miss rate for overall accesses
system.cpu0.dcache.overall_misses             2072476                       # number of overall misses
system.cpu0.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_miss_latency  39987246000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_rate     0.138594                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_misses        2072476                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_latency   2069056000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu0.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu0.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu0.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu0.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu0.dcache.replacements               1992967                       # number of replacements
system.cpu0.dcache.sampled_refs               1993479                       # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.dcache.tagsinuse               503.888732                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                13341539                       # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              66395000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.writebacks                  403713                       # number of writebacks
system.cpu0.dtb.accesses                       719861                       # DTB accesses
system.cpu0.dtb.acv                               289                       # DTB access violations
system.cpu0.dtb.hits                         15321442                       # DTB hits
system.cpu0.dtb.misses                           8487                       # DTB misses
system.cpu0.dtb.read_accesses                  524202                       # DTB read accesses
system.cpu0.dtb.read_acv                          174                       # DTB read access violations
system.cpu0.dtb.read_hits                     9294921                       # DTB read hits
system.cpu0.dtb.read_misses                      7689                       # DTB read misses
system.cpu0.dtb.write_accesses                 195659                       # DTB write accesses
system.cpu0.dtb.write_acv                         115                       # DTB write access violations
system.cpu0.dtb.write_hits                    6026521                       # DTB write hits
system.cpu0.dtb.write_misses                      798                       # DTB write misses
system.cpu0.icache.ReadReq_accesses          57943269                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_avg_miss_latency 14213.482115                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11212.730813                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_hits              57028190                       # number of ReadReq hits
system.cpu0.icache.ReadReq_miss_latency   13006459000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_rate         0.015793                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_misses              915079                       # number of ReadReq misses
system.cpu0.icache.ReadReq_mshr_miss_latency  10260534500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate     0.015793                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_misses         915079                       # number of ReadReq MSHR misses
system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu0.icache.avg_refs                 62.327526                       # Average number of references to valid blocks.
system.cpu0.icache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu0.icache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.demand_accesses           57943269                       # number of demand (read+write) accesses
system.cpu0.icache.demand_avg_miss_latency 14213.482115                       # average overall miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency 11212.730813                       # average overall mshr miss latency
system.cpu0.icache.demand_hits               57028190                       # number of demand (read+write) hits
system.cpu0.icache.demand_miss_latency    13006459000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_rate          0.015793                       # miss rate for demand accesses
system.cpu0.icache.demand_misses               915079                       # number of demand (read+write) misses
system.cpu0.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_miss_latency  10260534500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_rate     0.015793                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_misses          915079                       # number of demand (read+write) MSHR misses
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.overall_accesses          57943269                       # number of overall (read+write) accesses
system.cpu0.icache.overall_avg_miss_latency 14213.482115                       # average overall miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency 11212.730813                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_hits              57028190                       # number of overall hits
system.cpu0.icache.overall_miss_latency   13006459000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_rate         0.015793                       # miss rate for overall accesses
system.cpu0.icache.overall_misses              915079                       # number of overall misses
system.cpu0.icache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_miss_latency  10260534500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_rate     0.015793                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_misses         915079                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu0.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu0.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu0.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu0.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu0.icache.replacements                914464                       # number of replacements
system.cpu0.icache.sampled_refs                914976                       # Sample count of references to valid blocks.
system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.icache.tagsinuse               507.411447                       # Cycle average of tags in use
system.cpu0.icache.total_refs                57028190                       # Total number of references to valid blocks.
system.cpu0.icache.warmup_cycle           49269353000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.writebacks                       0                       # number of writebacks
system.cpu0.idle_fraction                    0.932800                       # Percentage of idle cycles
system.cpu0.itb.accesses                      3949472                       # ITB accesses
system.cpu0.itb.acv                               143                       # ITB acv
system.cpu0.itb.hits                          3945631                       # ITB hits
system.cpu0.itb.misses                           3841                       # ITB misses
system.cpu0.kern.callpal                       187580                       # number of callpals executed
system.cpu0.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal_wripir                    94      0.05%      0.05% # number of callpals executed
system.cpu0.kern.callpal_wrmces                     1      0.00%      0.05% # number of callpals executed
system.cpu0.kern.callpal_wrfen                      1      0.00%      0.05% # number of callpals executed
system.cpu0.kern.callpal_wrvptptr                   1      0.00%      0.05% # number of callpals executed
system.cpu0.kern.callpal_swpctx                  3867      2.06%      2.11% # number of callpals executed
system.cpu0.kern.callpal_tbi                       44      0.02%      2.14% # number of callpals executed
system.cpu0.kern.callpal_wrent                      7      0.00%      2.14% # number of callpals executed
system.cpu0.kern.callpal_swpipl                171680     91.52%     93.66% # number of callpals executed
system.cpu0.kern.callpal_rdps                    6661      3.55%     97.22% # number of callpals executed
system.cpu0.kern.callpal_wrkgp                      1      0.00%     97.22% # number of callpals executed
system.cpu0.kern.callpal_wrusp                      4      0.00%     97.22% # number of callpals executed
system.cpu0.kern.callpal_rdusp                      7      0.00%     97.22% # number of callpals executed
system.cpu0.kern.callpal_whami                      2      0.00%     97.22% # number of callpals executed
system.cpu0.kern.callpal_rti                     4704      2.51%     99.73% # number of callpals executed
system.cpu0.kern.callpal_callsys                  356      0.19%     99.92% # number of callpals executed
system.cpu0.kern.callpal_imb                      149      0.08%    100.00% # number of callpals executed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.hwrei                    202457                       # number of hwrei instructions executed
system.cpu0.kern.inst.quiesce                    6163                       # number of quiesce instructions executed
system.cpu0.kern.ipl_count                     178500                       # number of times we switched to this ipl
system.cpu0.kern.ipl_count_0                    72488     40.61%     40.61% # number of times we switched to this ipl
system.cpu0.kern.ipl_count_21                     131      0.07%     40.68% # number of times we switched to this ipl
system.cpu0.kern.ipl_count_22                    1977      1.11%     41.79% # number of times we switched to this ipl
system.cpu0.kern.ipl_count_30                       7      0.00%     41.79% # number of times we switched to this ipl
system.cpu0.kern.ipl_count_31                  103897     58.21%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_good                      144346                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good_0                     71119     49.27%     49.27% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good_21                      131      0.09%     49.36% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good_22                     1977      1.37%     50.73% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good_30                        7      0.00%     50.74% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good_31                    71112     49.26%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks               1972678821000                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_0             1900126420500     96.32%     96.32% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_21                86973000      0.00%     96.33% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_22               568583000      0.03%     96.36% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_30                 5546500      0.00%     96.36% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_31             71891298000      3.64%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used_0                  0.981114                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used_21                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used_22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used_30                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used_31                 0.684447                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.mode_good_kernel                1228                      
system.cpu0.kern.mode_good_user                  1229                      
system.cpu0.kern.mode_good_idle                     0                      
system.cpu0.kern.mode_switch_kernel              7227                       # number of protection mode switches
system.cpu0.kern.mode_switch_user                1229                       # number of protection mode switches
system.cpu0.kern.mode_switch_idle                   0                       # number of protection mode switches
system.cpu0.kern.mode_switch_good        <err: div-0>                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good_kernel     0.169918                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good_user              1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good_idle   <err: div-0>                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks_kernel       1969223377000     99.82%     99.82% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks_user           3455442000      0.18%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks_idle                    0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3868                       # number of times the context was actually changed
system.cpu0.kern.syscall                          224                       # number of syscalls executed
system.cpu0.kern.syscall_2                          6      2.68%      2.68% # number of syscalls executed
system.cpu0.kern.syscall_3                         19      8.48%     11.16% # number of syscalls executed
system.cpu0.kern.syscall_4                          3      1.34%     12.50% # number of syscalls executed
system.cpu0.kern.syscall_6                         30     13.39%     25.89% # number of syscalls executed
system.cpu0.kern.syscall_12                         1      0.45%     26.34% # number of syscalls executed
system.cpu0.kern.syscall_15                         1      0.45%     26.79% # number of syscalls executed
system.cpu0.kern.syscall_17                        10      4.46%     31.25% # number of syscalls executed
system.cpu0.kern.syscall_19                         6      2.68%     33.93% # number of syscalls executed
system.cpu0.kern.syscall_20                         4      1.79%     35.71% # number of syscalls executed
system.cpu0.kern.syscall_23                         2      0.89%     36.61% # number of syscalls executed
system.cpu0.kern.syscall_24                         4      1.79%     38.39% # number of syscalls executed
system.cpu0.kern.syscall_33                         8      3.57%     41.96% # number of syscalls executed
system.cpu0.kern.syscall_41                         2      0.89%     42.86% # number of syscalls executed
system.cpu0.kern.syscall_45                        39     17.41%     60.27% # number of syscalls executed
system.cpu0.kern.syscall_47                         4      1.79%     62.05% # number of syscalls executed
system.cpu0.kern.syscall_48                         7      3.12%     65.18% # number of syscalls executed
system.cpu0.kern.syscall_54                         9      4.02%     69.20% # number of syscalls executed
system.cpu0.kern.syscall_58                         1      0.45%     69.64% # number of syscalls executed
system.cpu0.kern.syscall_59                         5      2.23%     71.88% # number of syscalls executed
system.cpu0.kern.syscall_71                        32     14.29%     86.16% # number of syscalls executed
system.cpu0.kern.syscall_73                         3      1.34%     87.50% # number of syscalls executed
system.cpu0.kern.syscall_74                         9      4.02%     91.52% # number of syscalls executed
system.cpu0.kern.syscall_87                         1      0.45%     91.96% # number of syscalls executed
system.cpu0.kern.syscall_90                         2      0.89%     92.86% # number of syscalls executed
system.cpu0.kern.syscall_92                         7      3.12%     95.98% # number of syscalls executed
system.cpu0.kern.syscall_97                         2      0.89%     96.87% # number of syscalls executed
system.cpu0.kern.syscall_98                         2      0.89%     97.77% # number of syscalls executed
system.cpu0.kern.syscall_132                        2      0.89%     98.66% # number of syscalls executed
system.cpu0.kern.syscall_144                        1      0.45%     99.11% # number of syscalls executed
system.cpu0.kern.syscall_147                        2      0.89%    100.00% # number of syscalls executed
system.cpu0.not_idle_fraction                0.067200                       # Percentage of non-idle cycles
system.cpu0.numCycles                      3945359184                       # number of cpu cycles simulated
system.cpu0.num_insts                        57934492                       # Number of instructions executed
system.cpu0.num_refs                         15562811                       # Number of memory references
system.cpu1.dcache.LoadLockedReq_accesses        12625                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_avg_miss_latency 12190.944882                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency  9190.944882                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_hits           11609                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_miss_latency     12386000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_rate     0.080475                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_misses          1016                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency      9338000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate     0.080475                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_misses         1016                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.ReadReq_accesses           1030298                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_avg_miss_latency 13948.255862                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 10948.131577                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_hits                994091                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_miss_latency     505024500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_rate         0.035142                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_misses               36207                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_mshr_miss_latency    396399000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate     0.035142                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_misses          36207                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency     13393500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.StoreCondReq_accesses        12560                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_avg_miss_latency 22874.692875                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 19874.692875                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_hits            10118                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_miss_latency     55860000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_rate     0.194427                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_misses           2442                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_mshr_miss_latency     48534000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_rate     0.194427                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_misses         2442                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.WriteReq_accesses           657926                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_avg_miss_latency 26378.844865                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 23378.844865                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_hits               631072                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_miss_latency    708377500                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_rate        0.040816                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_misses              26854                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_mshr_miss_latency    627815500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_rate     0.040816                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_misses         26854                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    305665000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_refs                 30.077708                       # Average number of references to valid blocks.
system.cpu1.dcache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.demand_accesses            1688224                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_avg_miss_latency 19241.718336                       # average overall miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency 16241.646977                       # average overall mshr miss latency
system.cpu1.dcache.demand_hits                1625163                       # number of demand (read+write) hits
system.cpu1.dcache.demand_miss_latency     1213402000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_rate          0.037353                       # miss rate for demand accesses
system.cpu1.dcache.demand_misses                63061                       # number of demand (read+write) misses
system.cpu1.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_miss_latency   1024214500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_rate     0.037353                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_misses           63061                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.overall_accesses           1688224                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_avg_miss_latency 19241.718336                       # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency 16241.646977                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_hits               1625163                       # number of overall hits
system.cpu1.dcache.overall_miss_latency    1213402000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_rate         0.037353                       # miss rate for overall accesses
system.cpu1.dcache.overall_misses               63061                       # number of overall misses
system.cpu1.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_miss_latency   1024214500                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_rate     0.037353                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_misses          63061                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_latency    319058500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu1.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu1.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu1.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu1.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.dcache.replacements                 54390                       # number of replacements
system.cpu1.dcache.sampled_refs                 54808                       # Sample count of references to valid blocks.
system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.dcache.tagsinuse               387.947804                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                 1648499                       # Total number of references to valid blocks.
system.cpu1.dcache.warmup_cycle          1956976796000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.writebacks                   27227                       # number of writebacks
system.cpu1.dtb.accesses                       302878                       # DTB accesses
system.cpu1.dtb.acv                                84                       # DTB access violations
system.cpu1.dtb.hits                          1712100                       # DTB hits
system.cpu1.dtb.misses                           3106                       # DTB misses
system.cpu1.dtb.read_accesses                  205838                       # DTB read accesses
system.cpu1.dtb.read_acv                           36                       # DTB read access violations
system.cpu1.dtb.read_hits                     1039743                       # DTB read hits
system.cpu1.dtb.read_misses                      2750                       # DTB read misses
system.cpu1.dtb.write_accesses                  97040                       # DTB write accesses
system.cpu1.dtb.write_acv                          48                       # DTB write access violations
system.cpu1.dtb.write_hits                     672357                       # DTB write hits
system.cpu1.dtb.write_misses                      356                       # DTB write misses
system.cpu1.icache.ReadReq_accesses           5325914                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_avg_miss_latency 14299.912084                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11299.461372                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_hits               5236056                       # number of ReadReq hits
system.cpu1.icache.ReadReq_miss_latency    1284961500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_rate         0.016872                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_misses               89858                       # number of ReadReq misses
system.cpu1.icache.ReadReq_mshr_miss_latency   1015347000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate     0.016872                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_misses          89858                       # number of ReadReq MSHR misses
system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu1.icache.avg_refs                 58.288501                       # Average number of references to valid blocks.
system.cpu1.icache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu1.icache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.demand_accesses            5325914                       # number of demand (read+write) accesses
system.cpu1.icache.demand_avg_miss_latency 14299.912084                       # average overall miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency 11299.461372                       # average overall mshr miss latency
system.cpu1.icache.demand_hits                5236056                       # number of demand (read+write) hits
system.cpu1.icache.demand_miss_latency     1284961500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_rate          0.016872                       # miss rate for demand accesses
system.cpu1.icache.demand_misses                89858                       # number of demand (read+write) misses
system.cpu1.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_miss_latency   1015347000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_rate     0.016872                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_misses           89858                       # number of demand (read+write) MSHR misses
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.overall_accesses           5325914                       # number of overall (read+write) accesses
system.cpu1.icache.overall_avg_miss_latency 14299.912084                       # average overall miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency 11299.461372                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_hits               5236056                       # number of overall hits
system.cpu1.icache.overall_miss_latency    1284961500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_rate         0.016872                       # miss rate for overall accesses
system.cpu1.icache.overall_misses               89858                       # number of overall misses
system.cpu1.icache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_miss_latency   1015347000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_rate     0.016872                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_misses          89858                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu1.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu1.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu1.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu1.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.icache.replacements                 89318                       # number of replacements
system.cpu1.icache.sampled_refs                 89830                       # Sample count of references to valid blocks.
system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.icache.tagsinuse               419.412997                       # Cycle average of tags in use
system.cpu1.icache.total_refs                 5236056                       # Total number of references to valid blocks.
system.cpu1.icache.warmup_cycle          1957297672000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.writebacks                       0                       # number of writebacks
system.cpu1.idle_fraction                    0.995045                       # Percentage of idle cycles
system.cpu1.itb.accesses                      1398451                       # ITB accesses
system.cpu1.itb.acv                                41                       # ITB acv
system.cpu1.itb.hits                          1397205                       # ITB hits
system.cpu1.itb.misses                           1246                       # ITB misses
system.cpu1.kern.callpal                        29654                       # number of callpals executed
system.cpu1.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal_wripir                     7      0.02%      0.03% # number of callpals executed
system.cpu1.kern.callpal_wrmces                     1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal_wrfen                      1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal_swpctx                   369      1.24%      1.28% # number of callpals executed
system.cpu1.kern.callpal_tbi                       10      0.03%      1.31% # number of callpals executed
system.cpu1.kern.callpal_wrent                      7      0.02%      1.34% # number of callpals executed
system.cpu1.kern.callpal_swpipl                 24277     81.87%     83.20% # number of callpals executed
system.cpu1.kern.callpal_rdps                    2191      7.39%     90.59% # number of callpals executed
system.cpu1.kern.callpal_wrkgp                      1      0.00%     90.59% # number of callpals executed
system.cpu1.kern.callpal_wrusp                      3      0.01%     90.60% # number of callpals executed
system.cpu1.kern.callpal_rdusp                      2      0.01%     90.61% # number of callpals executed
system.cpu1.kern.callpal_whami                      3      0.01%     90.62% # number of callpals executed
system.cpu1.kern.callpal_rti                     2588      8.73%     99.35% # number of callpals executed
system.cpu1.kern.callpal_callsys                  161      0.54%     99.89% # number of callpals executed
system.cpu1.kern.callpal_imb                       31      0.10%    100.00% # number of callpals executed
system.cpu1.kern.callpal_rdunique                   1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.hwrei                     36198                       # number of hwrei instructions executed
system.cpu1.kern.inst.quiesce                    2401                       # number of quiesce instructions executed
system.cpu1.kern.ipl_count                      28931                       # number of times we switched to this ipl
system.cpu1.kern.ipl_count_0                     9254     31.99%     31.99% # number of times we switched to this ipl
system.cpu1.kern.ipl_count_22                    1971      6.81%     38.80% # number of times we switched to this ipl
system.cpu1.kern.ipl_count_30                      94      0.32%     39.12% # number of times we switched to this ipl
system.cpu1.kern.ipl_count_31                   17612     60.88%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_good                       20463                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good_0                      9246     45.18%     45.18% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good_22                     1971      9.63%     54.82% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good_30                       94      0.46%     55.28% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good_31                     9152     44.72%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks               1972666579000                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks_0             1919200833000     97.29%     97.29% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks_22               508731500      0.03%     97.32% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks_30                56757500      0.00%     97.32% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks_31             52900257000      2.68%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used_0                  0.999136                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used_22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used_30                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used_31                 0.519646                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.mode_good_kernel                 533                      
system.cpu1.kern.mode_good_user                   515                      
system.cpu1.kern.mode_good_idle                    18                      
system.cpu1.kern.mode_switch_kernel               882                       # number of protection mode switches
system.cpu1.kern.mode_switch_user                 515                       # number of protection mode switches
system.cpu1.kern.mode_switch_idle                2077                       # number of protection mode switches
system.cpu1.kern.mode_switch_good            1.612975                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good_kernel     0.604308                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good_user              1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good_idle       0.008666                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks_kernel         3978131000      0.20%      0.20% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks_user           1616488000      0.08%      0.28% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks_idle         1966135435000     99.72%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                     370                       # number of times the context was actually changed
system.cpu1.kern.syscall                          102                       # number of syscalls executed
system.cpu1.kern.syscall_2                          2      1.96%      1.96% # number of syscalls executed
system.cpu1.kern.syscall_3                         11     10.78%     12.75% # number of syscalls executed
system.cpu1.kern.syscall_4                          1      0.98%     13.73% # number of syscalls executed
system.cpu1.kern.syscall_6                         12     11.76%     25.49% # number of syscalls executed
system.cpu1.kern.syscall_17                         5      4.90%     30.39% # number of syscalls executed
system.cpu1.kern.syscall_19                         4      3.92%     34.31% # number of syscalls executed
system.cpu1.kern.syscall_20                         2      1.96%     36.27% # number of syscalls executed
system.cpu1.kern.syscall_23                         2      1.96%     38.24% # number of syscalls executed
system.cpu1.kern.syscall_24                         2      1.96%     40.20% # number of syscalls executed
system.cpu1.kern.syscall_33                         3      2.94%     43.14% # number of syscalls executed
system.cpu1.kern.syscall_45                        15     14.71%     57.84% # number of syscalls executed
system.cpu1.kern.syscall_47                         2      1.96%     59.80% # number of syscalls executed
system.cpu1.kern.syscall_48                         3      2.94%     62.75% # number of syscalls executed
system.cpu1.kern.syscall_54                         1      0.98%     63.73% # number of syscalls executed
system.cpu1.kern.syscall_59                         2      1.96%     65.69% # number of syscalls executed
system.cpu1.kern.syscall_71                        22     21.57%     87.25% # number of syscalls executed
system.cpu1.kern.syscall_74                         7      6.86%     94.12% # number of syscalls executed
system.cpu1.kern.syscall_90                         1      0.98%     95.10% # number of syscalls executed
system.cpu1.kern.syscall_92                         2      1.96%     97.06% # number of syscalls executed
system.cpu1.kern.syscall_132                        2      1.96%     99.02% # number of syscalls executed
system.cpu1.kern.syscall_144                        1      0.98%    100.00% # number of syscalls executed
system.cpu1.not_idle_fraction                0.004955                       # Percentage of non-idle cycles
system.cpu1.numCycles                      3945333218                       # number of cpu cycles simulated
system.cpu1.num_insts                         5322724                       # Number of instructions executed
system.cpu1.num_refs                          1722033                       # Number of memory references
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.iocache.ReadReq_accesses                   176                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_avg_miss_latency  113562.488636                       # average ReadReq miss latency
system.iocache.ReadReq_avg_mshr_miss_latency 61562.488636                       # average ReadReq mshr miss latency
system.iocache.ReadReq_miss_latency          19986998                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_rate                    1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_misses                     176                       # number of ReadReq misses
system.iocache.ReadReq_mshr_miss_latency     10834998                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate               1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_misses                176                       # number of ReadReq MSHR misses
system.iocache.WriteReq_accesses                41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_avg_miss_latency 115053.879621                       # average WriteReq miss latency
system.iocache.WriteReq_avg_mshr_miss_latency 63053.711494                       # average WriteReq mshr miss latency
system.iocache.WriteReq_miss_latency       4780718806                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_rate                   1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_misses                  41552                       # number of WriteReq misses
system.iocache.WriteReq_mshr_miss_latency   2620007820                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_rate              1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
system.iocache.avg_blocked_cycles_no_mshrs  4173.944424                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.blocked_no_mshrs                  2771                       # number of cycles access was blocked
system.iocache.blocked_no_targets                   0                       # number of cycles access was blocked
system.iocache.blocked_cycles_no_mshrs       11566000                       # number of cycles access was blocked
system.iocache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.demand_accesses                  41728                       # number of demand (read+write) accesses
system.iocache.demand_avg_miss_latency   115047.589245                       # average overall miss latency
system.iocache.demand_avg_mshr_miss_latency 63047.421827                       # average overall mshr miss latency
system.iocache.demand_hits                          0                       # number of demand (read+write) hits
system.iocache.demand_miss_latency         4800705804                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_rate                     1                       # miss rate for demand accesses
system.iocache.demand_misses                    41728                       # number of demand (read+write) misses
system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
system.iocache.demand_mshr_miss_latency    2630842818                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_rate                1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_misses               41728                       # number of demand (read+write) MSHR misses
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.iocache.overall_accesses                 41728                       # number of overall (read+write) accesses
system.iocache.overall_avg_miss_latency  115047.589245                       # average overall miss latency
system.iocache.overall_avg_mshr_miss_latency 63047.421827                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.iocache.overall_hits                         0                       # number of overall hits
system.iocache.overall_miss_latency        4800705804                       # number of overall miss cycles
system.iocache.overall_miss_rate                    1                       # miss rate for overall accesses
system.iocache.overall_misses                   41728                       # number of overall misses
system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
system.iocache.overall_mshr_miss_latency   2630842818                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_rate               1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_misses              41728                       # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.iocache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.iocache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.iocache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.iocache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.iocache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.iocache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.iocache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.iocache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.iocache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.iocache.replacements                     41696                       # number of replacements
system.iocache.sampled_refs                     41712                       # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
system.iocache.tagsinuse                     0.554980                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.warmup_cycle              1766170681000                       # Cycle when the warmup percentage was hit.
system.iocache.writebacks                       41520                       # number of writebacks
system.l2c.ReadExReq_accesses                  307159                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_avg_miss_latency    23004.538366                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 11004.538366                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_miss_latency          7066051000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_rate                      1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses                    307159                       # number of ReadExReq misses
system.l2c.ReadExReq_mshr_miss_latency     3380143000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate                 1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_misses               307159                       # number of ReadExReq MSHR misses
system.l2c.ReadReq_accesses                   2746056                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_avg_miss_latency      23013.053198                       # average ReadReq miss latency
system.l2c.ReadReq_avg_mshr_miss_latency 11012.812299                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_hits                       1782997                       # number of ReadReq hits
system.l2c.ReadReq_miss_latency           22162928000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_rate                 0.350706                       # miss rate for ReadReq accesses
system.l2c.ReadReq_misses                      963059                       # number of ReadReq misses
system.l2c.ReadReq_mshr_hits                       11                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_miss_latency      10605988000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate            0.350706                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_misses                 963059                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_uncacheable_latency    779852500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.UpgradeReq_accesses                 127459                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_avg_miss_latency   22445.817871                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 11007.104245                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_miss_latency         2860921500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_rate                     1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses                   127459                       # number of UpgradeReq misses
system.l2c.UpgradeReq_mshr_miss_latency    1402954500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_rate                1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_misses              127459                       # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_mshr_uncacheable_latency   1370781000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.Writeback_accesses                  430940                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits                      430940                       # number of Writeback hits
system.l2c.avg_blocked_cycles_no_mshrs   <err: div-0>                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.l2c.avg_refs                          1.813929                       # Average number of references to valid blocks.
system.l2c.blocked_no_mshrs                         0                       # number of cycles access was blocked
system.l2c.blocked_no_targets                       0                       # number of cycles access was blocked
system.l2c.blocked_cycles_no_mshrs                  0                       # number of cycles access was blocked
system.l2c.blocked_cycles_no_targets                0                       # number of cycles access was blocked
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.demand_accesses                    3053215                       # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency       23010.994176                       # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency  11010.811530                       # average overall mshr miss latency
system.l2c.demand_hits                        1782997                       # number of demand (read+write) hits
system.l2c.demand_miss_latency            29228979000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate                  0.416026                       # miss rate for demand accesses
system.l2c.demand_misses                      1270218                       # number of demand (read+write) misses
system.l2c.demand_mshr_hits                        11                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency       13986131000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate             0.416026                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses                 1270218                       # number of demand (read+write) MSHR misses
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.l2c.overall_accesses                   3053215                       # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency      23010.994176                       # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency 11010.811530                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.l2c.overall_hits                       1782997                       # number of overall hits
system.l2c.overall_miss_latency           29228979000                       # number of overall miss cycles
system.l2c.overall_miss_rate                 0.416026                       # miss rate for overall accesses
system.l2c.overall_misses                     1270218                       # number of overall misses
system.l2c.overall_mshr_hits                       11                       # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency      13986131000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate            0.416026                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses                1270218                       # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency   2150633500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.l2c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.l2c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.l2c.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.l2c.prefetcher.num_hwpf_evicted              0                       # number of hwpf removed due to no buffer left
system.l2c.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.l2c.prefetcher.num_hwpf_issued               0                       # number of hwpf issued
system.l2c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.l2c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.l2c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.l2c.replacements                       1055829                       # number of replacements
system.l2c.sampled_refs                       1087019                       # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
system.l2c.tagsinuse                     30866.493853                       # Cycle average of tags in use
system.l2c.total_refs                         1971775                       # Total number of references to valid blocks.
system.l2c.warmup_cycle                    7281125000                       # Cycle when the warmup percentage was hit.
system.l2c.writebacks                          123132                       # number of writebacks
system.tsunami.ethernet.coalescedRxDesc  <err: div-0>                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle  <err: div-0>                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk    <err: div-0>                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.coalescedRxOrn   <err: div-0>                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.coalescedSwi     <err: div-0>                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.coalescedTotal   <err: div-0>                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.coalescedTxDesc  <err: div-0>                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.coalescedTxIdle  <err: div-0>                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.coalescedTxOk    <err: div-0>                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR

---------- End Simulation Statistics   ----------