path: root/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000104                       # Number of seconds simulated
sim_ticks                                   104204500                       # Number of ticks simulated
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  98850                       # Simulator instruction rate (inst/s)
host_tick_rate                               10137150                       # Simulator tick rate (ticks/s)
host_mem_usage                                 260004                       # Number of bytes of host memory used
host_seconds                                    10.28                       # Real time elapsed on the host
sim_insts                                     1016120                       # Number of instructions simulated
system.cpu0.workload.num_syscalls                  89                       # Number of system calls
system.cpu0.numCycles                          208410                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.BPredUnit.lookups                   80590                       # Number of BP lookups
system.cpu0.BPredUnit.condPredicted             78618                       # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect              1041                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups                79686                       # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits                   77242                       # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS                     414                       # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect                132                       # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles             16537                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                        478571                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                      80590                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches             77656                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                       158025                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                   3261                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles                 12770                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles         1227                       # Number of stall cycles due to pending traps
system.cpu0.fetch.CacheLines                     5521                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes                  450                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples            190625                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             2.510536                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.192774                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                   32600     17.10%     17.10% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                   78462     41.16%     58.26% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                     548      0.29%     58.55% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                    1030      0.54%     59.09% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                     642      0.34%     59.43% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                   74529     39.10%     98.52% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                     776      0.41%     98.93% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                     250      0.13%     99.06% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                    1788      0.94%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total              190625                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.386690                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       2.296296                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                   16909                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles                14231                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                   157125                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles                  299                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                  2061                       # Number of cycles decode is squashing
system.cpu0.decode.DecodedInsts                476395                       # Number of instructions handled by decode
system.cpu0.rename.SquashCycles                  2061                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                   17525                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                   1226                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles         12360                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                   156835                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles                  618                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts                473886                       # Number of instructions processed by rename
system.cpu0.rename.IQFullEvents                     5                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents                  214                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands             323802                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups               945058                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups          945058                       # Number of integer rename lookups
system.cpu0.rename.CommittedMaps               313352                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                   10450                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts               798                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts           821                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                     3525                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads              151968                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores              76679                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads            74216                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores           74111                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                    396475                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded                848                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                   394743                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued               99                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined           8405                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined         7242                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved           289                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples       190625                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        2.070783                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.085610                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0              31655     16.61%     16.61% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1               5136      2.69%     19.30% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2              75959     39.85%     59.15% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3              75246     39.47%     98.62% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4               1565      0.82%     99.44% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5                775      0.41%     99.85% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                215      0.11%     99.96% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                 66      0.03%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                  8      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total         190625                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                     35     15.42%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     15.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                    74     32.60%     48.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite                  118     51.98%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu               166789     42.25%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead              151686     38.43%     80.68% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite              76268     19.32%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total                394743                       # Type of FU issued
system.cpu0.iq.rate                          1.894069                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                        227                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.000575                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads            980437                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes           405782                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses       393268                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses                394970                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads           73850                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads         1708                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation           55                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores         1043                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked           18                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                  2061                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                    862                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles                   25                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts             472051                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts              355                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts               151968                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts               76679                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts               747                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                    23                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents            55                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect           456                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect          747                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts                1203                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts               393858                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts               151382                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts              885                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                        74728                       # number of nop insts executed
system.cpu0.iew.exec_refs                      227540                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                   78360                       # Number of branches executed
system.cpu0.iew.exec_stores                     76158                       # Number of stores executed
system.cpu0.iew.exec_rate                    1.889823                       # Inst execution rate
system.cpu0.iew.wb_sent                        393529                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                       393268                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                   233079                       # num instructions producing a value
system.cpu0.iew.wb_consumers                   235200                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      1.886992                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.990982                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitCommittedInsts        462373                       # The number of committed instructions
system.cpu0.commit.commitSquashedInsts           9639                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts             1041                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples       188581                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     2.451854                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     2.134496                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0        32178     17.06%     17.06% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1        78251     41.49%     58.56% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2         2149      1.14%     59.70% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3          733      0.39%     60.09% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4          648      0.34%     60.43% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5        73572     39.01%     99.44% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6          474      0.25%     99.69% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7          279      0.15%     99.84% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8          297      0.16%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total       188581                       # Number of insts commited each cycle
system.cpu0.commit.count                       462373                       # Number of instructions committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                        225896                       # Number of memory references committed
system.cpu0.commit.loads                       150260                       # Number of loads committed
system.cpu0.commit.membars                         84                       # Number of memory barriers committed
system.cpu0.commit.branches                     77524                       # Number of branches committed
system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                   311682                       # Number of committed integer instructions.
system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events                  297                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                      659135                       # The number of ROB reads
system.cpu0.rob.rob_writes                     946098                       # The number of ROB writes
system.cpu0.timesIdled                            320                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                          17785                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts                     388034                       # Number of Instructions Simulated
system.cpu0.committedInsts_total               388034                       # Number of Instructions Simulated
system.cpu0.cpi                              0.537092                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        0.537092                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              1.861878                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        1.861878                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                  704687                       # number of integer regfile reads
system.cpu0.int_regfile_writes                 317694                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
system.cpu0.misc_regfile_reads                 229306                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
system.cpu0.icache.replacements                   294                       # number of replacements
system.cpu0.icache.tagsinuse               244.310261                       # Cycle average of tags in use
system.cpu0.icache.total_refs                    4819                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                   581                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                  8.294320                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::0           244.310261                       # Average occupied blocks per context
system.cpu0.icache.occ_percent::0            0.477168                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits                  4819                       # number of ReadReq hits
system.cpu0.icache.demand_hits                   4819                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits                  4819                       # number of overall hits
system.cpu0.icache.ReadReq_misses                 702                       # number of ReadReq misses
system.cpu0.icache.demand_misses                  702                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses                 702                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency      27601000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency       27601000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency      27601000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses              5521                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses               5521                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses              5521                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate         0.127151                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate          0.127151                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate         0.127151                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency 39317.663818                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency 39317.663818                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency 39317.663818                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs        15500                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs        15500                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks                       0                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits              120                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits               120                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits              120                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses            582                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses             582                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses            582                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency     21371000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency     21371000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency     21371000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate     0.105416                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate     0.105416                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate     0.105416                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36719.931271                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency 36719.931271                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency 36719.931271                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements                     9                       # number of replacements
system.cpu0.dcache.tagsinuse               139.593674                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                   95831                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs                   174                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                550.752874                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::0           140.420812                       # Average occupied blocks per context
system.cpu0.dcache.occ_blocks::1            -0.827138                       # Average occupied blocks per context
system.cpu0.dcache.occ_percent::0            0.274259                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::1           -0.001616                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits                 76983                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits                75054                       # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits                    23                       # number of SwapReq hits
system.cpu0.dcache.demand_hits                 152037                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits                152037                       # number of overall hits
system.cpu0.dcache.ReadReq_misses                 495                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses                540                       # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses                  19                       # number of SwapReq misses
system.cpu0.dcache.demand_misses                 1035                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses                1035                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency      13943500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency     24690984                       # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency        375000                       # number of SwapReq miss cycles
system.cpu0.dcache.demand_miss_latency       38634484                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency      38634484                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses             77478                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses            75594                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses                42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses             153072                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses            153072                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate         0.006389                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate        0.007143                       # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate         0.452381                       # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate          0.006762                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate         0.006762                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency 28168.686869                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency 45724.044444                       # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency 19736.842105                       # average SwapReq miss latency
system.cpu0.dcache.demand_avg_miss_latency 37328.003865                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency 37328.003865                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs       180500                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs               21                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs  8595.238095                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks                       6                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits              308                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits             369                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits               677                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits              677                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses            187                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses           171                       # number of WriteReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses             19                       # number of SwapReq MSHR misses
system.cpu0.dcache.demand_mshr_misses             358                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses            358                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency      5126500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency      6255000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency       318000                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency     11381500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency     11381500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate     0.002414                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate     0.002262                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate     0.452381                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.demand_mshr_miss_rate     0.002339                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate     0.002339                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27414.438503                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36578.947368                       # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 16736.842105                       # average SwapReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency 31791.899441                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency 31791.899441                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.numCycles                          174065                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.BPredUnit.lookups                   53680                       # Number of BP lookups
system.cpu1.BPredUnit.condPredicted             51050                       # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect              1082                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups                49680                       # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits                   47696                       # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS                     674                       # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles             25860                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                        302062                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                      53680                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches             48370                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                       105407                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                   3162                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles                 31070                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.NoActiveThreadStallCycles         6439                       # Number of stall cycles due to no active thread to fetch from
system.cpu1.fetch.PendingTrapStallCycles          670                       # Number of stall cycles due to pending traps
system.cpu1.fetch.CacheLines                    17358                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                  181                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples            171455                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.761757                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.155300                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                   66048     38.52%     38.52% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                   53266     31.07%     69.59% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                    5206      3.04%     72.63% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                    3414      1.99%     74.62% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                     592      0.35%     74.96% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                   38163     22.26%     97.22% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                    1383      0.81%     98.03% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                     403      0.24%     98.26% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                    2980      1.74%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total              171455                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.308391                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       1.735340                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                   30212                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles                28102                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                   100316                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles                 4382                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                  2004                       # Number of cycles decode is squashing
system.cpu1.decode.DecodedInsts                299336                       # Number of instructions handled by decode
system.cpu1.rename.SquashCycles                  2004                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                   30858                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                  13502                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles         13779                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                    96392                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles                 8481                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts                297385                       # Number of instructions processed by rename
system.cpu1.rename.IQFullEvents                    26                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents                   56                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands             208391                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups               574206                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups          574206                       # Number of integer rename lookups
system.cpu1.rename.CommittedMaps               198747                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                    9644                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts              1073                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts          1204                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                    11164                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads               85765                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores              40966                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads            40880                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores           36423                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                    247992                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded               5619                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                   250090                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued                3                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined           8378                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined         7678                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved           648                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples       171455                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        1.458633                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.309488                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0              63066     36.78%     36.78% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1              20362     11.88%     48.66% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2              40913     23.86%     72.52% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3              42366     24.71%     97.23% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4               3338      1.95%     99.18% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5               1156      0.67%     99.85% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                160      0.09%     99.95% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                 40      0.02%     99.97% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                 54      0.03%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total         171455                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                     12      4.58%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      4.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                    60     22.90%     27.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                  190     72.52%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu               120097     48.02%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.02% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead               89434     35.76%     83.78% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite              40559     16.22%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total                250090                       # Type of FU issued
system.cpu1.iq.rate                          1.436762                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                        262                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.001048                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads            671900                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes           262020                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses       248980                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses                250352                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           36283                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads         1818                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation           31                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores          869                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                  2004                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                   1662                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                   52                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts             295488                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts              312                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts                85765                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts               40966                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts              1034                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                    50                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents            31                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect           608                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect          631                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts                1239                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts               249342                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts                84980                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts              748                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                        41877                       # number of nop insts executed
system.cpu1.iew.exec_refs                      125494                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                   50909                       # Number of branches executed
system.cpu1.iew.exec_stores                     40514                       # Number of stores executed
system.cpu1.iew.exec_rate                    1.432465                       # Inst execution rate
system.cpu1.iew.wb_sent                        249148                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                       248980                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                   142220                       # num instructions producing a value
system.cpu1.iew.wb_consumers                   146685                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      1.430385                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.969561                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitCommittedInsts        285859                       # The number of committed instructions
system.cpu1.commit.commitSquashedInsts           9624                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls           4971                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts             1082                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples       163013                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     1.753596                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     2.061352                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0        61328     37.62%     37.62% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1        49151     30.15%     67.77% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2         5963      3.66%     71.43% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3         5859      3.59%     75.03% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4         1587      0.97%     76.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5        36625     22.47%     98.47% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6          608      0.37%     98.84% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7         1052      0.65%     99.48% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8          840      0.52%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total       163013                       # Number of insts commited each cycle
system.cpu1.commit.count                       285859                       # Number of instructions committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                        124044                       # Number of memory references committed
system.cpu1.commit.loads                        83947                       # Number of loads committed
system.cpu1.commit.membars                       4259                       # Number of memory barriers committed
system.cpu1.commit.branches                     50321                       # Number of branches committed
system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                   196488                       # Number of committed integer instructions.
system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events                  840                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                      457069                       # The number of ROB reads
system.cpu1.rob.rob_writes                     592971                       # The number of ROB writes
system.cpu1.timesIdled                            229                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                           2610                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.committedInsts                     240487                       # Number of Instructions Simulated
system.cpu1.committedInsts_total               240487                       # Number of Instructions Simulated
system.cpu1.cpi                              0.723802                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        0.723802                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              1.381593                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        1.381593                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                  434614                       # number of integer regfile reads
system.cpu1.int_regfile_writes                 202365                       # number of integer regfile writes
system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 127051                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                   646                       # number of misc regfile writes
system.cpu1.icache.replacements                   317                       # number of replacements
system.cpu1.icache.tagsinuse                84.485339                       # Cycle average of tags in use
system.cpu1.icache.total_refs                   16887                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                   427                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                 39.548009                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::0            84.485339                       # Average occupied blocks per context
system.cpu1.icache.occ_percent::0            0.165010                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits                 16887                       # number of ReadReq hits
system.cpu1.icache.demand_hits                  16887                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits                 16887                       # number of overall hits
system.cpu1.icache.ReadReq_misses                 471                       # number of ReadReq misses
system.cpu1.icache.demand_misses                  471                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses                 471                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency       7156000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency        7156000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency       7156000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses             17358                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses              17358                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses             17358                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate         0.027134                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate          0.027134                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate         0.027134                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency 15193.205945                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency 15193.205945                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency 15193.205945                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.writebacks                       0                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits               44                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits                44                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits               44                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses            427                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses             427                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses            427                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency      5329000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency      5329000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency      5329000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate     0.024600                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate     0.024600                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate     0.024600                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12480.093677                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency 12480.093677                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency 12480.093677                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                     2                       # number of replacements
system.cpu1.dcache.tagsinuse                18.326142                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                   46034                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                    29                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs               1587.379310                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::0            24.418432                       # Average occupied blocks per context
system.cpu1.dcache.occ_blocks::1            -6.092290                       # Average occupied blocks per context
system.cpu1.dcache.occ_percent::0            0.047692                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::1           -0.011899                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits                 48212                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits                39908                       # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits                    12                       # number of SwapReq hits
system.cpu1.dcache.demand_hits                  88120                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits                 88120                       # number of overall hits
system.cpu1.dcache.ReadReq_misses                 470                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses                123                       # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses                  54                       # number of SwapReq misses
system.cpu1.dcache.demand_misses                  593                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses                 593                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency       9944500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency      2927000                       # number of WriteReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency       1215000                       # number of SwapReq miss cycles
system.cpu1.dcache.demand_miss_latency       12871500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency      12871500                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses             48682                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses            40031                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses                66                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses              88713                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses             88713                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate         0.009654                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate        0.003073                       # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate         0.818182                       # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate          0.006684                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate         0.006684                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency 21158.510638                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency 23796.747967                       # average WriteReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency        22500                       # average SwapReq miss latency
system.cpu1.dcache.demand_avg_miss_latency 21705.733558                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency 21705.733558                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks                       1                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits              318                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits              18                       # number of WriteReq MSHR hits
system.cpu1.dcache.demand_mshr_hits               336                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits              336                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses            152                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses           105                       # number of WriteReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses             54                       # number of SwapReq MSHR misses
system.cpu1.dcache.demand_mshr_misses             257                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses            257                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency      1992500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency      1603000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency      1053000                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency      3595500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency      3595500                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate     0.003122                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate     0.002623                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate     0.818182                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.demand_mshr_miss_rate     0.002897                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate     0.002897                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13108.552632                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 15266.666667                       # average WriteReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency        19500                       # average SwapReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency 13990.272374                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency 13990.272374                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.numCycles                          173778                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.BPredUnit.lookups                   50805                       # Number of BP lookups
system.cpu2.BPredUnit.condPredicted             48180                       # Number of conditional branches predicted
system.cpu2.BPredUnit.condIncorrect              1153                       # Number of conditional branches incorrect
system.cpu2.BPredUnit.BTBLookups                47027                       # Number of BTB lookups
system.cpu2.BPredUnit.BTBHits                   44960                       # Number of BTB hits
system.cpu2.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.BPredUnit.usedRAS                     640                       # Number of times the RAS was used to get a target.
system.cpu2.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
system.cpu2.fetch.icacheStallCycles             27007                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                        283163                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                      50805                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches             45600                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                        99886                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                   3304                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.BlockedCycles                 32566                       # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.NoActiveThreadStallCycles         6449                       # Number of stall cycles due to no active thread to fetch from
system.cpu2.fetch.PendingTrapStallCycles          778                       # Number of stall cycles due to pending traps
system.cpu2.fetch.CacheLines                    18144                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes                  200                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples            168765                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.677854                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.125811                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                   68879     40.81%     40.81% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                   50491     29.92%     70.73% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                    5634      3.34%     74.07% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                    3757      2.23%     76.30% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                     707      0.42%     76.71% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                   34670     20.54%     97.26% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                    1324      0.78%     98.04% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                     413      0.24%     98.29% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                    2890      1.71%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total              168765                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.292356                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       1.629453                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                   31662                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles                29441                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                    94497                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles                 4642                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                  2074                       # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts                280431                       # Number of instructions handled by decode
system.cpu2.rename.SquashCycles                  2074                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                   32376                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles                  14418                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles         14186                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                    90338                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles                 8924                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts                278200                       # Number of instructions processed by rename
system.cpu2.rename.IQFullEvents                    53                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LSQFullEvents                   43                       # Number of times rename has blocked due to LSQ full
system.cpu2.rename.RenamedOperands             195247                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups               534109                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups          534109                       # Number of integer rename lookups
system.cpu2.rename.CommittedMaps               184829                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                   10418                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts              1050                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts          1186                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                    11541                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads               79019                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores              37409                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads            37644                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores           32854                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                    231381                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded               5925                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                   233568                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued                3                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined           8776                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined         8266                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved           641                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples       168765                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.383984                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.307813                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0              66154     39.20%     39.20% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1              21382     12.67%     51.87% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2              37723     22.35%     74.22% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3              38911     23.06%     97.28% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4               3386      2.01%     99.28% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5                949      0.56%     99.85% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6                160      0.09%     99.94% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7                 42      0.02%     99.97% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8                 58      0.03%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total         168765                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                     19      7.28%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     0      0.00%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      7.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                    52     19.92%     27.20% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite                  190     72.80%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu               113638     48.65%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.65% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead               82927     35.50%     84.16% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite              37003     15.84%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total                233568                       # Type of FU issued
system.cpu2.iq.rate                          1.344060                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                        261                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.001117                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads            636165                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes           246114                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses       232313                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses                233829                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads           32721                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads         1885                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation           32                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores          861                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                  2074                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles                   1817                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles                   62                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts             275982                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts              400                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts                79019                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts               37409                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts               998                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                    54                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents            32                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect           681                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect          621                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts                1302                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts               232725                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts                78144                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts              843                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                        38676                       # number of nop insts executed
system.cpu2.iew.exec_refs                      115111                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                   47758                       # Number of branches executed
system.cpu2.iew.exec_stores                     36967                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.339209                       # Inst execution rate
system.cpu2.iew.wb_sent                        232494                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                       232313                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                   131935                       # num instructions producing a value
system.cpu2.iew.wb_consumers                   136342                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      1.336838                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.967677                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitCommittedInsts        265754                       # The number of committed instructions
system.cpu2.commit.commitSquashedInsts          10224                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls           5284                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts             1153                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples       160243                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.658444                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     2.033027                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0        64923     40.52%     40.52% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1        46026     28.72%     69.24% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2         5970      3.73%     72.96% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3         6149      3.84%     76.80% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4         1628      1.02%     77.82% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5        33154     20.69%     98.51% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6          514      0.32%     98.83% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7         1057      0.66%     99.49% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8          822      0.51%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total       160243                       # Number of insts commited each cycle
system.cpu2.commit.count                       265754                       # Number of instructions committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                        113682                       # Number of memory references committed
system.cpu2.commit.loads                        77134                       # Number of loads committed
system.cpu2.commit.membars                       4565                       # Number of memory barriers committed
system.cpu2.commit.branches                     47078                       # Number of branches committed
system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                   182876                       # Number of committed integer instructions.
system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
system.cpu2.commit.bw_lim_events                  822                       # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads                      434812                       # The number of ROB reads
system.cpu2.rob.rob_writes                     554033                       # The number of ROB writes
system.cpu2.timesIdled                            231                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                           5013                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.committedInsts                     223326                       # Number of Instructions Simulated
system.cpu2.committedInsts_total               223326                       # Number of Instructions Simulated
system.cpu2.cpi                              0.778136                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        0.778136                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              1.285122                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        1.285122                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads                  403849                       # number of integer regfile reads
system.cpu2.int_regfile_writes                 188623                       # number of integer regfile writes
system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu2.misc_regfile_reads                 116687                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                   646                       # number of misc regfile writes
system.cpu2.icache.replacements                   323                       # number of replacements
system.cpu2.icache.tagsinuse                85.152335                       # Cycle average of tags in use
system.cpu2.icache.total_refs                   17658                       # Total number of references to valid blocks.
system.cpu2.icache.sampled_refs                   429                       # Sample count of references to valid blocks.
system.cpu2.icache.avg_refs                 41.160839                       # Average number of references to valid blocks.
system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu2.icache.occ_blocks::0            85.152335                       # Average occupied blocks per context
system.cpu2.icache.occ_percent::0            0.166313                       # Average percentage of cache occupancy
system.cpu2.icache.ReadReq_hits                 17658                       # number of ReadReq hits
system.cpu2.icache.demand_hits                  17658                       # number of demand (read+write) hits
system.cpu2.icache.overall_hits                 17658                       # number of overall hits
system.cpu2.icache.ReadReq_misses                 486                       # number of ReadReq misses
system.cpu2.icache.demand_misses                  486                       # number of demand (read+write) misses
system.cpu2.icache.overall_misses                 486                       # number of overall misses
system.cpu2.icache.ReadReq_miss_latency      10409000                       # number of ReadReq miss cycles
system.cpu2.icache.demand_miss_latency       10409000                       # number of demand (read+write) miss cycles
system.cpu2.icache.overall_miss_latency      10409000                       # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses             18144                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses              18144                       # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses             18144                       # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate         0.026786                       # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate          0.026786                       # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate         0.026786                       # miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_miss_latency 21417.695473                       # average ReadReq miss latency
system.cpu2.icache.demand_avg_miss_latency 21417.695473                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency 21417.695473                       # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs        33000                       # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs        33000                       # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
system.cpu2.icache.writebacks                       0                       # number of writebacks
system.cpu2.icache.ReadReq_mshr_hits               57                       # number of ReadReq MSHR hits
system.cpu2.icache.demand_mshr_hits                57                       # number of demand (read+write) MSHR hits
system.cpu2.icache.overall_mshr_hits               57                       # number of overall MSHR hits
system.cpu2.icache.ReadReq_mshr_misses            429                       # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses             429                       # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses            429                       # number of overall MSHR misses
system.cpu2.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu2.icache.ReadReq_mshr_miss_latency      7965500                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency      7965500                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency      7965500                       # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu2.icache.ReadReq_mshr_miss_rate     0.023644                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate     0.023644                       # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate     0.023644                       # mshr miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18567.599068                       # average ReadReq mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency 18567.599068                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency 18567.599068                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu2.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu2.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.dcache.replacements                     2                       # number of replacements
system.cpu2.dcache.tagsinuse                18.333268                       # Cycle average of tags in use
system.cpu2.dcache.total_refs                   42495                       # Total number of references to valid blocks.
system.cpu2.dcache.sampled_refs                    31                       # Sample count of references to valid blocks.
system.cpu2.dcache.avg_refs               1370.806452                       # Average number of references to valid blocks.
system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu2.dcache.occ_blocks::0            26.478684                       # Average occupied blocks per context
system.cpu2.dcache.occ_blocks::1            -8.145416                       # Average occupied blocks per context
system.cpu2.dcache.occ_percent::0            0.051716                       # Average percentage of cache occupancy
system.cpu2.dcache.occ_percent::1           -0.015909                       # Average percentage of cache occupancy
system.cpu2.dcache.ReadReq_hits                 44951                       # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits                36350                       # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits                    12                       # number of SwapReq hits
system.cpu2.dcache.demand_hits                  81301                       # number of demand (read+write) hits
system.cpu2.dcache.overall_hits                 81301                       # number of overall hits
system.cpu2.dcache.ReadReq_misses                 454                       # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses                125                       # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses                  61                       # number of SwapReq misses
system.cpu2.dcache.demand_misses                  579                       # number of demand (read+write) misses
system.cpu2.dcache.overall_misses                 579                       # number of overall misses
system.cpu2.dcache.ReadReq_miss_latency      10292500                       # number of ReadReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency      2895500                       # number of WriteReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency       1389500                       # number of SwapReq miss cycles
system.cpu2.dcache.demand_miss_latency       13188000                       # number of demand (read+write) miss cycles
system.cpu2.dcache.overall_miss_latency      13188000                       # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses             45405                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses            36475                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses                73                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses              81880                       # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses             81880                       # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate         0.009999                       # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate        0.003427                       # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate         0.835616                       # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate          0.007071                       # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate         0.007071                       # miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_miss_latency 22670.704846                       # average ReadReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency        23164                       # average WriteReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency 22778.688525                       # average SwapReq miss latency
system.cpu2.dcache.demand_avg_miss_latency 22777.202073                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency 22777.202073                       # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu2.dcache.writebacks                       1                       # number of writebacks
system.cpu2.dcache.ReadReq_mshr_hits              289                       # number of ReadReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits              18                       # number of WriteReq MSHR hits
system.cpu2.dcache.demand_mshr_hits               307                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.overall_mshr_hits              307                       # number of overall MSHR hits
system.cpu2.dcache.ReadReq_mshr_misses            165                       # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses           107                       # number of WriteReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses             61                       # number of SwapReq MSHR misses
system.cpu2.dcache.demand_mshr_misses             272                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses            272                       # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu2.dcache.ReadReq_mshr_miss_latency      2342500                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency      1563000                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency      1206500                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency      3905500                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency      3905500                       # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate     0.003634                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate     0.002934                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate     0.835616                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.demand_mshr_miss_rate     0.003322                       # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate     0.003322                       # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 14196.969697                       # average ReadReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 14607.476636                       # average WriteReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 19778.688525                       # average SwapReq mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency 14358.455882                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency 14358.455882                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu2.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu2.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.numCycles                          173512                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.BPredUnit.lookups                   40530                       # Number of BP lookups
system.cpu3.BPredUnit.condPredicted             37937                       # Number of conditional branches predicted
system.cpu3.BPredUnit.condIncorrect              1057                       # Number of conditional branches incorrect
system.cpu3.BPredUnit.BTBLookups                36753                       # Number of BTB lookups
system.cpu3.BPredUnit.BTBHits                   34800                       # Number of BTB hits
system.cpu3.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.BPredUnit.usedRAS                     627                       # Number of times the RAS was used to get a target.
system.cpu3.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
system.cpu3.fetch.icacheStallCycles             33125                       # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts                        215867                       # Number of instructions fetch has processed
system.cpu3.fetch.Branches                      40530                       # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches             35427                       # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles                        83007                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles                   3046                       # Number of cycles fetch has spent squashing
system.cpu3.fetch.BlockedCycles                 45401                       # Number of cycles fetch has spent blocked
system.cpu3.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.NoActiveThreadStallCycles         6445                       # Number of stall cycles due to no active thread to fetch from
system.cpu3.fetch.PendingTrapStallCycles          706                       # Number of stall cycles due to pending traps
system.cpu3.fetch.CacheLines                    24871                       # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes                  171                       # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.rateDist::samples            170604                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean             1.265310                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev            1.931210                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0                   87597     51.35%     51.35% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1                   43833     25.69%     77.04% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2                    8987      5.27%     82.31% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3                    3510      2.06%     84.36% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4                     653      0.38%     84.75% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5                   21422     12.56%     97.30% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6                    1319      0.77%     98.08% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7                     370      0.22%     98.29% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8                    2913      1.71%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total              170604                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate                 0.233586                       # Number of branch fetches per cycle
system.cpu3.fetch.rate                       1.244104                       # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles                   41023                       # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles                38920                       # Number of cycles decode is blocked
system.cpu3.decode.RunCycles                    74503                       # Number of cycles decode is running
system.cpu3.decode.UnblockCycles                 7798                       # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles                  1915                       # Number of cycles decode is squashing
system.cpu3.decode.DecodedInsts                213126                       # Number of instructions handled by decode
system.cpu3.rename.SquashCycles                  1915                       # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles                   41660                       # Number of cycles rename is idle
system.cpu3.rename.BlockCycles                  23650                       # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles         14461                       # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles                    67213                       # Number of cycles rename is running
system.cpu3.rename.UnblockCycles                15260                       # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts                211303                       # Number of instructions processed by rename
system.cpu3.rename.IQFullEvents                    13                       # Number of times rename has blocked due to IQ full
system.cpu3.rename.LSQFullEvents                   40                       # Number of times rename has blocked due to LSQ full
system.cpu3.rename.RenamedOperands             145000                       # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups               387654                       # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups          387654                       # Number of integer rename lookups
system.cpu3.rename.CommittedMaps               135623                       # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps                    9377                       # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts              1053                       # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts          1194                       # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts                    17810                       # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads               55847                       # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores              24229                       # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads            27736                       # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores           19680                       # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded                    171446                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded               9173                       # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued                   177208                       # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued                3                       # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined           8093                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined         7434                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved           618                       # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples       170604                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean        1.038710                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev       1.248224                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0              84759     49.68%     49.68% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1              31065     18.21%     67.89% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2              24373     14.29%     82.18% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3              25865     15.16%     97.34% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4               3284      1.92%     99.26% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5               1031      0.60%     99.87% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6                132      0.08%     99.94% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7                 41      0.02%     99.97% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8                 54      0.03%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total         170604                       # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu                     11      4.47%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult                     0      0.00%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv                      0      0.00%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult                   0      0.00%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult                    0      0.00%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift                   0      0.00%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      4.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead                    45     18.29%     22.76% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite                  190     77.24%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu                90240     50.92%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     50.92% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead               63111     35.61%     86.54% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite              23857     13.46%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total                177208                       # Type of FU issued
system.cpu3.iq.rate                          1.021301                       # Inst issue rate
system.cpu3.iq.fu_busy_cnt                        246                       # FU busy when requested
system.cpu3.iq.fu_busy_rate                  0.001388                       # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads            525269                       # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes           188741                       # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses       176086                       # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses                177454                       # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads           19589                       # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads         1676                       # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation           29                       # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores          799                       # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles                  1915                       # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles                   1524                       # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles                   35                       # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts             209347                       # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts              383                       # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts                55847                       # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts               24229                       # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts               987                       # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents                    33                       # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents            29                       # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect           624                       # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect          548                       # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts                1172                       # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts               176425                       # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts                55052                       # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts              783                       # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
system.cpu3.iew.exec_nop                        28728                       # number of nop insts executed
system.cpu3.iew.exec_refs                       78879                       # number of memory reference insts executed
system.cpu3.iew.exec_branches                   37783                       # Number of branches executed
system.cpu3.iew.exec_stores                     23827                       # Number of stores executed
system.cpu3.iew.exec_rate                    1.016788                       # Inst execution rate
system.cpu3.iew.wb_sent                        176246                       # cumulative count of insts sent to commit
system.cpu3.iew.wb_count                       176086                       # cumulative count of insts written-back
system.cpu3.iew.wb_producers                    95644                       # num instructions producing a value
system.cpu3.iew.wb_consumers                    99967                       # num instructions consuming a value
system.cpu3.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu3.iew.wb_rate                      1.014835                       # insts written-back per cycle
system.cpu3.iew.wb_fanout                    0.956756                       # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu3.commit.commitCommittedInsts        200126                       # The number of committed instructions
system.cpu3.commit.commitSquashedInsts           9211                       # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls           8555                       # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts             1057                       # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples       162245                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean     1.233480                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev     1.839252                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0        86736     53.46%     53.46% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1        36031     22.21%     75.67% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2         6002      3.70%     79.37% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3         9421      5.81%     85.17% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4         1631      1.01%     86.18% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5        19977     12.31%     98.49% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6          548      0.34%     98.83% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7         1061      0.65%     99.48% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8          838      0.52%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total       162245                       # Number of insts commited each cycle
system.cpu3.commit.count                       200126                       # Number of instructions committed
system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu3.commit.refs                         77601                       # Number of memory references committed
system.cpu3.commit.loads                        54171                       # Number of loads committed
system.cpu3.commit.membars                       7839                       # Number of memory barriers committed
system.cpu3.commit.branches                     37226                       # Number of branches committed
system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu3.commit.int_insts                   136949                       # Number of committed integer instructions.
system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
system.cpu3.commit.bw_lim_events                  838                       # number cycles where commit BW limit reached
system.cpu3.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu3.rob.rob_reads                      370157                       # The number of ROB reads
system.cpu3.rob.rob_writes                     420591                       # The number of ROB writes
system.cpu3.timesIdled                            233                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles                           2908                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.committedInsts                     164273                       # Number of Instructions Simulated
system.cpu3.committedInsts_total               164273                       # Number of Instructions Simulated
system.cpu3.cpi                              1.056242                       # CPI: Cycles Per Instruction
system.cpu3.cpi_total                        1.056242                       # CPI: Total CPI of All Threads
system.cpu3.ipc                              0.946753                       # IPC: Instructions Per Cycle
system.cpu3.ipc_total                        0.946753                       # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads                  294835                       # number of integer regfile reads
system.cpu3.int_regfile_writes                 139001                       # number of integer regfile writes
system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu3.misc_regfile_reads                  80433                       # number of misc regfile reads
system.cpu3.misc_regfile_writes                   646                       # number of misc regfile writes
system.cpu3.icache.replacements                   318                       # number of replacements
system.cpu3.icache.tagsinuse                80.013522                       # Cycle average of tags in use
system.cpu3.icache.total_refs                   24405                       # Total number of references to valid blocks.
system.cpu3.icache.sampled_refs                   426                       # Sample count of references to valid blocks.
system.cpu3.icache.avg_refs                 57.288732                       # Average number of references to valid blocks.
system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu3.icache.occ_blocks::0            80.013522                       # Average occupied blocks per context
system.cpu3.icache.occ_percent::0            0.156276                       # Average percentage of cache occupancy
system.cpu3.icache.ReadReq_hits                 24405                       # number of ReadReq hits
system.cpu3.icache.demand_hits                  24405                       # number of demand (read+write) hits
system.cpu3.icache.overall_hits                 24405                       # number of overall hits
system.cpu3.icache.ReadReq_misses                 466                       # number of ReadReq misses
system.cpu3.icache.demand_misses                  466                       # number of demand (read+write) misses
system.cpu3.icache.overall_misses                 466                       # number of overall misses
system.cpu3.icache.ReadReq_miss_latency       6656500                       # number of ReadReq miss cycles
system.cpu3.icache.demand_miss_latency        6656500                       # number of demand (read+write) miss cycles
system.cpu3.icache.overall_miss_latency       6656500                       # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses             24871                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses              24871                       # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses             24871                       # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate         0.018737                       # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate          0.018737                       # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate         0.018737                       # miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_miss_latency 14284.334764                       # average ReadReq miss latency
system.cpu3.icache.demand_avg_miss_latency 14284.334764                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency 14284.334764                       # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
system.cpu3.icache.writebacks                       0                       # number of writebacks
system.cpu3.icache.ReadReq_mshr_hits               40                       # number of ReadReq MSHR hits
system.cpu3.icache.demand_mshr_hits                40                       # number of demand (read+write) MSHR hits
system.cpu3.icache.overall_mshr_hits               40                       # number of overall MSHR hits
system.cpu3.icache.ReadReq_mshr_misses            426                       # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses             426                       # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses            426                       # number of overall MSHR misses
system.cpu3.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu3.icache.ReadReq_mshr_miss_latency      4959000                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency      4959000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency      4959000                       # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu3.icache.ReadReq_mshr_miss_rate     0.017128                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate     0.017128                       # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate     0.017128                       # mshr miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11640.845070                       # average ReadReq mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency 11640.845070                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency 11640.845070                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu3.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu3.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.dcache.replacements                     2                       # number of replacements
system.cpu3.dcache.tagsinuse                15.701328                       # Cycle average of tags in use
system.cpu3.dcache.total_refs                   29297                       # Total number of references to valid blocks.
system.cpu3.dcache.sampled_refs                    29                       # Sample count of references to valid blocks.
system.cpu3.dcache.avg_refs               1010.241379                       # Average number of references to valid blocks.
system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu3.dcache.occ_blocks::0            23.466885                       # Average occupied blocks per context
system.cpu3.dcache.occ_blocks::1            -7.765557                       # Average occupied blocks per context
system.cpu3.dcache.occ_percent::0            0.045834                       # Average percentage of cache occupancy
system.cpu3.dcache.occ_percent::1           -0.015167                       # Average percentage of cache occupancy
system.cpu3.dcache.ReadReq_hits                 35023                       # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits                23239                       # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits                    16                       # number of SwapReq hits
system.cpu3.dcache.demand_hits                  58262                       # number of demand (read+write) hits
system.cpu3.dcache.overall_hits                 58262                       # number of overall hits
system.cpu3.dcache.ReadReq_misses                 421                       # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses                121                       # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses                  54                       # number of SwapReq misses
system.cpu3.dcache.demand_misses                  542                       # number of demand (read+write) misses
system.cpu3.dcache.overall_misses                 542                       # number of overall misses
system.cpu3.dcache.ReadReq_miss_latency       8723500                       # number of ReadReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency      2943500                       # number of WriteReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency       1375000                       # number of SwapReq miss cycles
system.cpu3.dcache.demand_miss_latency       11667000                       # number of demand (read+write) miss cycles
system.cpu3.dcache.overall_miss_latency      11667000                       # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses             35444                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses            23360                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses                70                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses              58804                       # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses             58804                       # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate         0.011878                       # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate        0.005180                       # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate         0.771429                       # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate          0.009217                       # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate         0.009217                       # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency 20720.902613                       # average ReadReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency 24326.446281                       # average WriteReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency 25462.962963                       # average SwapReq miss latency
system.cpu3.dcache.demand_avg_miss_latency 21525.830258                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency 21525.830258                       # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu3.dcache.writebacks                       1                       # number of writebacks
system.cpu3.dcache.ReadReq_mshr_hits              256                       # number of ReadReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits              19                       # number of WriteReq MSHR hits
system.cpu3.dcache.demand_mshr_hits               275                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.overall_mshr_hits              275                       # number of overall MSHR hits
system.cpu3.dcache.ReadReq_mshr_misses            165                       # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses           102                       # number of WriteReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses             54                       # number of SwapReq MSHR misses
system.cpu3.dcache.demand_mshr_misses             267                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses            267                       # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu3.dcache.ReadReq_mshr_miss_latency      2157000                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency      1669000                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency      1213000                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency      3826000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency      3826000                       # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate     0.004655                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate     0.004366                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate     0.771429                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.demand_mshr_miss_rate     0.004541                       # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate     0.004541                       # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 13072.727273                       # average ReadReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 16362.745098                       # average WriteReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 22462.962963                       # average SwapReq mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency 14329.588015                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency 14329.588015                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu3.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu3.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.l2c.replacements                             0                       # number of replacements
system.l2c.tagsinuse                       428.144160                       # Cycle average of tags in use
system.l2c.total_refs                            1448                       # Total number of references to valid blocks.
system.l2c.sampled_refs                           527                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          2.747628                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::0                   347.119372                       # Average occupied blocks per context
system.l2c.occ_blocks::1                    10.560700                       # Average occupied blocks per context
system.l2c.occ_blocks::2                    63.080596                       # Average occupied blocks per context
system.l2c.occ_blocks::3                     2.422702                       # Average occupied blocks per context
system.l2c.occ_blocks::4                     4.960789                       # Average occupied blocks per context
system.l2c.occ_percent::0                    0.005297                       # Average percentage of cache occupancy
system.l2c.occ_percent::1                    0.000161                       # Average percentage of cache occupancy
system.l2c.occ_percent::2                    0.000963                       # Average percentage of cache occupancy
system.l2c.occ_percent::3                    0.000037                       # Average percentage of cache occupancy
system.l2c.occ_percent::4                    0.000076                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::0                        233                       # number of ReadReq hits
system.l2c.ReadReq_hits::1                        425                       # number of ReadReq hits
system.l2c.ReadReq_hits::2                        360                       # number of ReadReq hits
system.l2c.ReadReq_hits::3                        433                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                   1451                       # number of ReadReq hits
system.l2c.Writeback_hits::0                        9                       # number of Writeback hits
system.l2c.Writeback_hits::total                    9                       # number of Writeback hits
system.l2c.UpgradeReq_hits::0                       3                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                   3                       # number of UpgradeReq hits
system.l2c.demand_hits::0                         233                       # number of demand (read+write) hits
system.l2c.demand_hits::1                         425                       # number of demand (read+write) hits
system.l2c.demand_hits::2                         360                       # number of demand (read+write) hits
system.l2c.demand_hits::3                         433                       # number of demand (read+write) hits
system.l2c.demand_hits::total                    1451                       # number of demand (read+write) hits
system.l2c.overall_hits::0                        233                       # number of overall hits
system.l2c.overall_hits::1                        425                       # number of overall hits
system.l2c.overall_hits::2                        360                       # number of overall hits
system.l2c.overall_hits::3                        433                       # number of overall hits
system.l2c.overall_hits::total                   1451                       # number of overall hits
system.l2c.ReadReq_misses::0                      429                       # number of ReadReq misses
system.l2c.ReadReq_misses::1                       15                       # number of ReadReq misses
system.l2c.ReadReq_misses::2                       83                       # number of ReadReq misses
system.l2c.ReadReq_misses::3                        6                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                  533                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::0                    21                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::1                    23                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::2                    19                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::3                    24                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total                87                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::0                     94                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::1                     12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::2                     13                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::3                     12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
system.l2c.demand_misses::0                       523                       # number of demand (read+write) misses
system.l2c.demand_misses::1                        27                       # number of demand (read+write) misses
system.l2c.demand_misses::2                        96                       # number of demand (read+write) misses
system.l2c.demand_misses::3                        18                       # number of demand (read+write) misses
system.l2c.demand_misses::total                   664                       # number of demand (read+write) misses
system.l2c.overall_misses::0                      523                       # number of overall misses
system.l2c.overall_misses::1                       27                       # number of overall misses
system.l2c.overall_misses::2                       96                       # number of overall misses
system.l2c.overall_misses::3                       18                       # number of overall misses
system.l2c.overall_misses::total                  664                       # number of overall misses
system.l2c.ReadReq_miss_latency              27698500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency             157500                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency             6878000                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency               34576500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency              34576500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::0                    662                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1                    440                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::2                    443                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::3                    439                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total               1984                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::0                    9                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total                9                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::0                  24                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::1                  23                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::2                  19                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::3                  24                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              90                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::0                   94                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::1                   12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::2                   13                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::3                   12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::0                     756                       # number of demand (read+write) accesses
system.l2c.demand_accesses::1                     452                       # number of demand (read+write) accesses
system.l2c.demand_accesses::2                     456                       # number of demand (read+write) accesses
system.l2c.demand_accesses::3                     451                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total                2115                       # number of demand (read+write) accesses
system.l2c.overall_accesses::0                    756                       # number of overall (read+write) accesses
system.l2c.overall_accesses::1                    452                       # number of overall (read+write) accesses
system.l2c.overall_accesses::2                    456                       # number of overall (read+write) accesses
system.l2c.overall_accesses::3                    451                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total               2115                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::0              0.648036                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1              0.034091                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::2              0.187359                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::3              0.013667                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.883154                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::0           0.875000                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::1                  1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::2                  1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::3                  1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       3.875000                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::0                   1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::1                   1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::2                   1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::3                   1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total               4                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::0               0.691799                       # miss rate for demand accesses
system.l2c.demand_miss_rate::1               0.059735                       # miss rate for demand accesses
system.l2c.demand_miss_rate::2               0.210526                       # miss rate for demand accesses
system.l2c.demand_miss_rate::3               0.039911                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           1.001971                       # miss rate for demand accesses
system.l2c.overall_miss_rate::0              0.691799                       # miss rate for overall accesses
system.l2c.overall_miss_rate::1              0.059735                       # miss rate for overall accesses
system.l2c.overall_miss_rate::2              0.210526                       # miss rate for overall accesses
system.l2c.overall_miss_rate::3              0.039911                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          1.001971                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::0   64565.268065                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1   1846566.666667                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::2   333716.867470                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::3   4616416.666667                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 6861265.468868                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::0         7500                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1  6847.826087                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::2  8289.473684                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::3  6562.500000                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 29199.799771                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::0 73170.212766                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1 573166.666667                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::2 529076.923077                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::3 573166.666667                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 1748580.469176                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::0    66111.854685                       # average overall miss latency
system.l2c.demand_avg_miss_latency::1    1280611.111111                       # average overall miss latency
system.l2c.demand_avg_miss_latency::2    360171.875000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::3    1920916.666667                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 3627811.507462                       # average overall miss latency
system.l2c.overall_avg_miss_latency::0   66111.854685                       # average overall miss latency
system.l2c.overall_avg_miss_latency::1   1280611.111111                       # average overall miss latency
system.l2c.overall_avg_miss_latency::2   360171.875000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::3   1920916.666667                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 3627811.507462                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks                               0                       # number of writebacks
system.l2c.ReadReq_mshr_hits                        8                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits                         8                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits                        8                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses                    525                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses                  87                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses                  131                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses                     656                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses                    656                       # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency         20993500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency       3480000                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency        5279000                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency          26272500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency         26272500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::0         0.793051                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1         1.193182                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::2         1.185102                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::3         1.195900                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     4.367235                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::0      3.625000                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1      3.782609                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::2      4.578947                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::3      3.625000                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total    15.611556                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::0       1.393617                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1      10.916667                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::2      10.076923                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::3      10.916667                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total    33.303873                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::0          0.867725                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1          1.451327                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::2          1.438596                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::3          1.454545                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      5.212194                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::0         0.867725                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1         1.451327                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::2         1.438596                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::3         1.454545                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     5.212194                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency 39987.619048                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40297.709924                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency  40049.542683                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency 40049.542683                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------