path: root/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

---------- Begin Simulation Statistics ----------
host_inst_rate                                 225525                       # Simulator instruction rate (inst/s)
host_mem_usage                                 214280                       # Number of bytes of host memory used
host_seconds                                     5.12                       # Real time elapsed on the host
host_tick_rate                               22978978                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                     1153797                       # Number of instructions simulated
sim_seconds                                  0.000118                       # Number of seconds simulated
sim_ticks                                   117567000                       # Number of ticks simulated
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.BTBHits                   89355                       # Number of BTB hits
system.cpu0.BPredUnit.BTBLookups                91985                       # Number of BTB lookups
system.cpu0.BPredUnit.RASInCorrect                  0                       # Number of incorrect RAS predictions.
system.cpu0.BPredUnit.condIncorrect              1075                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.condPredicted             92438                       # Number of conditional branches predicted
system.cpu0.BPredUnit.lookups                   92438                       # Number of BP lookups
system.cpu0.BPredUnit.usedRAS                       0                       # Number of times the RAS was used to get a target.
system.cpu0.commit.COM:branches                 89649                       # Number of branches committed
system.cpu0.commit.COM:bw_lim_events              218                       # number cycles where commit BW limit reached
system.cpu0.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
system.cpu0.commit.COM:committed_per_cycle::samples       214956                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::mean     2.489454                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::stdev     2.121443                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::0        33666     15.66%     15.66% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::1        90734     42.21%     57.87% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::2         2490      1.16%     59.03% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::3          739      0.34%     59.37% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::4          734      0.34%     59.72% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::5        85813     39.92%     99.64% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::6          487      0.23%     99.86% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::7           75      0.03%     99.90% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::8          218      0.10%    100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::total       214956                       # Number of insts commited each cycle
system.cpu0.commit.COM:count                   535123                       # Number of instructions committed
system.cpu0.commit.COM:loads                   174510                       # Number of loads committed
system.cpu0.commit.COM:membars                     84                       # Number of memory barriers committed
system.cpu0.commit.COM:refs                    262271                       # Number of memory references committed
system.cpu0.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
system.cpu0.commit.branchMispredicts             1075                       # The number of times a branch was mispredicted
system.cpu0.commit.commitCommittedInsts        535123                       # The number of committed instructions
system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.commitSquashedInsts           9238                       # The number of squashed insts skipped by commit
system.cpu0.committedInsts                     448659                       # Number of Instructions Simulated
system.cpu0.committedInsts_total               448659                       # Number of Instructions Simulated
system.cpu0.cpi                              0.524084                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        0.524084                       # CPI: Total CPI of All Threads
system.cpu0.dcache.ReadReq_accesses             89545                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_avg_miss_latency 27580.808081                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27913.043478                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_hits                 89050                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_miss_latency      13652500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_rate         0.005528                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_misses                 495                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_mshr_hits              311                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_miss_latency      5136000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate     0.002055                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_misses            184                       # number of ReadReq MSHR misses
system.cpu0.dcache.SwapReq_accesses                42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_avg_miss_latency 16596.153846                       # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 13596.153846                       # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_hits                    16                       # number of SwapReq hits
system.cpu0.dcache.SwapReq_miss_latency        431500                       # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_rate         0.619048                       # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_misses                  26                       # number of SwapReq misses
system.cpu0.dcache.SwapReq_mshr_miss_latency       353500                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_rate     0.619048                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_misses             26                       # number of SwapReq MSHR misses
system.cpu0.dcache.WriteReq_accesses            87719                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_avg_miss_latency 46114.070501                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 37094.827586                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_hits                87180                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_miss_latency     24855484                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_rate        0.006145                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_misses                539                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_mshr_hits             365                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_miss_latency      6454500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_rate     0.001984                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_misses           174                       # number of WriteReq MSHR misses
system.cpu0.dcache.avg_blocked_cycles::no_mshrs  8595.238095                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_refs                639.867816                       # Average number of references to valid blocks.
system.cpu0.dcache.blocked::no_mshrs               21                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_mshrs       180500                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.demand_accesses             177264                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_avg_miss_latency 37241.764023                       # average overall miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency 32375.698324                       # average overall mshr miss latency
system.cpu0.dcache.demand_hits                 176230                       # number of demand (read+write) hits
system.cpu0.dcache.demand_miss_latency       38507984                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_rate          0.005833                       # miss rate for demand accesses
system.cpu0.dcache.demand_misses                 1034                       # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits               676                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_miss_latency     11590500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_rate     0.002020                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_misses             358                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.occ_%::0                  0.276057                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_%::1                 -0.002702                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_blocks::0           141.341435                       # Average occupied blocks per context
system.cpu0.dcache.occ_blocks::1            -1.383203                       # Average occupied blocks per context
system.cpu0.dcache.overall_accesses            177264                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_avg_miss_latency 37241.764023                       # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency 32375.698324                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_hits                176230                       # number of overall hits
system.cpu0.dcache.overall_miss_latency      38507984                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_rate         0.005833                       # miss rate for overall accesses
system.cpu0.dcache.overall_misses                1034                       # number of overall misses
system.cpu0.dcache.overall_mshr_hits              676                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_miss_latency     11590500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_rate     0.002020                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_misses            358                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.replacements                     9                       # number of replacements
system.cpu0.dcache.sampled_refs                   174                       # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.dcache.tagsinuse               139.958233                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                  111337                       # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.writebacks                       6                       # number of writebacks
system.cpu0.decode.DECODE:BlockedCycles         13605                       # Number of cycles decode is blocked
system.cpu0.decode.DECODE:DecodedInsts         549348                       # Number of instructions handled by decode
system.cpu0.decode.DECODE:IdleCycles            19922                       # Number of cycles decode is idle
system.cpu0.decode.DECODE:RunCycles            181227                       # Number of cycles decode is running
system.cpu0.decode.DECODE:SquashCycles           2012                       # Number of cycles decode is squashing
system.cpu0.decode.DECODE:UnblockCycles           202                       # Number of cycles decode is unblocking
system.cpu0.fetch.Branches                      92438                       # Number of branches that fetch encountered
system.cpu0.fetch.CacheLines                     5211                       # Number of cache lines fetched
system.cpu0.fetch.Cycles                       186910                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.IcacheSquashes                  478                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.Insts                        550298                       # Number of instructions fetch has processed
system.cpu0.fetch.SquashCycles                   1215                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.branchRate                 0.393127                       # Number of branch fetches per cycle
system.cpu0.fetch.icacheStallCycles              5211                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.predictedBranches             89355                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.rate                       2.340349                       # Number of inst fetches per cycle
system.cpu0.fetch.rateDist::samples            216968                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             2.536310                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.185886                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                   35310     16.27%     16.27% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                   90281     41.61%     57.88% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                     487      0.22%     58.11% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                     792      0.37%     58.47% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                     586      0.27%     58.74% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                   86643     39.93%     98.68% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                     826      0.38%     99.06% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                     192      0.09%     99.15% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                    1851      0.85%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total              216968                       # Number of instructions fetched each cycle (Total)
system.cpu0.icache.ReadReq_accesses              5211                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_avg_miss_latency 39190.412783                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency 37010.673235                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_hits                  4460                       # number of ReadReq hits
system.cpu0.icache.ReadReq_miss_latency      29432000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_rate         0.144118                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_misses                 751                       # number of ReadReq misses
system.cpu0.icache.ReadReq_mshr_hits              142                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_miss_latency     22539500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate     0.116868                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_misses            609                       # number of ReadReq MSHR misses
system.cpu0.icache.avg_blocked_cycles::no_mshrs        11000                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu0.icache.avg_refs                  7.335526                       # Average number of references to valid blocks.
system.cpu0.icache.blocked::no_mshrs                2                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_mshrs        22000                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.demand_accesses               5211                       # number of demand (read+write) accesses
system.cpu0.icache.demand_avg_miss_latency 39190.412783                       # average overall miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency 37010.673235                       # average overall mshr miss latency
system.cpu0.icache.demand_hits                   4460                       # number of demand (read+write) hits
system.cpu0.icache.demand_miss_latency       29432000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_rate          0.144118                       # miss rate for demand accesses
system.cpu0.icache.demand_misses                  751                       # number of demand (read+write) misses
system.cpu0.icache.demand_mshr_hits               142                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_miss_latency     22539500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_rate     0.116868                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_misses             609                       # number of demand (read+write) MSHR misses
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.occ_%::0                  0.503078                       # Average percentage of cache occupancy
system.cpu0.icache.occ_blocks::0           257.575944                       # Average occupied blocks per context
system.cpu0.icache.overall_accesses              5211                       # number of overall (read+write) accesses
system.cpu0.icache.overall_avg_miss_latency 39190.412783                       # average overall miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency 37010.673235                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_hits                  4460                       # number of overall hits
system.cpu0.icache.overall_miss_latency      29432000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_rate         0.144118                       # miss rate for overall accesses
system.cpu0.icache.overall_misses                 751                       # number of overall misses
system.cpu0.icache.overall_mshr_hits              142                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_miss_latency     22539500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_rate     0.116868                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_misses            609                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.icache.replacements                   307                       # number of replacements
system.cpu0.icache.sampled_refs                   608                       # Sample count of references to valid blocks.
system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.icache.tagsinuse               257.575944                       # Cycle average of tags in use
system.cpu0.icache.total_refs                    4460                       # Total number of references to valid blocks.
system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.writebacks                       0                       # number of writebacks
system.cpu0.idleCycles                          18167                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.iew.EXEC:branches                   90443                       # Number of branches executed
system.cpu0.iew.EXEC:nop                        86837                       # number of nop insts executed
system.cpu0.iew.EXEC:rate                    1.932175                       # Inst execution rate
system.cpu0.iew.EXEC:refs                      263768                       # number of memory reference insts executed
system.cpu0.iew.EXEC:stores                     88187                       # Number of stores executed
system.cpu0.iew.EXEC:swp                            0                       # number of swp insts executed
system.cpu0.iew.WB:consumers                   271302                       # num instructions consuming a value
system.cpu0.iew.WB:count                       453750                       # cumulative count of insts written-back
system.cpu0.iew.WB:fanout                    0.992930                       # average fanout of values written-back
system.cpu0.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.iew.WB:producers                   269384                       # num instructions producing a value
system.cpu0.iew.WB:rate                      1.929742                       # insts written-back per cycle
system.cpu0.iew.WB:sent                        453963                       # cumulative count of insts sent to commit
system.cpu0.iew.branchMispredicts                1256                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewBlockCycles                    901                       # Number of cycles IEW is blocking
system.cpu0.iew.iewDispLoadInsts               176074                       # Number of dispatched load instructions
system.cpu0.iew.iewDispNonSpecInsts               725                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewDispSquashedInsts              482                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispStoreInsts               88705                       # Number of dispatched store instructions
system.cpu0.iew.iewDispatchedInsts             544396                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewExecLoadInsts               175581                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts              893                       # Number of squashed instructions skipped in execute
system.cpu0.iew.iewExecutedInsts               454322                       # Number of executed instructions
system.cpu0.iew.iewIQFullEvents                    25                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.iewSquashCycles                  2012                       # Number of cycles IEW is squashing
system.cpu0.iew.iewUnblockCycles                   26                       # Number of cycles IEW is unblocking
system.cpu0.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread.0.cacheBlocked           18                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.lsq.thread.0.forwLoads          85985                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread.0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread.0.memOrderViolation           74                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread.0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread.0.squashedLoads         1564                       # Number of loads squashed
system.cpu0.iew.lsq.thread.0.squashedStores          944                       # Number of stores squashed
system.cpu0.iew.memOrderViolationEvents            74                       # Number of memory order violations
system.cpu0.iew.predictedNotTakenIncorrect          831                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.predictedTakenIncorrect           425                       # Number of branches that were predicted taken incorrectly
system.cpu0.ipc                              1.908091                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        1.908091                       # IPC: Total IPC of All Threads
system.cpu0.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntAlu         191075     41.97%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntMult             0      0.00%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatAdd            0      0.00%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatDiv            0      0.00%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdAdd             0      0.00%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdAlu             0      0.00%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdCmp             0      0.00%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdCvt             0      0.00%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdMisc            0      0.00%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdMult            0      0.00%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdSqrt            0      0.00%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::MemRead        175866     38.63%     80.61% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::MemWrite        88274     19.39%    100.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::total          455215                       # Type of FU issued
system.cpu0.iq.ISSUE:fu_busy_cnt                  184                       # FU busy when requested
system.cpu0.iq.ISSUE:fu_busy_rate            0.000404                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IntAlu               29     15.76%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IntMult               0      0.00%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IntDiv                0      0.00%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatAdd              0      0.00%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatCmp              0      0.00%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatCvt              0      0.00%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatMult             0      0.00%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatDiv              0      0.00%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatSqrt             0      0.00%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdAdd               0      0.00%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdAddAcc            0      0.00%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdAlu               0      0.00%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdCmp               0      0.00%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdCvt               0      0.00%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdMisc              0      0.00%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdMult              0      0.00%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdShift             0      0.00%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdSqrt              0      0.00%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%     15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::MemRead              75     40.76%     56.52% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::MemWrite             80     43.48%    100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:issued_per_cycle::samples       216968                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::mean     2.098074                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::stdev     1.056367                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::0        33344     15.37%     15.37% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::1         5639      2.60%     17.97% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::2        88266     40.68%     58.65% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::3        87233     40.21%     98.85% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::4         1475      0.68%     99.53% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::5          727      0.34%     99.87% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::6          185      0.09%     99.95% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::7           92      0.04%    100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::8            7      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::total       216968                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:rate                    1.935973                       # Inst issue rate
system.cpu0.iq.iqInstsAdded                    456737                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqInstsIssued                   455215                       # Number of instructions issued
system.cpu0.iq.iqNonSpecInstsAdded                822                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqSquashedInstsExamined           7989                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedInstsIssued               42                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedNonSpecRemoved           263                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.iqSquashedOperandsExamined         6440                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.memDep0.conflictingLoads            86348                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores           86194                       # Number of conflicting stores.
system.cpu0.memDep0.insertedLoads              176074                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores              88705                       # Number of stores inserted to the mem dependence unit.
system.cpu0.numCycles                          235135                       # number of cpu cycles simulated
system.cpu0.rename.RENAME:BlockCycles            1287                       # Number of cycles rename is blocking
system.cpu0.rename.RENAME:CommittedMaps        361852                       # Number of HB maps that are committed
system.cpu0.rename.RENAME:IQFullEvents              6                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.RENAME:IdleCycles            20610                       # Number of cycles rename is idle
system.cpu0.rename.RENAME:LSQFullEvents           290                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RENAME:RenameLookups       1089678                       # Number of register rename lookups that rename has made
system.cpu0.rename.RENAME:RenamedInsts         546179                       # Number of instructions processed by rename
system.cpu0.rename.RENAME:RenamedOperands       371907                       # Number of destination operands rename has renamed
system.cpu0.rename.RENAME:RunCycles            180783                       # Number of cycles rename is running
system.cpu0.rename.RENAME:SquashCycles           2012                       # Number of cycles rename is squashing
system.cpu0.rename.RENAME:UnblockCycles           696                       # Number of cycles rename is unblocking
system.cpu0.rename.RENAME:UndoneMaps            10055                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.RENAME:serializeStallCycles        11580                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RENAME:serializingInsts          797                       # count of serializing insts renamed
system.cpu0.rename.RENAME:skidInsts              4205                       # count of insts added to the skid buffer
system.cpu0.rename.RENAME:tempSerializingInsts          813                       # count of temporary serializing insts renamed
system.cpu0.timesIdled                            339                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.workload.PROG:num_syscalls             89                       # Number of system calls
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.BTBHits                   54161                       # Number of BTB hits
system.cpu1.BPredUnit.BTBLookups                56395                       # Number of BTB lookups
system.cpu1.BPredUnit.RASInCorrect                  0                       # Number of incorrect RAS predictions.
system.cpu1.BPredUnit.condIncorrect              1087                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.condPredicted             56507                       # Number of conditional branches predicted
system.cpu1.BPredUnit.lookups                   56507                       # Number of BP lookups
system.cpu1.BPredUnit.usedRAS                       0                       # Number of times the RAS was used to get a target.
system.cpu1.commit.COM:branches                 53696                       # Number of branches committed
system.cpu1.commit.COM:bw_lim_events              485                       # number cycles where commit BW limit reached
system.cpu1.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
system.cpu1.commit.COM:committed_per_cycle::samples       188473                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::mean     1.608787                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::stdev     1.965463                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::0        76772     40.73%     40.73% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::1        54519     28.93%     69.66% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::2         7469      3.96%     73.62% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::3         7244      3.84%     77.47% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::4         2460      1.31%     78.77% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::5        38973     20.68%     99.45% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::6          418      0.22%     99.67% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::7          133      0.07%     99.74% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::8          485      0.26%    100.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::total       188473                       # Number of insts commited each cycle
system.cpu1.commit.COM:count                   303213                       # Number of instructions committed
system.cpu1.commit.COM:loads                    89248                       # Number of loads committed
system.cpu1.commit.COM:membars                   5702                       # Number of memory barriers committed
system.cpu1.commit.COM:refs                    131277                       # Number of memory references committed
system.cpu1.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
system.cpu1.commit.branchMispredicts             1087                       # The number of times a branch was mispredicted
system.cpu1.commit.commitCommittedInsts        303213                       # The number of committed instructions
system.cpu1.commit.commitNonSpecStalls           6416                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.commitSquashedInsts           8260                       # The number of squashed insts skipped by commit
system.cpu1.committedInsts                     253025                       # Number of Instructions Simulated
system.cpu1.committedInsts_total               253025                       # Number of Instructions Simulated
system.cpu1.cpi                              0.791222                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        0.791222                       # CPI: Total CPI of All Threads
system.cpu1.dcache.ReadReq_accesses             51822                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_avg_miss_latency 22047.619048                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13770.186335                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_hits                 51360                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_miss_latency      10186000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_rate         0.008915                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_misses                 462                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_mshr_hits              301                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_miss_latency      2217000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate     0.003107                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_misses            161                       # number of ReadReq MSHR misses
system.cpu1.dcache.SwapReq_accesses                68                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_avg_miss_latency 25285.714286                       # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 22285.714286                       # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_hits                    12                       # number of SwapReq hits
system.cpu1.dcache.SwapReq_miss_latency       1416000                       # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_rate         0.823529                       # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_misses                  56                       # number of SwapReq misses
system.cpu1.dcache.SwapReq_mshr_miss_latency      1248000                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_rate     0.823529                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_misses             56                       # number of SwapReq MSHR misses
system.cpu1.dcache.WriteReq_accesses            41961                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_avg_miss_latency        22916                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 14406.542056                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_hits                41836                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_miss_latency      2864500                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_rate        0.002979                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_misses                125                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_mshr_hits              18                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_miss_latency      1541500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_rate     0.002550                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_misses           107                       # number of WriteReq MSHR misses
system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_refs               1593.333333                       # Average number of references to valid blocks.
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.demand_accesses              93783                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_avg_miss_latency 22232.538330                       # average overall miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency 14024.253731                       # average overall mshr miss latency
system.cpu1.dcache.demand_hits                  93196                       # number of demand (read+write) hits
system.cpu1.dcache.demand_miss_latency       13050500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_rate          0.006259                       # miss rate for demand accesses
system.cpu1.dcache.demand_misses                  587                       # number of demand (read+write) misses
system.cpu1.dcache.demand_mshr_hits               319                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_miss_latency      3758500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_rate     0.002858                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_misses             268                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.occ_%::0                  0.047229                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_%::1                 -0.018864                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_blocks::0            24.181003                       # Average occupied blocks per context
system.cpu1.dcache.occ_blocks::1            -9.658476                       # Average occupied blocks per context
system.cpu1.dcache.overall_accesses             93783                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_avg_miss_latency 22232.538330                       # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency 14024.253731                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_hits                 93196                       # number of overall hits
system.cpu1.dcache.overall_miss_latency      13050500                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_rate         0.006259                       # miss rate for overall accesses
system.cpu1.dcache.overall_misses                 587                       # number of overall misses
system.cpu1.dcache.overall_mshr_hits              319                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_miss_latency      3758500                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_rate     0.002858                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_misses            268                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.replacements                     2                       # number of replacements
system.cpu1.dcache.sampled_refs                    30                       # Sample count of references to valid blocks.
system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.dcache.tagsinuse                14.522528                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                   47800                       # Total number of references to valid blocks.
system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.writebacks                       1                       # number of writebacks
system.cpu1.decode.DECODE:BlockedCycles         20776                       # Number of cycles decode is blocked
system.cpu1.decode.DECODE:DecodedInsts         315521                       # Number of instructions handled by decode
system.cpu1.decode.DECODE:IdleCycles            53573                       # Number of cycles decode is idle
system.cpu1.decode.DECODE:RunCycles            108896                       # Number of cycles decode is running
system.cpu1.decode.DECODE:SquashCycles           1776                       # Number of cycles decode is squashing
system.cpu1.decode.DECODE:UnblockCycles          5228                       # Number of cycles decode is unblocking
system.cpu1.fetch.Branches                      56507                       # Number of branches that fetch encountered
system.cpu1.fetch.CacheLines                    20124                       # Number of cache lines fetched
system.cpu1.fetch.Cycles                       134645                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.IcacheSquashes                  219                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.Insts                        316659                       # Number of instructions fetch has processed
system.cpu1.fetch.SquashCycles                   1165                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.branchRate                 0.282254                       # Number of branch fetches per cycle
system.cpu1.fetch.icacheStallCycles             20124                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.predictedBranches             54161                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.rate                       1.581721                       # Number of inst fetches per cycle
system.cpu1.fetch.rateDist::samples            196865                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.608508                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.050886                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                   82366     41.84%     41.84% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                   58899     29.92%     71.76% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                    6765      3.44%     75.19% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                    2772      1.41%     76.60% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                    1900      0.97%     77.57% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                   39920     20.28%     97.84% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                    2488      1.26%     99.11% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                     254      0.13%     99.24% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                    1501      0.76%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total              196865                       # Number of instructions fetched each cycle (Total)
system.cpu1.icache.ReadReq_accesses             20124                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_avg_miss_latency 15227.650728                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12284.753363                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_hits                 19643                       # number of ReadReq hits
system.cpu1.icache.ReadReq_miss_latency       7324500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_rate         0.023902                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_misses                 481                       # number of ReadReq misses
system.cpu1.icache.ReadReq_mshr_hits               35                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_miss_latency      5479000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate     0.022163                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_misses            446                       # number of ReadReq MSHR misses
system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.icache.avg_refs                 44.042601                       # Average number of references to valid blocks.
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.demand_accesses              20124                       # number of demand (read+write) accesses
system.cpu1.icache.demand_avg_miss_latency 15227.650728                       # average overall miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency 12284.753363                       # average overall mshr miss latency
system.cpu1.icache.demand_hits                  19643                       # number of demand (read+write) hits
system.cpu1.icache.demand_miss_latency        7324500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_rate          0.023902                       # miss rate for demand accesses
system.cpu1.icache.demand_misses                  481                       # number of demand (read+write) misses
system.cpu1.icache.demand_mshr_hits                35                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_miss_latency      5479000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_rate     0.022163                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_misses             446                       # number of demand (read+write) MSHR misses
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.occ_%::0                  0.166563                       # Average percentage of cache occupancy
system.cpu1.icache.occ_blocks::0            85.280274                       # Average occupied blocks per context
system.cpu1.icache.overall_accesses             20124                       # number of overall (read+write) accesses
system.cpu1.icache.overall_avg_miss_latency 15227.650728                       # average overall miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency 12284.753363                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_hits                 19643                       # number of overall hits
system.cpu1.icache.overall_miss_latency       7324500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_rate         0.023902                       # miss rate for overall accesses
system.cpu1.icache.overall_misses                 481                       # number of overall misses
system.cpu1.icache.overall_mshr_hits               35                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_miss_latency      5479000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_rate     0.022163                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_misses            446                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.icache.replacements                   334                       # number of replacements
system.cpu1.icache.sampled_refs                   446                       # Sample count of references to valid blocks.
system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.icache.tagsinuse                85.280274                       # Cycle average of tags in use
system.cpu1.icache.total_refs                   19643                       # Total number of references to valid blocks.
system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.writebacks                       0                       # number of writebacks
system.cpu1.idleCycles                           3334                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.iew.EXEC:branches                   54256                       # Number of branches executed
system.cpu1.iew.EXEC:nop                        45272                       # number of nop insts executed
system.cpu1.iew.EXEC:rate                    1.311145                       # Inst execution rate
system.cpu1.iew.EXEC:refs                      132363                       # number of memory reference insts executed
system.cpu1.iew.EXEC:stores                     42366                       # Number of stores executed
system.cpu1.iew.EXEC:swp                            0                       # number of swp insts executed
system.cpu1.iew.WB:consumers                   152450                       # num instructions consuming a value
system.cpu1.iew.WB:count                       262125                       # cumulative count of insts written-back
system.cpu1.iew.WB:fanout                    0.975992                       # average fanout of values written-back
system.cpu1.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.iew.WB:producers                   148790                       # num instructions producing a value
system.cpu1.iew.WB:rate                      1.309322                       # insts written-back per cycle
system.cpu1.iew.WB:sent                        262257                       # cumulative count of insts sent to commit
system.cpu1.iew.branchMispredicts                1189                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewBlockCycles                   1724                       # Number of cycles IEW is blocking
system.cpu1.iew.iewDispLoadInsts                90756                       # Number of dispatched load instructions
system.cpu1.iew.iewDispNonSpecInsts               936                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewDispSquashedInsts              579                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispStoreInsts               42793                       # Number of dispatched store instructions
system.cpu1.iew.iewDispatchedInsts             311506                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewExecLoadInsts                89997                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts              940                       # Number of squashed instructions skipped in execute
system.cpu1.iew.iewExecutedInsts               262490                       # Number of executed instructions
system.cpu1.iew.iewIQFullEvents                    48                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.iewSquashCycles                  1776                       # Number of cycles IEW is squashing
system.cpu1.iew.iewUnblockCycles                   55                       # Number of cycles IEW is unblocking
system.cpu1.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread.0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.lsq.thread.0.forwLoads          38160                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread.0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread.0.memOrderViolation           37                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread.0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread.0.squashedLoads         1508                       # Number of loads squashed
system.cpu1.iew.lsq.thread.0.squashedStores          764                       # Number of stores squashed
system.cpu1.iew.memOrderViolationEvents            37                       # Number of memory order violations
system.cpu1.iew.predictedNotTakenIncorrect          207                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.predictedTakenIncorrect           982                       # Number of branches that were predicted taken incorrectly
system.cpu1.ipc                              1.263867                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        1.263867                       # IPC: Total IPC of All Threads
system.cpu1.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntAlu         125150     47.51%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntMult             0      0.00%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatAdd            0      0.00%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatDiv            0      0.00%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdAdd             0      0.00%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdAlu             0      0.00%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdCmp             0      0.00%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdCvt             0      0.00%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdMisc            0      0.00%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdMult            0      0.00%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt            0      0.00%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::MemRead         95884     36.40%     83.91% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::MemWrite        42396     16.09%    100.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::total          263430                       # Type of FU issued
system.cpu1.iq.ISSUE:fu_busy_cnt                  193                       # FU busy when requested
system.cpu1.iq.ISSUE:fu_busy_rate            0.000733                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IntAlu               10      5.18%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IntMult               0      0.00%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IntDiv                0      0.00%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatAdd              0      0.00%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatCmp              0      0.00%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatCvt              0      0.00%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatMult             0      0.00%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatDiv              0      0.00%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatSqrt             0      0.00%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdAdd               0      0.00%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdAddAcc            0      0.00%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdAlu               0      0.00%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdCmp               0      0.00%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdCvt               0      0.00%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdMisc              0      0.00%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdMult              0      0.00%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdShift             0      0.00%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdSqrt              0      0.00%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::MemRead              55     28.50%     33.68% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::MemWrite            128     66.32%    100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:issued_per_cycle::samples       196865                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::mean     1.338125                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::stdev     1.287182                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::0        78477     39.86%     39.86% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::1        26779     13.60%     53.47% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::2        44704     22.71%     76.17% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::3        42537     21.61%     97.78% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::4         2555      1.30%     99.08% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::5         1568      0.80%     99.88% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::6          153      0.08%     99.95% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::7           82      0.04%     99.99% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::8           10      0.01%    100.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::total       196865                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:rate                    1.315841                       # Inst issue rate
system.cpu1.iq.iqInstsAdded                    259216                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqInstsIssued                   263430                       # Number of instructions issued
system.cpu1.iq.iqNonSpecInstsAdded               7018                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqSquashedInstsExamined           6568                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedInstsIssued                1                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedNonSpecRemoved           602                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.iqSquashedOperandsExamined         6183                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.memDep0.conflictingLoads            44382                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores           38318                       # Number of conflicting stores.
system.cpu1.memDep0.insertedLoads               90756                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores              42793                       # Number of stores inserted to the mem dependence unit.
system.cpu1.numCycles                          200199                       # number of cpu cycles simulated
system.cpu1.rename.RENAME:BlockCycles            7060                       # Number of cycles rename is blocking
system.cpu1.rename.RENAME:CommittedMaps        207910                       # Number of HB maps that are committed
system.cpu1.rename.RENAME:IQFullEvents             85                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.RENAME:IdleCycles            54204                       # Number of cycles rename is idle
system.cpu1.rename.RENAME:LSQFullEvents            50                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RENAME:RenameLookups        600624                       # Number of register rename lookups that rename has made
system.cpu1.rename.RENAME:RenamedInsts         313715                       # Number of instructions processed by rename
system.cpu1.rename.RENAME:RenamedOperands       216199                       # Number of destination operands rename has renamed
system.cpu1.rename.RENAME:RunCycles            113621                       # Number of cycles rename is running
system.cpu1.rename.RENAME:SquashCycles           1776                       # Number of cycles rename is squashing
system.cpu1.rename.RENAME:UnblockCycles           643                       # Number of cycles rename is unblocking
system.cpu1.rename.RENAME:UndoneMaps             8289                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.RENAME:serializeStallCycles        12945                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RENAME:serializingInsts          960                       # count of serializing insts renamed
system.cpu1.rename.RENAME:skidInsts              2963                       # count of insts added to the skid buffer
system.cpu1.rename.RENAME:tempSerializingInsts         1012                       # count of temporary serializing insts renamed
system.cpu1.timesIdled                            296                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.BPredUnit.BTBHits                   47889                       # Number of BTB hits
system.cpu2.BPredUnit.BTBLookups                50081                       # Number of BTB lookups
system.cpu2.BPredUnit.RASInCorrect                  0                       # Number of incorrect RAS predictions.
system.cpu2.BPredUnit.condIncorrect              1085                       # Number of conditional branches incorrect
system.cpu2.BPredUnit.condPredicted             50180                       # Number of conditional branches predicted
system.cpu2.BPredUnit.lookups                   50180                       # Number of BP lookups
system.cpu2.BPredUnit.usedRAS                       0                       # Number of times the RAS was used to get a target.
system.cpu2.commit.COM:branches                 47494                       # Number of branches committed
system.cpu2.commit.COM:bw_lim_events              498                       # number cycles where commit BW limit reached
system.cpu2.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
system.cpu2.commit.COM:committed_per_cycle::samples       185767                       # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::mean     1.418212                       # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::stdev     1.887646                       # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::0        86596     46.62%     46.62% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::1        48193     25.94%     72.56% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::2         7461      4.02%     76.57% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::3         8520      4.59%     81.16% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::4         2452      1.32%     82.48% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::5        31422     16.91%     99.40% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::6          495      0.27%     99.66% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::7          130      0.07%     99.73% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::8          498      0.27%    100.00% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::total       185767                       # Number of insts commited each cycle
system.cpu2.commit.COM:count                   263457                       # Number of instructions committed
system.cpu2.commit.COM:loads                    75571                       # Number of loads committed
system.cpu2.commit.COM:membars                   6984                       # Number of memory barriers committed
system.cpu2.commit.COM:refs                    110122                       # Number of memory references committed
system.cpu2.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
system.cpu2.commit.branchMispredicts             1085                       # The number of times a branch was mispredicted
system.cpu2.commit.commitCommittedInsts        263457                       # The number of committed instructions
system.cpu2.commit.commitNonSpecStalls           7697                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.commitSquashedInsts           7870                       # The number of squashed insts skipped by commit
system.cpu2.committedInsts                     218188                       # Number of Instructions Simulated
system.cpu2.committedInsts_total               218188                       # Number of Instructions Simulated
system.cpu2.cpi                              0.916214                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        0.916214                       # CPI: Total CPI of All Threads
system.cpu2.dcache.ReadReq_accesses             45603                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_avg_miss_latency 22462.882096                       # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 15906.060606                       # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_hits                 45145                       # number of ReadReq hits
system.cpu2.dcache.ReadReq_miss_latency      10288000                       # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_rate         0.010043                       # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_misses                 458                       # number of ReadReq misses
system.cpu2.dcache.ReadReq_mshr_hits              293                       # number of ReadReq MSHR hits
system.cpu2.dcache.ReadReq_mshr_miss_latency      2624500                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate     0.003618                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_misses            165                       # number of ReadReq MSHR misses
system.cpu2.dcache.SwapReq_accesses                67                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_avg_miss_latency 27057.692308                       # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 24057.692308                       # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_hits                    15                       # number of SwapReq hits
system.cpu2.dcache.SwapReq_miss_latency       1407000                       # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_rate         0.776119                       # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_misses                  52                       # number of SwapReq misses
system.cpu2.dcache.SwapReq_mshr_miss_latency      1251000                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_rate     0.776119                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_misses             52                       # number of SwapReq MSHR misses
system.cpu2.dcache.WriteReq_accesses            34484                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_avg_miss_latency 24804.878049                       # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 16634.615385                       # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_hits                34361                       # number of WriteReq hits
system.cpu2.dcache.WriteReq_miss_latency      3051000                       # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_rate        0.003567                       # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_misses                123                       # number of WriteReq misses
system.cpu2.dcache.WriteReq_mshr_hits              19                       # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_miss_latency      1730000                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_rate     0.003016                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_misses           104                       # number of WriteReq MSHR misses
system.cpu2.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu2.dcache.avg_refs               1342.733333                       # Average number of references to valid blocks.
system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu2.dcache.demand_accesses              80087                       # number of demand (read+write) accesses
system.cpu2.dcache.demand_avg_miss_latency 22958.691910                       # average overall miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency 16187.732342                       # average overall mshr miss latency
system.cpu2.dcache.demand_hits                  79506                       # number of demand (read+write) hits
system.cpu2.dcache.demand_miss_latency       13339000                       # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_rate          0.007255                       # miss rate for demand accesses
system.cpu2.dcache.demand_misses                  581                       # number of demand (read+write) misses
system.cpu2.dcache.demand_mshr_hits               312                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_miss_latency      4354500                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_rate     0.003359                       # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_misses             269                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu2.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.dcache.occ_%::0                  0.052876                       # Average percentage of cache occupancy
system.cpu2.dcache.occ_%::1                 -0.017040                       # Average percentage of cache occupancy
system.cpu2.dcache.occ_blocks::0            27.072320                       # Average occupied blocks per context
system.cpu2.dcache.occ_blocks::1            -8.724259                       # Average occupied blocks per context
system.cpu2.dcache.overall_accesses             80087                       # number of overall (read+write) accesses
system.cpu2.dcache.overall_avg_miss_latency 22958.691910                       # average overall miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency 16187.732342                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu2.dcache.overall_hits                 79506                       # number of overall hits
system.cpu2.dcache.overall_miss_latency      13339000                       # number of overall miss cycles
system.cpu2.dcache.overall_miss_rate         0.007255                       # miss rate for overall accesses
system.cpu2.dcache.overall_misses                 581                       # number of overall misses
system.cpu2.dcache.overall_mshr_hits              312                       # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_miss_latency      4354500                       # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_rate     0.003359                       # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_misses            269                       # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu2.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu2.dcache.replacements                     2                       # number of replacements
system.cpu2.dcache.sampled_refs                    30                       # Sample count of references to valid blocks.
system.cpu2.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu2.dcache.tagsinuse                18.348061                       # Cycle average of tags in use
system.cpu2.dcache.total_refs                   40282                       # Total number of references to valid blocks.
system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu2.dcache.writebacks                       1                       # number of writebacks
system.cpu2.decode.DECODE:BlockedCycles         22115                       # Number of cycles decode is blocked
system.cpu2.decode.DECODE:DecodedInsts         275229                       # Number of instructions handled by decode
system.cpu2.decode.DECODE:IdleCycles            60651                       # Number of cycles decode is idle
system.cpu2.decode.DECODE:RunCycles             96513                       # Number of cycles decode is running
system.cpu2.decode.DECODE:SquashCycles           1718                       # Number of cycles decode is squashing
system.cpu2.decode.DECODE:UnblockCycles          6488                       # Number of cycles decode is unblocking
system.cpu2.fetch.Branches                      50180                       # Number of branches that fetch encountered
system.cpu2.fetch.CacheLines                    22951                       # Number of cache lines fetched
system.cpu2.fetch.Cycles                       126346                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.IcacheSquashes                  219                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.Insts                        276356                       # Number of instructions fetch has processed
system.cpu2.fetch.SquashCycles                   1162                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.branchRate                 0.251017                       # Number of branch fetches per cycle
system.cpu2.fetch.icacheStallCycles             22951                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.predictedBranches             47889                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.rate                       1.382423                       # Number of inst fetches per cycle
system.cpu2.fetch.rateDist::samples            194083                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.423906                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            1.970447                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                   90718     46.74%     46.74% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                   54044     27.85%     74.59% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                    8214      4.23%     78.82% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                    2581      1.33%     80.15% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                    1900      0.98%     81.13% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                   32424     16.71%     97.83% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                    2464      1.27%     99.10% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                     267      0.14%     99.24% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                    1471      0.76%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total              194083                       # Number of instructions fetched each cycle (Total)
system.cpu2.icache.ReadReq_accesses             22951                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_avg_miss_latency 21668.711656                       # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18378.959276                       # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_hits                 22462                       # number of ReadReq hits
system.cpu2.icache.ReadReq_miss_latency      10596000                       # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_rate         0.021306                       # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_misses                 489                       # number of ReadReq misses
system.cpu2.icache.ReadReq_mshr_hits               47                       # number of ReadReq MSHR hits
system.cpu2.icache.ReadReq_mshr_miss_latency      8123500                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate     0.019258                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_misses            442                       # number of ReadReq MSHR misses
system.cpu2.icache.avg_blocked_cycles::no_mshrs        18250                       # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu2.icache.avg_refs                 50.819005                       # Average number of references to valid blocks.
system.cpu2.icache.blocked::no_mshrs                2                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_mshrs        36500                       # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
system.cpu2.icache.demand_accesses              22951                       # number of demand (read+write) accesses
system.cpu2.icache.demand_avg_miss_latency 21668.711656                       # average overall miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency 18378.959276                       # average overall mshr miss latency
system.cpu2.icache.demand_hits                  22462                       # number of demand (read+write) hits
system.cpu2.icache.demand_miss_latency       10596000                       # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_rate          0.021306                       # miss rate for demand accesses
system.cpu2.icache.demand_misses                  489                       # number of demand (read+write) misses
system.cpu2.icache.demand_mshr_hits                47                       # number of demand (read+write) MSHR hits
system.cpu2.icache.demand_mshr_miss_latency      8123500                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_rate     0.019258                       # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_misses             442                       # number of demand (read+write) MSHR misses
system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
system.cpu2.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.icache.occ_%::0                  0.176802                       # Average percentage of cache occupancy
system.cpu2.icache.occ_blocks::0            90.522409                       # Average occupied blocks per context
system.cpu2.icache.overall_accesses             22951                       # number of overall (read+write) accesses
system.cpu2.icache.overall_avg_miss_latency 21668.711656                       # average overall miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency 18378.959276                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu2.icache.overall_hits                 22462                       # number of overall hits
system.cpu2.icache.overall_miss_latency      10596000                       # number of overall miss cycles
system.cpu2.icache.overall_miss_rate         0.021306                       # miss rate for overall accesses
system.cpu2.icache.overall_misses                 489                       # number of overall misses
system.cpu2.icache.overall_mshr_hits               47                       # number of overall MSHR hits
system.cpu2.icache.overall_mshr_miss_latency      8123500                       # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_rate     0.019258                       # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_misses            442                       # number of overall MSHR misses
system.cpu2.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu2.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu2.icache.replacements                   332                       # number of replacements
system.cpu2.icache.sampled_refs                   442                       # Sample count of references to valid blocks.
system.cpu2.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu2.icache.tagsinuse                90.522409                       # Cycle average of tags in use
system.cpu2.icache.total_refs                   22462                       # Total number of references to valid blocks.
system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu2.icache.writebacks                       0                       # number of writebacks
system.cpu2.idleCycles                           5824                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.iew.EXEC:branches                   48041                       # Number of branches executed
system.cpu2.iew.EXEC:nop                        38985                       # number of nop insts executed
system.cpu2.iew.EXEC:rate                    1.144757                       # Inst execution rate
system.cpu2.iew.EXEC:refs                      111164                       # number of memory reference insts executed
system.cpu2.iew.EXEC:stores                     34874                       # Number of stores executed
system.cpu2.iew.EXEC:swp                            0                       # number of swp insts executed
system.cpu2.iew.WB:consumers                   131236                       # num instructions consuming a value
system.cpu2.iew.WB:count                       228477                       # cumulative count of insts written-back
system.cpu2.iew.WB:fanout                    0.972142                       # average fanout of values written-back
system.cpu2.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.iew.WB:producers                   127580                       # num instructions producing a value
system.cpu2.iew.WB:rate                      1.142916                       # insts written-back per cycle
system.cpu2.iew.WB:sent                        228606                       # cumulative count of insts sent to commit
system.cpu2.iew.branchMispredicts                1190                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewBlockCycles                   1615                       # Number of cycles IEW is blocking
system.cpu2.iew.iewDispLoadInsts                76990                       # Number of dispatched load instructions
system.cpu2.iew.iewDispNonSpecInsts               921                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewDispSquashedInsts              577                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispStoreInsts               35262                       # Number of dispatched store instructions
system.cpu2.iew.iewDispatchedInsts             271358                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewExecLoadInsts                76290                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts              955                       # Number of squashed instructions skipped in execute
system.cpu2.iew.iewExecutedInsts               228845                       # Number of executed instructions
system.cpu2.iew.iewIQFullEvents                    46                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.iewSquashCycles                  1718                       # Number of cycles IEW is squashing
system.cpu2.iew.iewUnblockCycles                   53                       # Number of cycles IEW is unblocking
system.cpu2.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread.0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.lsq.thread.0.forwLoads          30669                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread.0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread.0.memOrderViolation           36                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread.0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread.0.squashedLoads         1419                       # Number of loads squashed
system.cpu2.iew.lsq.thread.0.squashedStores          711                       # Number of stores squashed
system.cpu2.iew.memOrderViolationEvents            36                       # Number of memory order violations
system.cpu2.iew.predictedNotTakenIncorrect          197                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.predictedTakenIncorrect           993                       # Number of branches that were predicted taken incorrectly
system.cpu2.ipc                              1.091448                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        1.091448                       # IPC: Total IPC of All Threads
system.cpu2.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::IntAlu         111446     48.50%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::IntMult             0      0.00%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::FloatAdd            0      0.00%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::FloatDiv            0      0.00%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdAdd             0      0.00%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdAlu             0      0.00%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdCmp             0      0.00%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdCvt             0      0.00%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdMisc            0      0.00%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdMult            0      0.00%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdSqrt            0      0.00%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::MemRead         83455     36.32%     84.81% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::MemWrite        34899     15.19%    100.00% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::total          229800                       # Type of FU issued
system.cpu2.iq.ISSUE:fu_busy_cnt                  187                       # FU busy when requested
system.cpu2.iq.ISSUE:fu_busy_rate            0.000814                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::IntAlu               11      5.88%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::IntMult               0      0.00%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::IntDiv                0      0.00%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::FloatAdd              0      0.00%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::FloatCmp              0      0.00%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::FloatCvt              0      0.00%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::FloatMult             0      0.00%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::FloatDiv              0      0.00%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::FloatSqrt             0      0.00%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdAdd               0      0.00%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdAddAcc            0      0.00%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdAlu               0      0.00%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdCmp               0      0.00%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdCvt               0      0.00%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdMisc              0      0.00%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdMult              0      0.00%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdShift             0      0.00%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdSqrt              0      0.00%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::MemRead              48     25.67%     31.55% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::MemWrite            128     68.45%    100.00% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.ISSUE:issued_per_cycle::samples       194083                       # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::mean     1.184030                       # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::stdev     1.270781                       # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::0        86865     44.76%     44.76% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::1        30647     15.79%     60.55% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::2        37170     19.15%     79.70% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::3        34973     18.02%     97.72% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::4         2604      1.34%     99.06% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::5         1569      0.81%     99.87% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::6          161      0.08%     99.95% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::7           85      0.04%    100.00% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::8            9      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::total       194083                       # Number of insts issued each cycle
system.cpu2.iq.ISSUE:rate                    1.149535                       # Inst issue rate
system.cpu2.iq.iqInstsAdded                    224135                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqInstsIssued                   229800                       # Number of instructions issued
system.cpu2.iq.iqNonSpecInstsAdded               8238                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqSquashedInstsExamined           6304                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedNonSpecRemoved           541                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.iqSquashedOperandsExamined         5829                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.memDep0.conflictingLoads            38114                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores           30803                       # Number of conflicting stores.
system.cpu2.memDep0.insertedLoads               76990                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores              35262                       # Number of stores inserted to the mem dependence unit.
system.cpu2.numCycles                          199907                       # number of cpu cycles simulated
system.cpu2.rename.RENAME:BlockCycles            8148                       # Number of cycles rename is blocking
system.cpu2.rename.RENAME:CommittedMaps        179272                       # Number of HB maps that are committed
system.cpu2.rename.RENAME:IQFullEvents             31                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.RENAME:IdleCycles            61263                       # Number of cycles rename is idle
system.cpu2.rename.RENAME:LSQFullEvents            56                       # Number of times rename has blocked due to LSQ full
system.cpu2.rename.RENAME:RenameLookups        515407                       # Number of register rename lookups that rename has made
system.cpu2.rename.RENAME:RenamedInsts         273547                       # Number of instructions processed by rename
system.cpu2.rename.RENAME:RenamedOperands       187363                       # Number of destination operands rename has renamed
system.cpu2.rename.RENAME:RunCycles            102562                       # Number of cycles rename is running
system.cpu2.rename.RENAME:SquashCycles           1718                       # Number of cycles rename is squashing
system.cpu2.rename.RENAME:UnblockCycles           553                       # Number of cycles rename is unblocking
system.cpu2.rename.RENAME:UndoneMaps             8091                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.RENAME:serializeStallCycles        13241                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RENAME:serializingInsts          943                       # count of serializing insts renamed
system.cpu2.rename.RENAME:skidInsts              2678                       # count of insts added to the skid buffer
system.cpu2.rename.RENAME:tempSerializingInsts          998                       # count of temporary serializing insts renamed
system.cpu2.timesIdled                            306                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.BPredUnit.BTBHits                   51000                       # Number of BTB hits
system.cpu3.BPredUnit.BTBLookups                53222                       # Number of BTB lookups
system.cpu3.BPredUnit.RASInCorrect                  0                       # Number of incorrect RAS predictions.
system.cpu3.BPredUnit.condIncorrect              1107                       # Number of conditional branches incorrect
system.cpu3.BPredUnit.condPredicted             53282                       # Number of conditional branches predicted
system.cpu3.BPredUnit.lookups                   53282                       # Number of BP lookups
system.cpu3.BPredUnit.usedRAS                       0                       # Number of times the RAS was used to get a target.
system.cpu3.commit.COM:branches                 50377                       # Number of branches committed
system.cpu3.commit.COM:bw_lim_events              486                       # number cycles where commit BW limit reached
system.cpu3.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
system.cpu3.commit.COM:committed_per_cycle::samples       188057                       # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::mean     1.497514                       # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::stdev     1.921417                       # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::0        82996     44.13%     44.13% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::1        51194     27.22%     71.36% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::2         7476      3.98%     75.33% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::3         8061      4.29%     79.62% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::4         2450      1.30%     80.92% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::5        34892     18.55%     99.47% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::6          373      0.20%     99.67% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::7          129      0.07%     99.74% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::8          486      0.26%    100.00% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::total       188057                       # Number of insts commited each cycle
system.cpu3.commit.COM:count                   281618                       # Number of instructions committed
system.cpu3.commit.COM:loads                    81766                       # Number of loads committed
system.cpu3.commit.COM:membars                   6531                       # Number of memory barriers committed
system.cpu3.commit.COM:refs                    119649                       # Number of memory references committed
system.cpu3.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
system.cpu3.commit.branchMispredicts             1107                       # The number of times a branch was mispredicted
system.cpu3.commit.commitCommittedInsts        281618                       # The number of committed instructions
system.cpu3.commit.commitNonSpecStalls           7250                       # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.commitSquashedInsts           8574                       # The number of squashed insts skipped by commit
system.cpu3.committedInsts                     233925                       # Number of Instructions Simulated
system.cpu3.committedInsts_total               233925                       # Number of Instructions Simulated
system.cpu3.cpi                              0.853423                       # CPI: Cycles Per Instruction
system.cpu3.cpi_total                        0.853423                       # CPI: Total CPI of All Threads
system.cpu3.dcache.ReadReq_accesses             48473                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_avg_miss_latency 22753.504673                       # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 14018.518519                       # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_hits                 48045                       # number of ReadReq hits
system.cpu3.dcache.ReadReq_miss_latency       9738500                       # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_rate         0.008830                       # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_misses                 428                       # number of ReadReq misses
system.cpu3.dcache.ReadReq_mshr_hits              266                       # number of ReadReq MSHR hits
system.cpu3.dcache.ReadReq_mshr_miss_latency      2271000                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate     0.003342                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_misses            162                       # number of ReadReq MSHR misses
system.cpu3.dcache.SwapReq_accesses                73                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_avg_miss_latency 25166.666667                       # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 22166.666667                       # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_hits                    13                       # number of SwapReq hits
system.cpu3.dcache.SwapReq_miss_latency       1510000                       # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_rate         0.821918                       # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_misses                  60                       # number of SwapReq misses
system.cpu3.dcache.SwapReq_mshr_miss_latency      1330000                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_rate     0.821918                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_misses             60                       # number of SwapReq MSHR misses
system.cpu3.dcache.WriteReq_accesses            37810                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_avg_miss_latency 24109.243697                       # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 15764.705882                       # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_hits                37691                       # number of WriteReq hits
system.cpu3.dcache.WriteReq_miss_latency      2869000                       # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_rate        0.003147                       # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_misses                119                       # number of WriteReq misses
system.cpu3.dcache.WriteReq_mshr_hits              17                       # number of WriteReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_miss_latency      1608000                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_rate     0.002698                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_misses           102                       # number of WriteReq MSHR misses
system.cpu3.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu3.dcache.avg_refs               1503.344828                       # Average number of references to valid blocks.
system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu3.dcache.demand_accesses              86283                       # number of demand (read+write) accesses
system.cpu3.dcache.demand_avg_miss_latency 23048.446069                       # average overall miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency 14693.181818                       # average overall mshr miss latency
system.cpu3.dcache.demand_hits                  85736                       # number of demand (read+write) hits
system.cpu3.dcache.demand_miss_latency       12607500                       # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_rate          0.006340                       # miss rate for demand accesses
system.cpu3.dcache.demand_misses                  547                       # number of demand (read+write) misses
system.cpu3.dcache.demand_mshr_hits               283                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_miss_latency      3879000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_rate     0.003060                       # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_misses             264                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu3.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.dcache.occ_%::0                  0.049266                       # Average percentage of cache occupancy
system.cpu3.dcache.occ_%::1                 -0.015422                       # Average percentage of cache occupancy
system.cpu3.dcache.occ_blocks::0            25.223945                       # Average occupied blocks per context
system.cpu3.dcache.occ_blocks::1            -7.896204                       # Average occupied blocks per context
system.cpu3.dcache.overall_accesses             86283                       # number of overall (read+write) accesses
system.cpu3.dcache.overall_avg_miss_latency 23048.446069                       # average overall miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency 14693.181818                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu3.dcache.overall_hits                 85736                       # number of overall hits
system.cpu3.dcache.overall_miss_latency      12607500                       # number of overall miss cycles
system.cpu3.dcache.overall_miss_rate         0.006340                       # miss rate for overall accesses
system.cpu3.dcache.overall_misses                 547                       # number of overall misses
system.cpu3.dcache.overall_mshr_hits              283                       # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_miss_latency      3879000                       # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_rate     0.003060                       # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_misses            264                       # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu3.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu3.dcache.replacements                     2                       # number of replacements
system.cpu3.dcache.sampled_refs                    29                       # Sample count of references to valid blocks.
system.cpu3.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu3.dcache.tagsinuse                17.327741                       # Cycle average of tags in use
system.cpu3.dcache.total_refs                   43597                       # Total number of references to valid blocks.
system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu3.dcache.writebacks                       1                       # number of writebacks
system.cpu3.decode.DECODE:BlockedCycles         21716                       # Number of cycles decode is blocked
system.cpu3.decode.DECODE:DecodedInsts         294261                       # Number of instructions handled by decode
system.cpu3.decode.DECODE:IdleCycles            57777                       # Number of cycles decode is idle
system.cpu3.decode.DECODE:RunCycles            102518                       # Number of cycles decode is running
system.cpu3.decode.DECODE:SquashCycles           1820                       # Number of cycles decode is squashing
system.cpu3.decode.DECODE:UnblockCycles          6046                       # Number of cycles decode is unblocking
system.cpu3.fetch.Branches                      53282                       # Number of branches that fetch encountered
system.cpu3.fetch.CacheLines                    21872                       # Number of cache lines fetched
system.cpu3.fetch.Cycles                       130835                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.IcacheSquashes                  221                       # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.Insts                        295412                       # Number of instructions fetch has processed
system.cpu3.fetch.SquashCycles                   1181                       # Number of cycles fetch has spent squashing
system.cpu3.fetch.branchRate                 0.266894                       # Number of branch fetches per cycle
system.cpu3.fetch.icacheStallCycles             21872                       # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.predictedBranches             51000                       # Number of branches that fetch has predicted taken
system.cpu3.fetch.rate                       1.479746                       # Number of inst fetches per cycle
system.cpu3.fetch.rateDist::samples            196481                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean             1.503514                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev            2.005027                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0                   87542     44.55%     44.55% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1                   56519     28.77%     73.32% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2                    7661      3.90%     77.22% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3                    2862      1.46%     78.68% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4                    1914      0.97%     79.65% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5                   35774     18.21%     97.86% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6                    2478      1.26%     99.12% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7                     257      0.13%     99.25% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8                    1474      0.75%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total              196481                       # Number of instructions fetched each cycle (Total)
system.cpu3.icache.ReadReq_accesses             21872                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_avg_miss_latency 14323.590814                       # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11652.370203                       # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_hits                 21393                       # number of ReadReq hits
system.cpu3.icache.ReadReq_miss_latency       6861000                       # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_rate         0.021900                       # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_misses                 479                       # number of ReadReq misses
system.cpu3.icache.ReadReq_mshr_hits               36                       # number of ReadReq MSHR hits
system.cpu3.icache.ReadReq_mshr_miss_latency      5162000                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate     0.020254                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_misses            443                       # number of ReadReq MSHR misses
system.cpu3.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu3.icache.avg_refs                 48.291196                       # Average number of references to valid blocks.
system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
system.cpu3.icache.demand_accesses              21872                       # number of demand (read+write) accesses
system.cpu3.icache.demand_avg_miss_latency 14323.590814                       # average overall miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency 11652.370203                       # average overall mshr miss latency
system.cpu3.icache.demand_hits                  21393                       # number of demand (read+write) hits
system.cpu3.icache.demand_miss_latency        6861000                       # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_rate          0.021900                       # miss rate for demand accesses
system.cpu3.icache.demand_misses                  479                       # number of demand (read+write) misses
system.cpu3.icache.demand_mshr_hits                36                       # number of demand (read+write) MSHR hits
system.cpu3.icache.demand_mshr_miss_latency      5162000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_rate     0.020254                       # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_misses             443                       # number of demand (read+write) MSHR misses
system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
system.cpu3.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.icache.occ_%::0                  0.173082                       # Average percentage of cache occupancy
system.cpu3.icache.occ_blocks::0            88.617750                       # Average occupied blocks per context
system.cpu3.icache.overall_accesses             21872                       # number of overall (read+write) accesses
system.cpu3.icache.overall_avg_miss_latency 14323.590814                       # average overall miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency 11652.370203                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu3.icache.overall_hits                 21393                       # number of overall hits
system.cpu3.icache.overall_miss_latency       6861000                       # number of overall miss cycles
system.cpu3.icache.overall_miss_rate         0.021900                       # miss rate for overall accesses
system.cpu3.icache.overall_misses                 479                       # number of overall misses
system.cpu3.icache.overall_mshr_hits               36                       # number of overall MSHR hits
system.cpu3.icache.overall_mshr_miss_latency      5162000                       # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_rate     0.020254                       # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_misses            443                       # number of overall MSHR misses
system.cpu3.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu3.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu3.icache.replacements                   331                       # number of replacements
system.cpu3.icache.sampled_refs                   443                       # Sample count of references to valid blocks.
system.cpu3.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu3.icache.tagsinuse                88.617750                       # Cycle average of tags in use
system.cpu3.icache.total_refs                   21393                       # Total number of references to valid blocks.
system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu3.icache.writebacks                       0                       # number of writebacks
system.cpu3.idleCycles                           3156                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.iew.EXEC:branches                   50931                       # Number of branches executed
system.cpu3.iew.EXEC:nop                        42039                       # number of nop insts executed
system.cpu3.iew.EXEC:rate                    1.222935                       # Inst execution rate
system.cpu3.iew.EXEC:refs                      120716                       # number of memory reference insts executed
system.cpu3.iew.EXEC:stores                     38219                       # Number of stores executed
system.cpu3.iew.EXEC:swp                            0                       # number of swp insts executed
system.cpu3.iew.WB:consumers                   140772                       # num instructions consuming a value
system.cpu3.iew.WB:count                       243777                       # cumulative count of insts written-back
system.cpu3.iew.WB:fanout                    0.974072                       # average fanout of values written-back
system.cpu3.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu3.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu3.iew.WB:producers                   137122                       # num instructions producing a value
system.cpu3.iew.WB:rate                      1.221101                       # insts written-back per cycle
system.cpu3.iew.WB:sent                        243910                       # cumulative count of insts sent to commit
system.cpu3.iew.branchMispredicts                1214                       # Number of branch mispredicts detected at execute
system.cpu3.iew.iewBlockCycles                   1676                       # Number of cycles IEW is blocking
system.cpu3.iew.iewDispLoadInsts                83353                       # Number of dispatched load instructions
system.cpu3.iew.iewDispNonSpecInsts               943                       # Number of dispatched non-speculative instructions
system.cpu3.iew.iewDispSquashedInsts              577                       # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispStoreInsts               38642                       # Number of dispatched store instructions
system.cpu3.iew.iewDispatchedInsts             290221                       # Number of instructions dispatched to IQ
system.cpu3.iew.iewExecLoadInsts                82497                       # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts              962                       # Number of squashed instructions skipped in execute
system.cpu3.iew.iewExecutedInsts               244143                       # Number of executed instructions
system.cpu3.iew.iewIQFullEvents                    55                       # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.iewSquashCycles                  1820                       # Number of cycles IEW is squashing
system.cpu3.iew.iewUnblockCycles                   60                       # Number of cycles IEW is unblocking
system.cpu3.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread.0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.lsq.thread.0.forwLoads          34006                       # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread.0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread.0.memOrderViolation           33                       # Number of memory ordering violations
system.cpu3.iew.lsq.thread.0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread.0.squashedLoads         1587                       # Number of loads squashed
system.cpu3.iew.lsq.thread.0.squashedStores          759                       # Number of stores squashed
system.cpu3.iew.memOrderViolationEvents            33                       # Number of memory order violations
system.cpu3.iew.predictedNotTakenIncorrect          191                       # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.predictedTakenIncorrect          1023                       # Number of branches that were predicted taken incorrectly
system.cpu3.ipc                              1.171752                       # IPC: Instructions Per Cycle
system.cpu3.ipc_total                        1.171752                       # IPC: Total IPC of All Threads
system.cpu3.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::IntAlu         117646     48.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::IntMult             0      0.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::FloatAdd            0      0.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::FloatDiv            0      0.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdAdd             0      0.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdAlu             0      0.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdCmp             0      0.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdCvt             0      0.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdMisc            0      0.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdMult            0      0.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdSqrt            0      0.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::MemRead         89212     36.40%     84.40% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::MemWrite        38247     15.60%    100.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::total          245105                       # Type of FU issued
system.cpu3.iq.ISSUE:fu_busy_cnt                  192                       # FU busy when requested
system.cpu3.iq.ISSUE:fu_busy_rate            0.000783                       # FU busy rate (busy events/executed inst)
system.cpu3.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::IntAlu               10      5.21%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::IntMult               0      0.00%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::IntDiv                0      0.00%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::FloatAdd              0      0.00%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::FloatCmp              0      0.00%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::FloatCvt              0      0.00%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::FloatMult             0      0.00%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::FloatDiv              0      0.00%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::FloatSqrt             0      0.00%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdAdd               0      0.00%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdAddAcc            0      0.00%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdAlu               0      0.00%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdCmp               0      0.00%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdCvt               0      0.00%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdMisc              0      0.00%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdMult              0      0.00%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdShift             0      0.00%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdSqrt              0      0.00%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::MemRead              54     28.12%     33.33% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::MemWrite            128     66.67%    100.00% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.ISSUE:issued_per_cycle::samples       196481                       # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::mean     1.247474                       # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::stdev     1.278014                       # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::0        83915     42.71%     42.71% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::1        29209     14.87%     57.58% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::2        40640     20.68%     78.26% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::3        38393     19.54%     97.80% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::4         2530      1.29%     99.09% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::5         1549      0.79%     99.88% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::6          153      0.08%     99.95% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::7           82      0.04%     99.99% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::8           10      0.01%    100.00% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::total       196481                       # Number of insts issued each cycle
system.cpu3.iq.ISSUE:rate                    1.227753                       # Inst issue rate
system.cpu3.iq.iqInstsAdded                    240238                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqInstsIssued                   245105                       # Number of instructions issued
system.cpu3.iq.iqNonSpecInstsAdded               7944                       # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqSquashedInstsExamined           6797                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedInstsIssued                1                       # Number of squashed instructions issued
system.cpu3.iq.iqSquashedNonSpecRemoved           694                       # Number of squashed non-spec instructions that were removed
system.cpu3.iq.iqSquashedOperandsExamined         6548                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.memDep0.conflictingLoads            41135                       # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores           34159                       # Number of conflicting stores.
system.cpu3.memDep0.insertedLoads               83353                       # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores              38642                       # Number of stores inserted to the mem dependence unit.
system.cpu3.numCycles                          199637                       # number of cpu cycles simulated
system.cpu3.rename.RENAME:BlockCycles            7787                       # Number of cycles rename is blocking
system.cpu3.rename.RENAME:CommittedMaps        192127                       # Number of HB maps that are committed
system.cpu3.rename.RENAME:IQFullEvents             59                       # Number of times rename has blocked due to IQ full
system.cpu3.rename.RENAME:IdleCycles            58403                       # Number of cycles rename is idle
system.cpu3.rename.RENAME:LSQFullEvents            39                       # Number of times rename has blocked due to LSQ full
system.cpu3.rename.RENAME:RenameLookups        554400                       # Number of register rename lookups that rename has made
system.cpu3.rename.RENAME:RenamedInsts         292478                       # Number of instructions processed by rename
system.cpu3.rename.RENAME:RenamedOperands       200449                       # Number of destination operands rename has renamed
system.cpu3.rename.RENAME:RunCycles            108083                       # Number of cycles rename is running
system.cpu3.rename.RENAME:SquashCycles           1820                       # Number of cycles rename is squashing
system.cpu3.rename.RENAME:UnblockCycles           588                       # Number of cycles rename is unblocking
system.cpu3.rename.RENAME:UndoneMaps             8322                       # Number of HB maps that are undone due to squashing
system.cpu3.rename.RENAME:serializeStallCycles        13196                       # count of cycles rename stalled for serializing inst
system.cpu3.rename.RENAME:serializingInsts          964                       # count of serializing insts renamed
system.cpu3.rename.RENAME:skidInsts              2784                       # count of insts added to the skid buffer
system.cpu3.rename.RENAME:tempSerializingInsts         1016                       # count of temporary serializing insts renamed
system.cpu3.timesIdled                            293                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.l2c.ReadExReq_accesses::0                   94                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::1                   12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::2                   13                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::3                   12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_avg_miss_latency::0 73191.489362                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1 573333.333333                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::2 529230.769231                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::3 573333.333333                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 1749088.925259                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40335.877863                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_miss_latency             6880000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_rate::0                   1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::1                   1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::2                   1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::3                   1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total               4                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses::0                     94                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::1                     12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::2                     13                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::3                     12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
system.l2c.ReadExReq_mshr_miss_latency        5284000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate::0       1.393617                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1      10.916667                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::2      10.076923                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::3      10.916667                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total    33.303873                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_misses                  131                       # number of ReadExReq MSHR misses
system.l2c.ReadReq_accesses::0                    689                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1                    459                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::2                    456                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::3                    456                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total               2060                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_avg_miss_latency::0   63650.334076                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1   2381583.333333                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::2   340226.190476                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::3        5715800                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 8501259.857885                       # average ReadReq miss latency
system.l2c.ReadReq_avg_mshr_miss_latency 40001.841621                       # average ReadReq mshr miss latency
system.l2c.ReadReq_hits::0                        240                       # number of ReadReq hits
system.l2c.ReadReq_hits::1                        447                       # number of ReadReq hits
system.l2c.ReadReq_hits::2                        372                       # number of ReadReq hits
system.l2c.ReadReq_hits::3                        451                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                   1510                       # number of ReadReq hits
system.l2c.ReadReq_miss_latency              28579000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_rate::0              0.651669                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1              0.026144                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::2              0.184211                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::3              0.010965                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.872988                       # miss rate for ReadReq accesses
system.l2c.ReadReq_misses::0                      449                       # number of ReadReq misses
system.l2c.ReadReq_misses::1                       12                       # number of ReadReq misses
system.l2c.ReadReq_misses::2                       84                       # number of ReadReq misses
system.l2c.ReadReq_misses::3                        5                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                  550                       # number of ReadReq misses
system.l2c.ReadReq_mshr_hits                        7                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_miss_latency         21721000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::0         0.788099                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1         1.183007                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::2         1.190789                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::3         1.190789                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     4.352684                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_misses                    543                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_accesses::0                  29                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::1                  21                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::2                  25                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::3                  23                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              98                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_avg_miss_latency::0         6000                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1  7428.571429                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::2         6240                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::3  6782.608696                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 26451.180124                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_hits::0                       3                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                   3                       # number of UpgradeReq hits
system.l2c.UpgradeReq_miss_latency             156000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_rate::0           0.896552                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::1                  1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::2                  1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::3                  1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       3.896552                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses::0                    26                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::1                    21                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::2                    25                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::3                    23                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total                95                       # number of UpgradeReq misses
system.l2c.UpgradeReq_mshr_miss_latency       3800000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_rate::0      3.275862                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1      4.523810                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::2      3.800000                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::3      4.130435                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total    15.730106                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_misses                  95                       # number of UpgradeReq MSHR misses
system.l2c.Writeback_accesses::0                    9                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total                9                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits::0                        9                       # number of Writeback hits
system.l2c.Writeback_hits::total                    9                       # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.l2c.avg_refs                          2.765138                       # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.demand_accesses::0                     783                       # number of demand (read+write) accesses
system.l2c.demand_accesses::1                     471                       # number of demand (read+write) accesses
system.l2c.demand_accesses::2                     469                       # number of demand (read+write) accesses
system.l2c.demand_accesses::3                     468                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total                2191                       # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency::0    65302.025783                       # average overall miss latency
system.l2c.demand_avg_miss_latency::1    1477458.333333                       # average overall miss latency
system.l2c.demand_avg_miss_latency::2    365556.701031                       # average overall miss latency
system.l2c.demand_avg_miss_latency::3    2085823.529412                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 3994140.589559                       # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency  40066.765579                       # average overall mshr miss latency
system.l2c.demand_hits::0                         240                       # number of demand (read+write) hits
system.l2c.demand_hits::1                         447                       # number of demand (read+write) hits
system.l2c.demand_hits::2                         372                       # number of demand (read+write) hits
system.l2c.demand_hits::3                         451                       # number of demand (read+write) hits
system.l2c.demand_hits::total                    1510                       # number of demand (read+write) hits
system.l2c.demand_miss_latency               35459000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate::0               0.693487                       # miss rate for demand accesses
system.l2c.demand_miss_rate::1               0.050955                       # miss rate for demand accesses
system.l2c.demand_miss_rate::2               0.206823                       # miss rate for demand accesses
system.l2c.demand_miss_rate::3               0.036325                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.987590                       # miss rate for demand accesses
system.l2c.demand_misses::0                       543                       # number of demand (read+write) misses
system.l2c.demand_misses::1                        24                       # number of demand (read+write) misses
system.l2c.demand_misses::2                        97                       # number of demand (read+write) misses
system.l2c.demand_misses::3                        17                       # number of demand (read+write) misses
system.l2c.demand_misses::total                   681                       # number of demand (read+write) misses
system.l2c.demand_mshr_hits                         7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency          27005000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate::0          0.860792                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1          1.430998                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::2          1.437100                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::3          1.440171                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      5.169061                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses                     674                       # number of demand (read+write) MSHR misses
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.l2c.occ_%::0                          0.005563                       # Average percentage of cache occupancy
system.l2c.occ_%::1                          0.000142                       # Average percentage of cache occupancy
system.l2c.occ_%::2                          0.000963                       # Average percentage of cache occupancy
system.l2c.occ_%::3                          0.000050                       # Average percentage of cache occupancy
system.l2c.occ_%::4                          0.000078                       # Average percentage of cache occupancy
system.l2c.occ_blocks::0                   364.605872                       # Average occupied blocks per context
system.l2c.occ_blocks::1                     9.278582                       # Average occupied blocks per context
system.l2c.occ_blocks::2                    63.097749                       # Average occupied blocks per context
system.l2c.occ_blocks::3                     3.264789                       # Average occupied blocks per context
system.l2c.occ_blocks::4                     5.109725                       # Average occupied blocks per context
system.l2c.overall_accesses::0                    783                       # number of overall (read+write) accesses
system.l2c.overall_accesses::1                    471                       # number of overall (read+write) accesses
system.l2c.overall_accesses::2                    469                       # number of overall (read+write) accesses
system.l2c.overall_accesses::3                    468                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total               2191                       # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency::0   65302.025783                       # average overall miss latency
system.l2c.overall_avg_miss_latency::1   1477458.333333                       # average overall miss latency
system.l2c.overall_avg_miss_latency::2   365556.701031                       # average overall miss latency
system.l2c.overall_avg_miss_latency::3   2085823.529412                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 3994140.589559                       # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency 40066.765579                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.l2c.overall_hits::0                        240                       # number of overall hits
system.l2c.overall_hits::1                        447                       # number of overall hits
system.l2c.overall_hits::2                        372                       # number of overall hits
system.l2c.overall_hits::3                        451                       # number of overall hits
system.l2c.overall_hits::total                   1510                       # number of overall hits
system.l2c.overall_miss_latency              35459000                       # number of overall miss cycles
system.l2c.overall_miss_rate::0              0.693487                       # miss rate for overall accesses
system.l2c.overall_miss_rate::1              0.050955                       # miss rate for overall accesses
system.l2c.overall_miss_rate::2              0.206823                       # miss rate for overall accesses
system.l2c.overall_miss_rate::3              0.036325                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.987590                       # miss rate for overall accesses
system.l2c.overall_misses::0                      543                       # number of overall misses
system.l2c.overall_misses::1                       24                       # number of overall misses
system.l2c.overall_misses::2                       97                       # number of overall misses
system.l2c.overall_misses::3                       17                       # number of overall misses
system.l2c.overall_misses::total                  681                       # number of overall misses
system.l2c.overall_mshr_hits                        7                       # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency         27005000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate::0         0.860792                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1         1.430998                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::2         1.437100                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::3         1.440171                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     5.169061                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses                    674                       # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.l2c.replacements                             0                       # number of replacements
system.l2c.sampled_refs                           545                       # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
system.l2c.tagsinuse                       445.356717                       # Cycle average of tags in use
system.l2c.total_refs                            1507                       # Total number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.writebacks                               0                       # number of writebacks

---------- End Simulation Statistics   ----------