blob: 68fb0ebc9806ee6297c8db2e6305b14a4d327210 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
|
---------- Begin Simulation Statistics ----------
host_inst_rate 52624 # Simulator instruction rate (inst/s)
host_mem_usage 204896 # Number of bytes of host memory used
host_seconds 8.25 # Real time elapsed on the host
host_tick_rate 26298944 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 434213 # Number of instructions simulated
sim_seconds 0.000217 # Number of seconds simulated
sim_ticks 217002500 # Number of ticks simulated
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.BTBHits 44089 # Number of BTB hits
system.cpu0.BPredUnit.BTBLookups 68672 # Number of BTB lookups
system.cpu0.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu0.BPredUnit.condIncorrect 42322 # Number of conditional branches incorrect
system.cpu0.BPredUnit.condPredicted 70853 # Number of conditional branches predicted
system.cpu0.BPredUnit.lookups 70853 # Number of BP lookups
system.cpu0.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu0.commit.COM:branches 23275 # Number of branches committed
system.cpu0.commit.COM:bw_lim_events 181 # number cycles where commit BW limit reached
system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu0.commit.COM:committed_per_cycle::samples 371561 # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::mean 0.368389 # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::stdev 0.674594 # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::0 264099 71.08% 71.08% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::1 83154 22.38% 93.46% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::2 22390 6.03% 99.48% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::3 687 0.18% 99.67% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::4 334 0.09% 99.76% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::5 230 0.06% 99.82% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::6 452 0.12% 99.94% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::7 34 0.01% 99.95% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::8 181 0.05% 100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::total 371561 # Number of insts commited each cycle
system.cpu0.commit.COM:count 136879 # Number of instructions committed
system.cpu0.commit.COM:loads 41762 # Number of loads committed
system.cpu0.commit.COM:membars 84 # Number of memory barriers committed
system.cpu0.commit.COM:refs 63149 # Number of memory references committed
system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.branchMispredicts 42322 # The number of times a branch was mispredicted
system.cpu0.commit.commitCommittedInsts 136879 # The number of committed instructions
system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.commitSquashedInsts 179861 # The number of squashed insts skipped by commit
system.cpu0.committedInsts 116789 # Number of Instructions Simulated
system.cpu0.committedInsts_total 116789 # Number of Instructions Simulated
system.cpu0.cpi 3.716155 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 3.716155 # CPI: Total CPI of All Threads
system.cpu0.dcache.ReadReq_accesses 24665 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_avg_miss_latency 30305.031447 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 24070.175439 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_hits 24347 # number of ReadReq hits
system.cpu0.dcache.ReadReq_miss_latency 9637000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_rate 0.012893 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_misses 318 # number of ReadReq misses
system.cpu0.dcache.ReadReq_mshr_hits 90 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_miss_latency 5488000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate 0.009244 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses
system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_avg_miss_latency 15653.846154 # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 12653.846154 # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_hits 16 # number of SwapReq hits
system.cpu0.dcache.SwapReq_miss_latency 407000 # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_rate 0.619048 # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_misses 26 # number of SwapReq misses
system.cpu0.dcache.SwapReq_mshr_miss_latency 329000 # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_rate 0.619048 # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_misses 26 # number of SwapReq MSHR misses
system.cpu0.dcache.WriteReq_accesses 21345 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_avg_miss_latency 45805.892548 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 38962.500000 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_hits 20768 # number of WriteReq hits
system.cpu0.dcache.WriteReq_miss_latency 26430000 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_rate 0.027032 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_misses 577 # number of WriteReq misses
system.cpu0.dcache.WriteReq_mshr_hits 377 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_miss_latency 7792500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_rate 0.009370 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_misses 200 # number of WriteReq MSHR misses
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 22000 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.dcache.avg_refs 162.931818 # Average number of references to valid blocks.
system.cpu0.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_mshrs 66000 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.demand_accesses 46010 # number of demand (read+write) accesses
system.cpu0.dcache.demand_avg_miss_latency 40298.324022 # average overall miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency 31029.205607 # average overall mshr miss latency
system.cpu0.dcache.demand_hits 45115 # number of demand (read+write) hits
system.cpu0.dcache.demand_miss_latency 36067000 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_rate 0.019452 # miss rate for demand accesses
system.cpu0.dcache.demand_misses 895 # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits 467 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_miss_latency 13280500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_rate 0.009302 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_misses 428 # number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.occ_%::0 0.284939 # Average percentage of cache occupancy
system.cpu0.dcache.occ_%::1 -0.008000 # Average percentage of cache occupancy
system.cpu0.dcache.occ_blocks::0 145.888773 # Average occupied blocks per context
system.cpu0.dcache.occ_blocks::1 -4.096255 # Average occupied blocks per context
system.cpu0.dcache.overall_accesses 46010 # number of overall (read+write) accesses
system.cpu0.dcache.overall_avg_miss_latency 40298.324022 # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency 31029.205607 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu0.dcache.overall_hits 45115 # number of overall hits
system.cpu0.dcache.overall_miss_latency 36067000 # number of overall miss cycles
system.cpu0.dcache.overall_miss_rate 0.019452 # miss rate for overall accesses
system.cpu0.dcache.overall_misses 895 # number of overall misses
system.cpu0.dcache.overall_mshr_hits 467 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_miss_latency 13280500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_rate 0.009302 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_misses 428 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu0.dcache.replacements 10 # number of replacements
system.cpu0.dcache.sampled_refs 176 # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu0.dcache.tagsinuse 141.792519 # Cycle average of tags in use
system.cpu0.dcache.total_refs 28676 # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.writebacks 6 # number of writebacks
system.cpu0.decode.DECODE:BlockedCycles 52836 # Number of cycles decode is blocked
system.cpu0.decode.DECODE:DecodedInsts 451840 # Number of instructions handled by decode
system.cpu0.decode.DECODE:IdleCycles 164219 # Number of cycles decode is idle
system.cpu0.decode.DECODE:RunCycles 154431 # Number of cycles decode is running
system.cpu0.decode.DECODE:SquashCycles 44292 # Number of cycles decode is squashing
system.cpu0.decode.DECODE:UnblockCycles 75 # Number of cycles decode is unblocking
system.cpu0.fetch.Branches 70853 # Number of branches that fetch encountered
system.cpu0.fetch.CacheLines 87025 # Number of cache lines fetched
system.cpu0.fetch.Cycles 242792 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.IcacheSquashes 20665 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.Insts 457882 # Number of instructions fetch has processed
system.cpu0.fetch.SquashCycles 42477 # Number of cycles fetch has spent squashing
system.cpu0.fetch.branchRate 0.163254 # Number of branch fetches per cycle
system.cpu0.fetch.icacheStallCycles 87025 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.predictedBranches 44089 # Number of branches that fetch has predicted taken
system.cpu0.fetch.rate 1.055013 # Number of inst fetches per cycle
system.cpu0.fetch.rateDist::samples 415853 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 1.101067 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.125993 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 260123 62.55% 62.55% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 86799 20.87% 83.42% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 1004 0.24% 83.67% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 21052 5.06% 88.73% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 1074 0.26% 88.99% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 20905 5.03% 94.01% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 680 0.16% 94.18% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 710 0.17% 94.35% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 23506 5.65% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 415853 # Number of instructions fetched each cycle (Total)
system.cpu0.icache.ReadReq_accesses 87025 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_avg_miss_latency 37067.241379 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency 35094.029851 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_hits 86155 # number of ReadReq hits
system.cpu0.icache.ReadReq_miss_latency 32248500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_rate 0.009997 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_misses 870 # number of ReadReq misses
system.cpu0.icache.ReadReq_mshr_hits 200 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_miss_latency 23513000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate 0.007699 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_misses 670 # number of ReadReq MSHR misses
system.cpu0.icache.avg_blocked_cycles::no_mshrs 10250 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.icache.avg_refs 128.781764 # Average number of references to valid blocks.
system.cpu0.icache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_mshrs 20500 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.demand_accesses 87025 # number of demand (read+write) accesses
system.cpu0.icache.demand_avg_miss_latency 37067.241379 # average overall miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency 35094.029851 # average overall mshr miss latency
system.cpu0.icache.demand_hits 86155 # number of demand (read+write) hits
system.cpu0.icache.demand_miss_latency 32248500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_rate 0.009997 # miss rate for demand accesses
system.cpu0.icache.demand_misses 870 # number of demand (read+write) misses
system.cpu0.icache.demand_mshr_hits 200 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_miss_latency 23513000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_rate 0.007699 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_misses 670 # number of demand (read+write) MSHR misses
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.occ_%::0 0.526442 # Average percentage of cache occupancy
system.cpu0.icache.occ_blocks::0 269.538121 # Average occupied blocks per context
system.cpu0.icache.overall_accesses 87025 # number of overall (read+write) accesses
system.cpu0.icache.overall_avg_miss_latency 37067.241379 # average overall miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency 35094.029851 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu0.icache.overall_hits 86155 # number of overall hits
system.cpu0.icache.overall_miss_latency 32248500 # number of overall miss cycles
system.cpu0.icache.overall_miss_rate 0.009997 # miss rate for overall accesses
system.cpu0.icache.overall_misses 870 # number of overall misses
system.cpu0.icache.overall_mshr_hits 200 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_miss_latency 23513000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_rate 0.007699 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_misses 670 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu0.icache.replacements 363 # number of replacements
system.cpu0.icache.sampled_refs 669 # Sample count of references to valid blocks.
system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu0.icache.tagsinuse 269.538121 # Cycle average of tags in use
system.cpu0.icache.total_refs 86155 # Total number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.icache.writebacks 0 # number of writebacks
system.cpu0.idleCycles 18153 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.iew.EXEC:branches 44503 # Number of branches executed
system.cpu0.iew.EXEC:nop 59775 # number of nop insts executed
system.cpu0.iew.EXEC:rate 0.434987 # Inst execution rate
system.cpu0.iew.EXEC:refs 66647 # number of memory reference insts executed
system.cpu0.iew.EXEC:stores 22312 # Number of stores executed
system.cpu0.iew.EXEC:swp 0 # number of swp insts executed
system.cpu0.iew.WB:consumers 95172 # num instructions consuming a value
system.cpu0.iew.WB:count 187212 # cumulative count of insts written-back
system.cpu0.iew.WB:fanout 0.972912 # average fanout of values written-back
system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.iew.WB:producers 92594 # num instructions producing a value
system.cpu0.iew.WB:rate 0.431358 # insts written-back per cycle
system.cpu0.iew.WB:sent 187507 # cumulative count of insts sent to commit
system.cpu0.iew.branchMispredicts 42628 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewBlockCycles 24 # Number of cycles IEW is blocking
system.cpu0.iew.iewDispLoadInsts 45739 # Number of dispatched load instructions
system.cpu0.iew.iewDispNonSpecInsts 20652 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewDispSquashedInsts 2935 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispStoreInsts 43021 # Number of dispatched store instructions
system.cpu0.iew.iewDispatchedInsts 316777 # Number of instructions dispatched to IQ
system.cpu0.iew.iewExecLoadInsts 44335 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 42979 # Number of squashed instructions skipped in execute
system.cpu0.iew.iewExecutedInsts 188787 # Number of executed instructions
system.cpu0.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.iewSquashCycles 44292 # Number of cycles IEW is squashing
system.cpu0.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking
system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread.0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.lsq.thread.0.forwLoads 19578 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread.0.memOrderViolation 197 # Number of memory ordering violations
system.cpu0.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread.0.squashedLoads 3977 # Number of loads squashed
system.cpu0.iew.lsq.thread.0.squashedStores 21634 # Number of stores squashed
system.cpu0.iew.memOrderViolationEvents 197 # Number of memory order violations
system.cpu0.iew.predictedNotTakenIncorrect 962 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.predictedTakenIncorrect 41666 # Number of branches that were predicted taken incorrectly
system.cpu0.ipc 0.269095 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.269095 # IPC: Total IPC of All Threads
system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntAlu 164239 70.86% 70.86% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.86% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.86% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.86% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.86% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.86% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.86% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.86% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.86% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::MemRead 44972 19.40% 90.27% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::MemWrite 22555 9.73% 100.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::total 231766 # Type of FU issued
system.cpu0.iq.ISSUE:fu_busy_cnt 133 # FU busy when requested
system.cpu0.iq.ISSUE:fu_busy_rate 0.000574 # FU busy rate (busy events/executed inst)
system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IntAlu 38 28.57% 28.57% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 28.57% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 28.57% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 28.57% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 28.57% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 28.57% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 28.57% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 28.57% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 28.57% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::MemRead 27 20.30% 48.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::MemWrite 68 51.13% 100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:issued_per_cycle::samples 415853 # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.557327 # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::stdev 0.948090 # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::0 281858 67.78% 67.78% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::1 66212 15.92% 83.70% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::2 42876 10.31% 94.01% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::3 21783 5.24% 99.25% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::4 1770 0.43% 99.67% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::5 926 0.22% 99.90% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::6 279 0.07% 99.96% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::7 123 0.03% 99.99% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::8 26 0.01% 100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::total 415853 # Number of insts issued each cycle
system.cpu0.iq.ISSUE:rate 0.534016 # Inst issue rate
system.cpu0.iq.iqInstsAdded 236227 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqInstsIssued 231766 # Number of instructions issued
system.cpu0.iq.iqNonSpecInstsAdded 20775 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqSquashedInstsExamined 98225 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedNonSpecRemoved 20216 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.iqSquashedOperandsExamined 15756 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.memDep0.conflictingLoads 19721 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 107 # Number of conflicting stores.
system.cpu0.memDep0.insertedLoads 45739 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 43021 # Number of stores inserted to the mem dependence unit.
system.cpu0.numCycles 434006 # number of cpu cycles simulated
system.cpu0.rename.RENAME:BlockCycles 32 # Number of cycles rename is blocking
system.cpu0.rename.RENAME:CommittedMaps 96356 # Number of HB maps that are committed
system.cpu0.rename.RENAME:IdleCycles 185616 # Number of cycles rename is idle
system.cpu0.rename.RENAME:LSQFullEvents 5 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RENAME:RenameLookups 505980 # Number of register rename lookups that rename has made
system.cpu0.rename.RENAME:RenamedInsts 324358 # Number of instructions processed by rename
system.cpu0.rename.RENAME:RenamedOperands 242034 # Number of destination operands rename has renamed
system.cpu0.rename.RENAME:RunCycles 133139 # Number of cycles rename is running
system.cpu0.rename.RENAME:SquashCycles 44292 # Number of cycles rename is squashing
system.cpu0.rename.RENAME:UnblockCycles 355 # Number of cycles rename is unblocking
system.cpu0.rename.RENAME:UndoneMaps 145678 # Number of HB maps that are undone due to squashing
system.cpu0.rename.RENAME:serializeStallCycles 52419 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RENAME:serializingInsts 20781 # count of serializing insts renamed
system.cpu0.rename.RENAME:skidInsts 83231 # count of insts added to the skid buffer
system.cpu0.rename.RENAME:tempSerializingInsts 20770 # count of temporary serializing insts renamed
system.cpu0.timesIdled 339 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.workload.PROG:num_syscalls 89 # Number of system calls
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.BTBHits 53713 # Number of BTB hits
system.cpu1.BPredUnit.BTBLookups 65870 # Number of BTB lookups
system.cpu1.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu1.BPredUnit.condIncorrect 29792 # Number of conditional branches incorrect
system.cpu1.BPredUnit.condPredicted 83669 # Number of conditional branches predicted
system.cpu1.BPredUnit.lookups 83669 # Number of BP lookups
system.cpu1.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu1.commit.COM:branches 25470 # Number of branches committed
system.cpu1.commit.COM:bw_lim_events 577 # number cycles where commit BW limit reached
system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu1.commit.COM:committed_per_cycle::samples 350132 # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::mean 0.363609 # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::stdev 0.831936 # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::0 266836 76.21% 76.21% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::1 54270 15.50% 91.71% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::2 24066 6.87% 98.58% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::3 1288 0.37% 98.95% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::4 810 0.23% 99.18% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::5 561 0.16% 99.34% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::6 1684 0.48% 99.82% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::7 40 0.01% 99.84% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::8 577 0.16% 100.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::total 350132 # Number of insts commited each cycle
system.cpu1.commit.COM:count 127311 # Number of instructions committed
system.cpu1.commit.COM:loads 29520 # Number of loads committed
system.cpu1.commit.COM:membars 8970 # Number of memory barriers committed
system.cpu1.commit.COM:refs 40059 # Number of memory references committed
system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.branchMispredicts 29792 # The number of times a branch was mispredicted
system.cpu1.commit.commitCommittedInsts 127311 # The number of committed instructions
system.cpu1.commit.commitNonSpecStalls 9688 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.commitSquashedInsts 134332 # The number of squashed insts skipped by commit
system.cpu1.committedInsts 102085 # Number of Instructions Simulated
system.cpu1.committedInsts_total 102085 # Number of Instructions Simulated
system.cpu1.cpi 3.876926 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 3.876926 # CPI: Total CPI of All Threads
system.cpu1.dcache.ReadReq_accesses 28866 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_avg_miss_latency 18882.352941 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 16694.285714 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_hits 28662 # number of ReadReq hits
system.cpu1.dcache.ReadReq_miss_latency 3852000 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_rate 0.007067 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_misses 204 # number of ReadReq misses
system.cpu1.dcache.ReadReq_mshr_hits 29 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_miss_latency 2921500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate 0.006062 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_misses 175 # number of ReadReq MSHR misses
system.cpu1.dcache.SwapReq_accesses 72 # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_avg_miss_latency 22155.172414 # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 24152.173913 # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_hits 14 # number of SwapReq hits
system.cpu1.dcache.SwapReq_miss_latency 1285000 # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_rate 0.805556 # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_misses 58 # number of SwapReq misses
system.cpu1.dcache.SwapReq_mshr_hits 12 # number of SwapReq MSHR hits
system.cpu1.dcache.SwapReq_mshr_miss_latency 1111000 # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_rate 0.638889 # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_misses 46 # number of SwapReq MSHR misses
system.cpu1.dcache.WriteReq_accesses 10467 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_avg_miss_latency 23593.023256 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 15414.414414 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_hits 10338 # number of WriteReq hits
system.cpu1.dcache.WriteReq_miss_latency 3043500 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_rate 0.012324 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_misses 129 # number of WriteReq misses
system.cpu1.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_miss_latency 1711000 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_rate 0.010605 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_misses 111 # number of WriteReq MSHR misses
system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.dcache.avg_refs 701.333333 # Average number of references to valid blocks.
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.demand_accesses 39333 # number of demand (read+write) accesses
system.cpu1.dcache.demand_avg_miss_latency 20707.207207 # average overall miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency 16197.552448 # average overall mshr miss latency
system.cpu1.dcache.demand_hits 39000 # number of demand (read+write) hits
system.cpu1.dcache.demand_miss_latency 6895500 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_rate 0.008466 # miss rate for demand accesses
system.cpu1.dcache.demand_misses 333 # number of demand (read+write) misses
system.cpu1.dcache.demand_mshr_hits 47 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_miss_latency 4632500 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_rate 0.007271 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_misses 286 # number of demand (read+write) MSHR misses
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.occ_%::0 0.053188 # Average percentage of cache occupancy
system.cpu1.dcache.occ_blocks::0 27.232391 # Average occupied blocks per context
system.cpu1.dcache.overall_accesses 39333 # number of overall (read+write) accesses
system.cpu1.dcache.overall_avg_miss_latency 20707.207207 # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency 16197.552448 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu1.dcache.overall_hits 39000 # number of overall hits
system.cpu1.dcache.overall_miss_latency 6895500 # number of overall miss cycles
system.cpu1.dcache.overall_miss_rate 0.008466 # miss rate for overall accesses
system.cpu1.dcache.overall_misses 333 # number of overall misses
system.cpu1.dcache.overall_mshr_hits 47 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_miss_latency 4632500 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_rate 0.007271 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_misses 286 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu1.dcache.replacements 2 # number of replacements
system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks.
system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu1.dcache.tagsinuse 27.232391 # Cycle average of tags in use
system.cpu1.dcache.total_refs 21040 # Total number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.writebacks 1 # number of writebacks
system.cpu1.decode.DECODE:BlockedCycles 30059 # Number of cycles decode is blocked
system.cpu1.decode.DECODE:DecodedInsts 353088 # Number of instructions handled by decode
system.cpu1.decode.DECODE:IdleCycles 174967 # Number of cycles decode is idle
system.cpu1.decode.DECODE:RunCycles 144955 # Number of cycles decode is running
system.cpu1.decode.DECODE:SquashCycles 33628 # Number of cycles decode is squashing
system.cpu1.decode.DECODE:UnblockCycles 151 # Number of cycles decode is unblocking
system.cpu1.fetch.Branches 83669 # Number of branches that fetch encountered
system.cpu1.fetch.CacheLines 82467 # Number of cache lines fetched
system.cpu1.fetch.Cycles 239936 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.IcacheSquashes 9132 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.Insts 410532 # Number of instructions fetch has processed
system.cpu1.fetch.SquashCycles 29946 # Number of cycles fetch has spent squashing
system.cpu1.fetch.branchRate 0.211405 # Number of branch fetches per cycle
system.cpu1.fetch.icacheStallCycles 82467 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.predictedBranches 53713 # Number of branches that fetch has predicted taken
system.cpu1.fetch.rate 1.037284 # Number of inst fetches per cycle
system.cpu1.fetch.rateDist::samples 392867 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 1.044964 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 1.945559 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 235421 59.92% 59.92% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 84908 21.61% 81.54% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 20175 5.14% 86.67% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 13313 3.39% 90.06% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 2697 0.69% 90.75% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 17066 4.34% 95.09% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 1329 0.34% 95.43% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 2421 0.62% 96.05% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 15537 3.95% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total 392867 # Number of instructions fetched each cycle (Total)
system.cpu1.icache.ReadReq_accesses 82467 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_avg_miss_latency 14489.768076 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11935.534591 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_hits 81734 # number of ReadReq hits
system.cpu1.icache.ReadReq_miss_latency 10621000 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_rate 0.008888 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_misses 733 # number of ReadReq misses
system.cpu1.icache.ReadReq_mshr_hits 97 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_miss_latency 7591000 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate 0.007712 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_misses 636 # number of ReadReq MSHR misses
system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.icache.avg_refs 128.512579 # Average number of references to valid blocks.
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.demand_accesses 82467 # number of demand (read+write) accesses
system.cpu1.icache.demand_avg_miss_latency 14489.768076 # average overall miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency 11935.534591 # average overall mshr miss latency
system.cpu1.icache.demand_hits 81734 # number of demand (read+write) hits
system.cpu1.icache.demand_miss_latency 10621000 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_rate 0.008888 # miss rate for demand accesses
system.cpu1.icache.demand_misses 733 # number of demand (read+write) misses
system.cpu1.icache.demand_mshr_hits 97 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_miss_latency 7591000 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_rate 0.007712 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_misses 636 # number of demand (read+write) MSHR misses
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.occ_%::0 0.182938 # Average percentage of cache occupancy
system.cpu1.icache.occ_blocks::0 93.664377 # Average occupied blocks per context
system.cpu1.icache.overall_accesses 82467 # number of overall (read+write) accesses
system.cpu1.icache.overall_avg_miss_latency 14489.768076 # average overall miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency 11935.534591 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu1.icache.overall_hits 81734 # number of overall hits
system.cpu1.icache.overall_miss_latency 10621000 # number of overall miss cycles
system.cpu1.icache.overall_miss_rate 0.008888 # miss rate for overall accesses
system.cpu1.icache.overall_misses 733 # number of overall misses
system.cpu1.icache.overall_mshr_hits 97 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_miss_latency 7591000 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_rate 0.007712 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_misses 636 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu1.icache.replacements 524 # number of replacements
system.cpu1.icache.sampled_refs 636 # Sample count of references to valid blocks.
system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu1.icache.tagsinuse 93.664377 # Cycle average of tags in use
system.cpu1.icache.total_refs 81734 # Total number of references to valid blocks.
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.icache.writebacks 0 # number of writebacks
system.cpu1.idleCycles 2909 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.iew.EXEC:branches 36547 # Number of branches executed
system.cpu1.iew.EXEC:nop 47873 # number of nop insts executed
system.cpu1.iew.EXEC:rate 0.410224 # Inst execution rate
system.cpu1.iew.EXEC:refs 47615 # number of memory reference insts executed
system.cpu1.iew.EXEC:stores 12164 # Number of stores executed
system.cpu1.iew.EXEC:swp 0 # number of swp insts executed
system.cpu1.iew.WB:consumers 78764 # num instructions consuming a value
system.cpu1.iew.WB:count 158732 # cumulative count of insts written-back
system.cpu1.iew.WB:fanout 0.929676 # average fanout of values written-back
system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.iew.WB:producers 73225 # num instructions producing a value
system.cpu1.iew.WB:rate 0.401065 # insts written-back per cycle
system.cpu1.iew.WB:sent 158983 # cumulative count of insts sent to commit
system.cpu1.iew.branchMispredicts 30400 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
system.cpu1.iew.iewDispLoadInsts 39543 # Number of dispatched load instructions
system.cpu1.iew.iewDispNonSpecInsts 8501 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewDispSquashedInsts 3508 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispStoreInsts 20654 # Number of dispatched store instructions
system.cpu1.iew.iewDispatchedInsts 261662 # Number of instructions dispatched to IQ
system.cpu1.iew.iewExecLoadInsts 35451 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 33572 # Number of squashed instructions skipped in execute
system.cpu1.iew.iewExecutedInsts 162357 # Number of executed instructions
system.cpu1.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.iewSquashCycles 33628 # Number of cycles IEW is squashing
system.cpu1.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.lsq.thread.0.forwLoads 6568 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread.0.memOrderViolation 694 # Number of memory ordering violations
system.cpu1.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread.0.squashedLoads 10023 # Number of loads squashed
system.cpu1.iew.lsq.thread.0.squashedStores 10115 # Number of stores squashed
system.cpu1.iew.memOrderViolationEvents 694 # Number of memory order violations
system.cpu1.iew.predictedNotTakenIncorrect 1033 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.predictedTakenIncorrect 29367 # Number of branches that were predicted taken incorrectly
system.cpu1.ipc 0.257936 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.257936 # IPC: Total IPC of All Threads
system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntAlu 137441 70.15% 70.15% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.15% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.15% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.15% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.15% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.15% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.15% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.15% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.15% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::MemRead 45623 23.29% 93.43% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::MemWrite 12865 6.57% 100.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::total 195929 # Type of FU issued
system.cpu1.iq.ISSUE:fu_busy_cnt 186 # FU busy when requested
system.cpu1.iq.ISSUE:fu_busy_rate 0.000949 # FU busy rate (busy events/executed inst)
system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IntAlu 24 12.90% 12.90% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 12.90% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 12.90% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 12.90% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.90% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.90% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.90% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.90% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.90% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::MemRead 17 9.14% 22.04% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::MemWrite 145 77.96% 100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:issued_per_cycle::samples 392867 # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.498716 # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::stdev 0.955880 # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::0 276221 70.31% 70.31% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::1 71375 18.17% 88.48% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::2 23368 5.95% 94.42% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::3 13587 3.46% 97.88% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::4 5437 1.38% 99.27% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::5 2194 0.56% 99.83% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::6 490 0.12% 99.95% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::7 161 0.04% 99.99% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::8 34 0.01% 100.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::total 392867 # Number of insts issued each cycle
system.cpu1.iq.ISSUE:rate 0.495050 # Inst issue rate
system.cpu1.iq.iqInstsAdded 196258 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqInstsIssued 195929 # Number of instructions issued
system.cpu1.iq.iqNonSpecInstsAdded 17531 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqSquashedInstsExamined 74909 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedInstsIssued 4 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedNonSpecRemoved 7843 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.iqSquashedOperandsExamined 33478 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.memDep0.conflictingLoads 6760 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 87 # Number of conflicting stores.
system.cpu1.memDep0.insertedLoads 39543 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 20654 # Number of stores inserted to the mem dependence unit.
system.cpu1.numCycles 395776 # number of cpu cycles simulated
system.cpu1.rename.RENAME:CommittedMaps 85194 # Number of HB maps that are committed
system.cpu1.rename.RENAME:IdleCycles 186916 # Number of cycles rename is idle
system.cpu1.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RENAME:RenameLookups 447878 # Number of register rename lookups that rename has made
system.cpu1.rename.RENAME:RenamedInsts 290237 # Number of instructions processed by rename
system.cpu1.rename.RENAME:RenamedOperands 204758 # Number of destination operands rename has renamed
system.cpu1.rename.RENAME:RunCycles 133245 # Number of cycles rename is running
system.cpu1.rename.RENAME:SquashCycles 33628 # Number of cycles rename is squashing
system.cpu1.rename.RENAME:UnblockCycles 630 # Number of cycles rename is unblocking
system.cpu1.rename.RENAME:UndoneMaps 119564 # Number of HB maps that are undone due to squashing
system.cpu1.rename.RENAME:serializeStallCycles 29341 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RENAME:serializingInsts 8772 # count of serializing insts renamed
system.cpu1.rename.RENAME:skidInsts 33179 # count of insts added to the skid buffer
system.cpu1.rename.RENAME:tempSerializingInsts 8900 # count of temporary serializing insts renamed
system.cpu1.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.BPredUnit.BTBHits 52073 # Number of BTB hits
system.cpu2.BPredUnit.BTBLookups 66680 # Number of BTB lookups
system.cpu2.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu2.BPredUnit.condIncorrect 30422 # Number of conditional branches incorrect
system.cpu2.BPredUnit.condPredicted 81408 # Number of conditional branches predicted
system.cpu2.BPredUnit.lookups 81408 # Number of BP lookups
system.cpu2.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu2.commit.COM:branches 25190 # Number of branches committed
system.cpu2.commit.COM:bw_lim_events 578 # number cycles where commit BW limit reached
system.cpu2.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu2.commit.COM:committed_per_cycle::samples 347008 # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::mean 0.368821 # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::stdev 0.833965 # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::0 262750 75.72% 75.72% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::1 55494 15.99% 91.71% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::2 23803 6.86% 98.57% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::3 1293 0.37% 98.94% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::4 820 0.24% 99.18% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::5 559 0.16% 99.34% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::6 1671 0.48% 99.82% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::7 40 0.01% 99.83% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::8 578 0.17% 100.00% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::total 347008 # Number of insts commited each cycle
system.cpu2.commit.COM:count 127984 # Number of instructions committed
system.cpu2.commit.COM:loads 30137 # Number of loads committed
system.cpu2.commit.COM:membars 7796 # Number of memory barriers committed
system.cpu2.commit.COM:refs 41570 # Number of memory references committed
system.cpu2.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu2.commit.branchMispredicts 30422 # The number of times a branch was mispredicted
system.cpu2.commit.commitCommittedInsts 127984 # The number of committed instructions
system.cpu2.commit.commitNonSpecStalls 8513 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.commitSquashedInsts 138030 # The number of squashed insts skipped by commit
system.cpu2.committedInsts 104211 # Number of Instructions Simulated
system.cpu2.committedInsts_total 104211 # Number of Instructions Simulated
system.cpu2.cpi 3.794734 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 3.794734 # CPI: Total CPI of All Threads
system.cpu2.dcache.ReadReq_accesses 28582 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_avg_miss_latency 19289.473684 # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 17373.563218 # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_hits 28373 # number of ReadReq hits
system.cpu2.dcache.ReadReq_miss_latency 4031500 # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_rate 0.007312 # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_misses 209 # number of ReadReq misses
system.cpu2.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits
system.cpu2.dcache.ReadReq_mshr_miss_latency 3023000 # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate 0.006088 # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_misses 174 # number of ReadReq MSHR misses
system.cpu2.dcache.SwapReq_accesses 71 # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_avg_miss_latency 21973.684211 # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 23510.869565 # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_hits 14 # number of SwapReq hits
system.cpu2.dcache.SwapReq_miss_latency 1252500 # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_rate 0.802817 # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_misses 57 # number of SwapReq misses
system.cpu2.dcache.SwapReq_mshr_hits 11 # number of SwapReq MSHR hits
system.cpu2.dcache.SwapReq_mshr_miss_latency 1081500 # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_rate 0.647887 # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_misses 46 # number of SwapReq MSHR misses
system.cpu2.dcache.WriteReq_accesses 11362 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_avg_miss_latency 24003.906250 # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 15831.818182 # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_hits 11234 # number of WriteReq hits
system.cpu2.dcache.WriteReq_miss_latency 3072500 # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_rate 0.011266 # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_misses 128 # number of WriteReq misses
system.cpu2.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_miss_latency 1741500 # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_rate 0.009681 # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_misses 110 # number of WriteReq MSHR misses
system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu2.dcache.avg_refs 708.483871 # Average number of references to valid blocks.
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
system.cpu2.dcache.demand_accesses 39944 # number of demand (read+write) accesses
system.cpu2.dcache.demand_avg_miss_latency 21080.118694 # average overall miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency 16776.408451 # average overall mshr miss latency
system.cpu2.dcache.demand_hits 39607 # number of demand (read+write) hits
system.cpu2.dcache.demand_miss_latency 7104000 # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_rate 0.008437 # miss rate for demand accesses
system.cpu2.dcache.demand_misses 337 # number of demand (read+write) misses
system.cpu2.dcache.demand_mshr_hits 53 # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_miss_latency 4764500 # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_rate 0.007110 # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_misses 284 # number of demand (read+write) MSHR misses
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dcache.occ_%::0 0.056939 # Average percentage of cache occupancy
system.cpu2.dcache.occ_blocks::0 29.152957 # Average occupied blocks per context
system.cpu2.dcache.overall_accesses 39944 # number of overall (read+write) accesses
system.cpu2.dcache.overall_avg_miss_latency 21080.118694 # average overall miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency 16776.408451 # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu2.dcache.overall_hits 39607 # number of overall hits
system.cpu2.dcache.overall_miss_latency 7104000 # number of overall miss cycles
system.cpu2.dcache.overall_miss_rate 0.008437 # miss rate for overall accesses
system.cpu2.dcache.overall_misses 337 # number of overall misses
system.cpu2.dcache.overall_mshr_hits 53 # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_miss_latency 4764500 # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_rate 0.007110 # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_misses 284 # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu2.dcache.replacements 2 # number of replacements
system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks.
system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu2.dcache.tagsinuse 29.152957 # Cycle average of tags in use
system.cpu2.dcache.total_refs 21963 # Total number of references to valid blocks.
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.dcache.writebacks 1 # number of writebacks
system.cpu2.decode.DECODE:BlockedCycles 31861 # Number of cycles decode is blocked
system.cpu2.decode.DECODE:DecodedInsts 361505 # Number of instructions handled by decode
system.cpu2.decode.DECODE:IdleCycles 170760 # Number of cycles decode is idle
system.cpu2.decode.DECODE:RunCycles 144226 # Number of cycles decode is running
system.cpu2.decode.DECODE:SquashCycles 34255 # Number of cycles decode is squashing
system.cpu2.decode.DECODE:UnblockCycles 161 # Number of cycles decode is unblocking
system.cpu2.fetch.Branches 81408 # Number of branches that fetch encountered
system.cpu2.fetch.CacheLines 81347 # Number of cache lines fetched
system.cpu2.fetch.Cycles 236913 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.IcacheSquashes 10044 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.Insts 412447 # Number of instructions fetch has processed
system.cpu2.fetch.SquashCycles 30579 # Number of cycles fetch has spent squashing
system.cpu2.fetch.branchRate 0.205860 # Number of branch fetches per cycle
system.cpu2.fetch.icacheStallCycles 81347 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.predictedBranches 52073 # Number of branches that fetch has predicted taken
system.cpu2.fetch.rate 1.042974 # Number of inst fetches per cycle
system.cpu2.fetch.rateDist::samples 390306 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 1.056727 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 1.974128 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0 234764 60.15% 60.15% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 83865 21.49% 81.64% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 17837 4.57% 86.21% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 14411 3.69% 89.90% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 2742 0.70% 90.60% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 16550 4.24% 94.84% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 1358 0.35% 95.19% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 2423 0.62% 95.81% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 16356 4.19% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total 390306 # Number of instructions fetched each cycle (Total)
system.cpu2.icache.ReadReq_accesses 81347 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_avg_miss_latency 18963.235294 # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency 16003.955696 # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_hits 80599 # number of ReadReq hits
system.cpu2.icache.ReadReq_miss_latency 14184500 # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_rate 0.009195 # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_misses 748 # number of ReadReq misses
system.cpu2.icache.ReadReq_mshr_hits 116 # number of ReadReq MSHR hits
system.cpu2.icache.ReadReq_mshr_miss_latency 10114500 # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate 0.007769 # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_misses 632 # number of ReadReq MSHR misses
system.cpu2.icache.avg_blocked_cycles::no_mshrs 32500 # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu2.icache.avg_refs 127.530063 # Average number of references to valid blocks.
system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_mshrs 32500 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.cache_copies 0 # number of cache copies performed
system.cpu2.icache.demand_accesses 81347 # number of demand (read+write) accesses
system.cpu2.icache.demand_avg_miss_latency 18963.235294 # average overall miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency 16003.955696 # average overall mshr miss latency
system.cpu2.icache.demand_hits 80599 # number of demand (read+write) hits
system.cpu2.icache.demand_miss_latency 14184500 # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_rate 0.009195 # miss rate for demand accesses
system.cpu2.icache.demand_misses 748 # number of demand (read+write) misses
system.cpu2.icache.demand_mshr_hits 116 # number of demand (read+write) MSHR hits
system.cpu2.icache.demand_mshr_miss_latency 10114500 # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_rate 0.007769 # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_misses 632 # number of demand (read+write) MSHR misses
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.icache.occ_%::0 0.191179 # Average percentage of cache occupancy
system.cpu2.icache.occ_blocks::0 97.883584 # Average occupied blocks per context
system.cpu2.icache.overall_accesses 81347 # number of overall (read+write) accesses
system.cpu2.icache.overall_avg_miss_latency 18963.235294 # average overall miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency 16003.955696 # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu2.icache.overall_hits 80599 # number of overall hits
system.cpu2.icache.overall_miss_latency 14184500 # number of overall miss cycles
system.cpu2.icache.overall_miss_rate 0.009195 # miss rate for overall accesses
system.cpu2.icache.overall_misses 748 # number of overall misses
system.cpu2.icache.overall_mshr_hits 116 # number of overall MSHR hits
system.cpu2.icache.overall_mshr_miss_latency 10114500 # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_rate 0.007769 # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_misses 632 # number of overall MSHR misses
system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu2.icache.replacements 522 # number of replacements
system.cpu2.icache.sampled_refs 632 # Sample count of references to valid blocks.
system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu2.icache.tagsinuse 97.883584 # Cycle average of tags in use
system.cpu2.icache.total_refs 80599 # Total number of references to valid blocks.
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.icache.writebacks 0 # number of writebacks
system.cpu2.idleCycles 5147 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.iew.EXEC:branches 37149 # Number of branches executed
system.cpu2.iew.EXEC:nop 47058 # number of nop insts executed
system.cpu2.iew.EXEC:rate 0.419532 # Inst execution rate
system.cpu2.iew.EXEC:refs 49104 # number of memory reference insts executed
system.cpu2.iew.EXEC:stores 13043 # Number of stores executed
system.cpu2.iew.EXEC:swp 0 # number of swp insts executed
system.cpu2.iew.WB:consumers 81150 # num instructions consuming a value
system.cpu2.iew.WB:count 162295 # cumulative count of insts written-back
system.cpu2.iew.WB:fanout 0.931855 # average fanout of values written-back
system.cpu2.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu2.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.iew.WB:producers 75620 # num instructions producing a value
system.cpu2.iew.WB:rate 0.410403 # insts written-back per cycle
system.cpu2.iew.WB:sent 162544 # cumulative count of insts sent to commit
system.cpu2.iew.branchMispredicts 31026 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
system.cpu2.iew.iewDispLoadInsts 40176 # Number of dispatched load instructions
system.cpu2.iew.iewDispNonSpecInsts 9384 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewDispSquashedInsts 3614 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispStoreInsts 22433 # Number of dispatched store instructions
system.cpu2.iew.iewDispatchedInsts 266034 # Number of instructions dispatched to IQ
system.cpu2.iew.iewExecLoadInsts 36061 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 34221 # Number of squashed instructions skipped in execute
system.cpu2.iew.iewExecutedInsts 165905 # Number of executed instructions
system.cpu2.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.iewSquashCycles 34255 # Number of cycles IEW is squashing
system.cpu2.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
system.cpu2.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.lsq.thread.0.forwLoads 7459 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread.0.memOrderViolation 698 # Number of memory ordering violations
system.cpu2.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread.0.squashedLoads 10039 # Number of loads squashed
system.cpu2.iew.lsq.thread.0.squashedStores 11000 # Number of stores squashed
system.cpu2.iew.memOrderViolationEvents 698 # Number of memory order violations
system.cpu2.iew.predictedNotTakenIncorrect 1011 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.predictedTakenIncorrect 30015 # Number of branches that were predicted taken incorrectly
system.cpu2.ipc 0.263523 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 0.263523 # IPC: Total IPC of All Threads
system.cpu2.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::IntAlu 141339 70.63% 70.63% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.63% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.63% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.63% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.63% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.63% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.63% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.63% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.63% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::MemRead 45052 22.51% 93.14% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::MemWrite 13735 6.86% 100.00% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::total 200126 # Type of FU issued
system.cpu2.iq.ISSUE:fu_busy_cnt 181 # FU busy when requested
system.cpu2.iq.ISSUE:fu_busy_rate 0.000904 # FU busy rate (busy events/executed inst)
system.cpu2.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::IntAlu 19 10.50% 10.50% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::IntMult 0 0.00% 10.50% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.50% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.50% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.50% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.50% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.50% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.50% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.50% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::MemRead 17 9.39% 19.89% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::MemWrite 145 80.11% 100.00% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.ISSUE:issued_per_cycle::samples 390306 # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::mean 0.512741 # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::stdev 0.969063 # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::0 272942 69.93% 69.93% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::1 69416 17.79% 87.72% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::2 25173 6.45% 94.16% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::3 14490 3.71% 97.88% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::4 5424 1.39% 99.27% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::5 2186 0.56% 99.83% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::6 485 0.12% 99.95% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::7 162 0.04% 99.99% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::8 28 0.01% 100.00% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::total 390306 # Number of insts issued each cycle
system.cpu2.iq.ISSUE:rate 0.506068 # Inst issue rate
system.cpu2.iq.iqInstsAdded 201728 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqInstsIssued 200126 # Number of instructions issued
system.cpu2.iq.iqNonSpecInstsAdded 17248 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqSquashedInstsExamined 77302 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedNonSpecRemoved 8735 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.iqSquashedOperandsExamined 33615 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.memDep0.conflictingLoads 7669 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 92 # Number of conflicting stores.
system.cpu2.memDep0.insertedLoads 40176 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 22433 # Number of stores inserted to the mem dependence unit.
system.cpu2.numCycles 395453 # number of cpu cycles simulated
system.cpu2.rename.RENAME:CommittedMaps 87600 # Number of HB maps that are committed
system.cpu2.rename.RENAME:IdleCycles 183597 # Number of cycles rename is idle
system.cpu2.rename.RENAME:RenameLookups 458439 # Number of register rename lookups that rename has made
system.cpu2.rename.RENAME:RenamedInsts 293451 # Number of instructions processed by rename
system.cpu2.rename.RENAME:RenamedOperands 211386 # Number of destination operands rename has renamed
system.cpu2.rename.RENAME:RunCycles 131636 # Number of cycles rename is running
system.cpu2.rename.RENAME:SquashCycles 34255 # Number of cycles rename is squashing
system.cpu2.rename.RENAME:UnblockCycles 645 # Number of cycles rename is unblocking
system.cpu2.rename.RENAME:UndoneMaps 123786 # Number of HB maps that are undone due to squashing
system.cpu2.rename.RENAME:serializeStallCycles 31130 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RENAME:serializingInsts 9653 # count of serializing insts renamed
system.cpu2.rename.RENAME:skidInsts 36749 # count of insts added to the skid buffer
system.cpu2.rename.RENAME:tempSerializingInsts 9784 # count of temporary serializing insts renamed
system.cpu2.timesIdled 292 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.BPredUnit.BTBHits 48405 # Number of BTB hits
system.cpu3.BPredUnit.BTBLookups 65841 # Number of BTB lookups
system.cpu3.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu3.BPredUnit.condIncorrect 32660 # Number of conditional branches incorrect
system.cpu3.BPredUnit.condPredicted 82266 # Number of conditional branches predicted
system.cpu3.BPredUnit.lookups 82266 # Number of BP lookups
system.cpu3.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu3.commit.COM:branches 25082 # Number of branches committed
system.cpu3.commit.COM:bw_lim_events 576 # number cycles where commit BW limit reached
system.cpu3.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu3.commit.COM:committed_per_cycle::samples 346536 # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::mean 0.381828 # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::stdev 0.836481 # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::0 257870 74.41% 74.41% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::1 60023 17.32% 91.73% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::2 23680 6.83% 98.57% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::3 1288 0.37% 98.94% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::4 802 0.23% 99.17% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::5 567 0.16% 99.33% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::6 1691 0.49% 99.82% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::7 39 0.01% 99.83% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::8 576 0.17% 100.00% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::total 346536 # Number of insts commited each cycle
system.cpu3.commit.COM:count 132317 # Number of instructions committed
system.cpu3.commit.COM:loads 32415 # Number of loads committed
system.cpu3.commit.COM:membars 5314 # Number of memory barriers committed
system.cpu3.commit.COM:refs 46218 # Number of memory references committed
system.cpu3.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu3.commit.branchMispredicts 32660 # The number of times a branch was mispredicted
system.cpu3.commit.commitCommittedInsts 132317 # The number of committed instructions
system.cpu3.commit.commitNonSpecStalls 6025 # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.commitSquashedInsts 152378 # The number of squashed insts skipped by commit
system.cpu3.committedInsts 111128 # Number of Instructions Simulated
system.cpu3.committedInsts_total 111128 # Number of Instructions Simulated
system.cpu3.cpi 3.555675 # CPI: Cycles Per Instruction
system.cpu3.cpi_total 3.555675 # CPI: Total CPI of All Threads
system.cpu3.dcache.ReadReq_accesses 28485 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_avg_miss_latency 16678.947368 # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 14832.258065 # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_hits 28295 # number of ReadReq hits
system.cpu3.dcache.ReadReq_miss_latency 3169000 # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_rate 0.006670 # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_misses 190 # number of ReadReq misses
system.cpu3.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits
system.cpu3.dcache.ReadReq_mshr_miss_latency 2299000 # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate 0.005441 # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_misses 155 # number of ReadReq MSHR misses
system.cpu3.dcache.SwapReq_accesses 65 # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_avg_miss_latency 22773.584906 # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 22782.608696 # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_hits 12 # number of SwapReq hits
system.cpu3.dcache.SwapReq_miss_latency 1207000 # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_rate 0.815385 # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_misses 53 # number of SwapReq misses
system.cpu3.dcache.SwapReq_mshr_hits 7 # number of SwapReq MSHR hits
system.cpu3.dcache.SwapReq_mshr_miss_latency 1048000 # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_rate 0.707692 # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_misses 46 # number of SwapReq MSHR misses
system.cpu3.dcache.WriteReq_accesses 13738 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_avg_miss_latency 22585.271318 # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 14535.714286 # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_hits 13609 # number of WriteReq hits
system.cpu3.dcache.WriteReq_miss_latency 2913500 # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_rate 0.009390 # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_misses 129 # number of WriteReq misses
system.cpu3.dcache.WriteReq_mshr_hits 17 # number of WriteReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_miss_latency 1628000 # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_rate 0.008153 # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_misses 112 # number of WriteReq MSHR misses
system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu3.dcache.avg_refs 810.166667 # Average number of references to valid blocks.
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
system.cpu3.dcache.demand_accesses 42223 # number of demand (read+write) accesses
system.cpu3.dcache.demand_avg_miss_latency 19067.398119 # average overall miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency 14707.865169 # average overall mshr miss latency
system.cpu3.dcache.demand_hits 41904 # number of demand (read+write) hits
system.cpu3.dcache.demand_miss_latency 6082500 # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_rate 0.007555 # miss rate for demand accesses
system.cpu3.dcache.demand_misses 319 # number of demand (read+write) misses
system.cpu3.dcache.demand_mshr_hits 52 # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_miss_latency 3927000 # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_rate 0.006324 # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_misses 267 # number of demand (read+write) MSHR misses
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dcache.occ_%::0 0.054820 # Average percentage of cache occupancy
system.cpu3.dcache.occ_blocks::0 28.067737 # Average occupied blocks per context
system.cpu3.dcache.overall_accesses 42223 # number of overall (read+write) accesses
system.cpu3.dcache.overall_avg_miss_latency 19067.398119 # average overall miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency 14707.865169 # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu3.dcache.overall_hits 41904 # number of overall hits
system.cpu3.dcache.overall_miss_latency 6082500 # number of overall miss cycles
system.cpu3.dcache.overall_miss_rate 0.007555 # miss rate for overall accesses
system.cpu3.dcache.overall_misses 319 # number of overall misses
system.cpu3.dcache.overall_mshr_hits 52 # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_miss_latency 3927000 # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_rate 0.006324 # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_misses 267 # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu3.dcache.replacements 2 # number of replacements
system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks.
system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu3.dcache.tagsinuse 28.067737 # Cycle average of tags in use
system.cpu3.dcache.total_refs 24305 # Total number of references to valid blocks.
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.dcache.writebacks 1 # number of writebacks
system.cpu3.decode.DECODE:BlockedCycles 35593 # Number of cycles decode is blocked
system.cpu3.decode.DECODE:DecodedInsts 394229 # Number of instructions handled by decode
system.cpu3.decode.DECODE:IdleCycles 164873 # Number of cycles decode is idle
system.cpu3.decode.DECODE:RunCycles 145919 # Number of cycles decode is running
system.cpu3.decode.DECODE:SquashCycles 36967 # Number of cycles decode is squashing
system.cpu3.decode.DECODE:UnblockCycles 151 # Number of cycles decode is unblocking
system.cpu3.fetch.Branches 82266 # Number of branches that fetch encountered
system.cpu3.fetch.CacheLines 80954 # Number of cache lines fetched
system.cpu3.fetch.Cycles 235714 # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.IcacheSquashes 12405 # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.Insts 435938 # Number of instructions fetch has processed
system.cpu3.fetch.SquashCycles 32818 # Number of cycles fetch has spent squashing
system.cpu3.fetch.branchRate 0.208197 # Number of branch fetches per cycle
system.cpu3.fetch.icacheStallCycles 80954 # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.predictedBranches 48405 # Number of branches that fetch has predicted taken
system.cpu3.fetch.rate 1.103263 # Number of inst fetches per cycle
system.cpu3.fetch.rateDist::samples 392614 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean 1.110348 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev 2.081451 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0 237879 60.59% 60.59% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1 82939 21.12% 81.71% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2 12394 3.16% 84.87% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3 15941 4.06% 88.93% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4 2706 0.69% 89.62% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5 16830 4.29% 93.91% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6 1787 0.46% 94.36% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7 2412 0.61% 94.98% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8 19726 5.02% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total 392614 # Number of instructions fetched each cycle (Total)
system.cpu3.icache.ReadReq_accesses 80954 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_avg_miss_latency 13933.423913 # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11485.915493 # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_hits 80218 # number of ReadReq hits
system.cpu3.icache.ReadReq_miss_latency 10255000 # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_rate 0.009092 # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_misses 736 # number of ReadReq misses
system.cpu3.icache.ReadReq_mshr_hits 97 # number of ReadReq MSHR hits
system.cpu3.icache.ReadReq_mshr_miss_latency 7339500 # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate 0.007893 # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_misses 639 # number of ReadReq MSHR misses
system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu3.icache.avg_refs 125.536776 # Average number of references to valid blocks.
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.cache_copies 0 # number of cache copies performed
system.cpu3.icache.demand_accesses 80954 # number of demand (read+write) accesses
system.cpu3.icache.demand_avg_miss_latency 13933.423913 # average overall miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency 11485.915493 # average overall mshr miss latency
system.cpu3.icache.demand_hits 80218 # number of demand (read+write) hits
system.cpu3.icache.demand_miss_latency 10255000 # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_rate 0.009092 # miss rate for demand accesses
system.cpu3.icache.demand_misses 736 # number of demand (read+write) misses
system.cpu3.icache.demand_mshr_hits 97 # number of demand (read+write) MSHR hits
system.cpu3.icache.demand_mshr_miss_latency 7339500 # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_rate 0.007893 # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_misses 639 # number of demand (read+write) MSHR misses
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.icache.occ_%::0 0.188794 # Average percentage of cache occupancy
system.cpu3.icache.occ_blocks::0 96.662446 # Average occupied blocks per context
system.cpu3.icache.overall_accesses 80954 # number of overall (read+write) accesses
system.cpu3.icache.overall_avg_miss_latency 13933.423913 # average overall miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency 11485.915493 # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu3.icache.overall_hits 80218 # number of overall hits
system.cpu3.icache.overall_miss_latency 10255000 # number of overall miss cycles
system.cpu3.icache.overall_miss_rate 0.009092 # miss rate for overall accesses
system.cpu3.icache.overall_misses 736 # number of overall misses
system.cpu3.icache.overall_mshr_hits 97 # number of overall MSHR hits
system.cpu3.icache.overall_mshr_miss_latency 7339500 # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_rate 0.007893 # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_misses 639 # number of overall MSHR misses
system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu3.icache.replacements 527 # number of replacements
system.cpu3.icache.sampled_refs 639 # Sample count of references to valid blocks.
system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu3.icache.tagsinuse 96.662446 # Cycle average of tags in use
system.cpu3.icache.total_refs 80218 # Total number of references to valid blocks.
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.icache.writebacks 0 # number of writebacks
system.cpu3.idleCycles 2521 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.iew.EXEC:branches 39408 # Number of branches executed
system.cpu3.iew.EXEC:nop 47237 # number of nop insts executed
system.cpu3.iew.EXEC:rate 0.449348 # Inst execution rate
system.cpu3.iew.EXEC:refs 53769 # number of memory reference insts executed
system.cpu3.iew.EXEC:stores 15425 # Number of stores executed
system.cpu3.iew.EXEC:swp 0 # number of swp insts executed
system.cpu3.iew.WB:consumers 88234 # num instructions consuming a value
system.cpu3.iew.WB:count 173934 # cumulative count of insts written-back
system.cpu3.iew.WB:fanout 0.937246 # average fanout of values written-back
system.cpu3.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu3.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu3.iew.WB:producers 82697 # num instructions producing a value
system.cpu3.iew.WB:rate 0.440189 # insts written-back per cycle
system.cpu3.iew.WB:sent 174194 # cumulative count of insts sent to commit
system.cpu3.iew.branchMispredicts 33269 # Number of branch mispredicts detected at execute
system.cpu3.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
system.cpu3.iew.iewDispLoadInsts 43341 # Number of dispatched load instructions
system.cpu3.iew.iewDispNonSpecInsts 11749 # Number of dispatched non-speculative instructions
system.cpu3.iew.iewDispSquashedInsts 3545 # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispStoreInsts 27172 # Number of dispatched store instructions
system.cpu3.iew.iewDispatchedInsts 284714 # Number of instructions dispatched to IQ
system.cpu3.iew.iewExecLoadInsts 38344 # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts 36975 # Number of squashed instructions skipped in execute
system.cpu3.iew.iewExecutedInsts 177553 # Number of executed instructions
system.cpu3.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.iewSquashCycles 36967 # Number of cycles IEW is squashing
system.cpu3.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
system.cpu3.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.lsq.thread.0.forwLoads 9839 # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread.0.memOrderViolation 701 # Number of memory ordering violations
system.cpu3.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread.0.squashedLoads 10926 # Number of loads squashed
system.cpu3.iew.lsq.thread.0.squashedStores 13369 # Number of stores squashed
system.cpu3.iew.memOrderViolationEvents 701 # Number of memory order violations
system.cpu3.iew.predictedNotTakenIncorrect 1030 # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.predictedTakenIncorrect 32239 # Number of branches that were predicted taken incorrectly
system.cpu3.ipc 0.281241 # IPC: Instructions Per Cycle
system.cpu3.ipc_total 0.281241 # IPC: Total IPC of All Threads
system.cpu3.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::IntAlu 153538 71.57% 71.57% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::IntMult 0 0.00% 71.57% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.57% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.57% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.57% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.57% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.57% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.57% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.57% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::MemRead 44868 20.91% 92.48% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::MemWrite 16122 7.52% 100.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::total 214528 # Type of FU issued
system.cpu3.iq.ISSUE:fu_busy_cnt 186 # FU busy when requested
system.cpu3.iq.ISSUE:fu_busy_rate 0.000867 # FU busy rate (busy events/executed inst)
system.cpu3.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::IntAlu 24 12.90% 12.90% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::IntMult 0 0.00% 12.90% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::IntDiv 0 0.00% 12.90% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::FloatAdd 0 0.00% 12.90% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.90% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.90% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.90% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.90% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.90% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::MemRead 17 9.14% 22.04% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::MemWrite 145 77.96% 100.00% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.ISSUE:issued_per_cycle::samples 392614 # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::mean 0.546409 # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::stdev 0.998842 # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::0 270914 69.00% 69.00% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::1 66150 16.85% 85.85% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::2 30383 7.74% 93.59% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::3 16859 4.29% 97.88% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::4 5420 1.38% 99.26% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::5 2202 0.56% 99.83% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::6 491 0.13% 99.95% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::7 161 0.04% 99.99% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::8 34 0.01% 100.00% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::total 392614 # Number of insts issued each cycle
system.cpu3.iq.ISSUE:rate 0.542923 # Inst issue rate
system.cpu3.iq.iqInstsAdded 219886 # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqInstsIssued 214528 # Number of instructions issued
system.cpu3.iq.iqNonSpecInstsAdded 17591 # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqSquashedInstsExamined 86635 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedInstsIssued 4 # Number of squashed instructions issued
system.cpu3.iq.iqSquashedNonSpecRemoved 11566 # Number of squashed non-spec instructions that were removed
system.cpu3.iq.iqSquashedOperandsExamined 36678 # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.memDep0.conflictingLoads 10938 # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores 96 # Number of conflicting stores.
system.cpu3.memDep0.insertedLoads 43341 # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores 27172 # Number of stores inserted to the mem dependence unit.
system.cpu3.numCycles 395135 # number of cpu cycles simulated
system.cpu3.rename.RENAME:CommittedMaps 94626 # Number of HB maps that are committed
system.cpu3.rename.RENAME:IdleCycles 180043 # Number of cycles rename is idle
system.cpu3.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full
system.cpu3.rename.RENAME:RenameLookups 494732 # Number of register rename lookups that rename has made
system.cpu3.rename.RENAME:RenamedInsts 312015 # Number of instructions processed by rename
system.cpu3.rename.RENAME:RenamedOperands 231166 # Number of destination operands rename has renamed
system.cpu3.rename.RENAME:RunCycles 130989 # Number of cycles rename is running
system.cpu3.rename.RENAME:SquashCycles 36967 # Number of cycles rename is squashing
system.cpu3.rename.RENAME:UnblockCycles 619 # Number of cycles rename is unblocking
system.cpu3.rename.RENAME:UndoneMaps 136540 # Number of HB maps that are undone due to squashing
system.cpu3.rename.RENAME:serializeStallCycles 34885 # count of cycles rename stalled for serializing inst
system.cpu3.rename.RENAME:serializingInsts 11999 # count of serializing insts renamed
system.cpu3.rename.RENAME:skidInsts 46061 # count of insts added to the skid buffer
system.cpu3.rename.RENAME:tempSerializingInsts 12120 # count of temporary serializing insts renamed
system.cpu3.timesIdled 278 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.l2c.ReadExReq_accesses::0 94 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::1 12 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::2 13 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::3 12 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_avg_miss_latency::0 73122.340426 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1 572791.666667 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::2 528730.769231 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::3 572791.666667 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 1747436.442990 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40312.977099 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_miss_latency 6873500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses::0 94 # number of ReadExReq misses
system.l2c.ReadExReq_misses::1 12 # number of ReadExReq misses
system.l2c.ReadExReq_misses::2 13 # number of ReadExReq misses
system.l2c.ReadExReq_misses::3 12 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses
system.l2c.ReadExReq_mshr_miss_latency 5281000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate::0 1.393617 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1 10.916667 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::2 10.076923 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::3 10.916667 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 33.303873 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_misses 131 # number of ReadExReq MSHR misses
system.l2c.ReadReq_accesses::0 752 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1 650 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::2 646 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::3 653 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2701 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_avg_miss_latency::0 63425.601751 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1 2229653.846154 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::2 362318.750000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::3 4830916.666667 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 7486314.864571 # average ReadReq miss latency
system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_hits::0 295 # number of ReadReq hits
system.l2c.ReadReq_hits::1 637 # number of ReadReq hits
system.l2c.ReadReq_hits::2 566 # number of ReadReq hits
system.l2c.ReadReq_hits::3 647 # number of ReadReq hits
system.l2c.ReadReq_hits::total 2145 # number of ReadReq hits
system.l2c.ReadReq_miss_latency 28985500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_rate::0 0.607713 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1 0.020000 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::2 0.123839 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::3 0.009188 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.760740 # miss rate for ReadReq accesses
system.l2c.ReadReq_misses::0 457 # number of ReadReq misses
system.l2c.ReadReq_misses::1 13 # number of ReadReq misses
system.l2c.ReadReq_misses::2 80 # number of ReadReq misses
system.l2c.ReadReq_misses::3 6 # number of ReadReq misses
system.l2c.ReadReq_misses::total 556 # number of ReadReq misses
system.l2c.ReadReq_mshr_hits 4 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_miss_latency 22080000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::0 0.734043 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1 0.849231 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::2 0.854489 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::3 0.845329 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 3.283092 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_misses 552 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_accesses::0 53 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::1 21 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::2 21 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::3 22 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 117 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_avg_miss_latency::0 24698.113208 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1 62333.333333 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::2 62333.333333 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::3 59500 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 208864.779874 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40038.461538 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_miss_latency 1309000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 4 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses::0 53 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::1 21 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::2 21 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::3 22 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 117 # number of UpgradeReq misses
system.l2c.UpgradeReq_mshr_miss_latency 4684500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_rate::0 2.207547 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1 5.571429 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::2 5.571429 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::3 5.318182 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 18.668586 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_misses 117 # number of UpgradeReq MSHR misses
system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits::0 9 # number of Writeback hits
system.l2c.Writeback_hits::total 9 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.avg_refs 4.003738 # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.demand_accesses::0 846 # number of demand (read+write) accesses
system.l2c.demand_accesses::1 662 # number of demand (read+write) accesses
system.l2c.demand_accesses::2 659 # number of demand (read+write) accesses
system.l2c.demand_accesses::3 665 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2832 # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency::0 65079.854809 # average overall miss latency
system.l2c.demand_avg_miss_latency::1 1434360 # average overall miss latency
system.l2c.demand_avg_miss_latency::2 385580.645161 # average overall miss latency
system.l2c.demand_avg_miss_latency::3 1992166.666667 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 3877187.166637 # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency 40060.029283 # average overall mshr miss latency
system.l2c.demand_hits::0 295 # number of demand (read+write) hits
system.l2c.demand_hits::1 637 # number of demand (read+write) hits
system.l2c.demand_hits::2 566 # number of demand (read+write) hits
system.l2c.demand_hits::3 647 # number of demand (read+write) hits
system.l2c.demand_hits::total 2145 # number of demand (read+write) hits
system.l2c.demand_miss_latency 35859000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate::0 0.651300 # miss rate for demand accesses
system.l2c.demand_miss_rate::1 0.037764 # miss rate for demand accesses
system.l2c.demand_miss_rate::2 0.141123 # miss rate for demand accesses
system.l2c.demand_miss_rate::3 0.027068 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.857255 # miss rate for demand accesses
system.l2c.demand_misses::0 551 # number of demand (read+write) misses
system.l2c.demand_misses::1 25 # number of demand (read+write) misses
system.l2c.demand_misses::2 93 # number of demand (read+write) misses
system.l2c.demand_misses::3 18 # number of demand (read+write) misses
system.l2c.demand_misses::total 687 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 4 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 27361000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate::0 0.807329 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1 1.031722 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::2 1.036419 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::3 1.027068 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 3.902537 # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses 683 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.occ_%::0 0.005570 # Average percentage of cache occupancy
system.l2c.occ_%::1 0.000152 # Average percentage of cache occupancy
system.l2c.occ_%::2 0.001067 # Average percentage of cache occupancy
system.l2c.occ_%::3 0.000056 # Average percentage of cache occupancy
system.l2c.occ_%::4 0.000091 # Average percentage of cache occupancy
system.l2c.occ_blocks::0 365.031703 # Average occupied blocks per context
system.l2c.occ_blocks::1 9.942146 # Average occupied blocks per context
system.l2c.occ_blocks::2 69.921003 # Average occupied blocks per context
system.l2c.occ_blocks::3 3.643564 # Average occupied blocks per context
system.l2c.occ_blocks::4 5.939892 # Average occupied blocks per context
system.l2c.overall_accesses::0 846 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 662 # number of overall (read+write) accesses
system.l2c.overall_accesses::2 659 # number of overall (read+write) accesses
system.l2c.overall_accesses::3 665 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2832 # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency::0 65079.854809 # average overall miss latency
system.l2c.overall_avg_miss_latency::1 1434360 # average overall miss latency
system.l2c.overall_avg_miss_latency::2 385580.645161 # average overall miss latency
system.l2c.overall_avg_miss_latency::3 1992166.666667 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 3877187.166637 # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency 40060.029283 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.l2c.overall_hits::0 295 # number of overall hits
system.l2c.overall_hits::1 637 # number of overall hits
system.l2c.overall_hits::2 566 # number of overall hits
system.l2c.overall_hits::3 647 # number of overall hits
system.l2c.overall_hits::total 2145 # number of overall hits
system.l2c.overall_miss_latency 35859000 # number of overall miss cycles
system.l2c.overall_miss_rate::0 0.651300 # miss rate for overall accesses
system.l2c.overall_miss_rate::1 0.037764 # miss rate for overall accesses
system.l2c.overall_miss_rate::2 0.141123 # miss rate for overall accesses
system.l2c.overall_miss_rate::3 0.027068 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.857255 # miss rate for overall accesses
system.l2c.overall_misses::0 551 # number of overall misses
system.l2c.overall_misses::1 25 # number of overall misses
system.l2c.overall_misses::2 93 # number of overall misses
system.l2c.overall_misses::3 18 # number of overall misses
system.l2c.overall_misses::total 687 # number of overall misses
system.l2c.overall_mshr_hits 4 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 27361000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate::0 0.807329 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1 1.031722 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::2 1.036419 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::3 1.027068 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 3.902537 # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses 683 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.replacements 0 # number of replacements
system.l2c.sampled_refs 535 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.l2c.tagsinuse 454.478308 # Cycle average of tags in use
system.l2c.total_refs 2142 # Total number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.writebacks 0 # number of writebacks
---------- End Simulation Statistics ----------
|