path: root/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats

================ Begin RubySystem Configuration Print ================

RubySystem config:
  random_seed: 1234
  randomization: 0
  tech_nm: 45
  freq_mhz: 3000
  block_size_bytes: 64
  block_size_bits: 6
  memory_size_bytes: 1073741824
  memory_size_bits: 30
DMA_Controller config: DMAController_0
  version: 0
  buffer_size: 32
  dma_sequencer: DMASequencer_0
  number_of_TBEs: 256
  transitions_per_cycle: 32
Directory_Controller config: DirectoryController_0
  version: 0
  buffer_size: 32
  directory_latency: 6
  directory_name: DirectoryMemory_0
  memory_controller_name: MemoryControl_0
  memory_latency: 1
  number_of_TBEs: 256
  recycle_latency: 10
  to_mem_ctrl_latency: 1
  transitions_per_cycle: 32
L1Cache_Controller config: L1CacheController_0
  version: 0
  buffer_size: 32
  cache: l1u_0
  cache_response_latency: 12
  issue_latency: 2
  number_of_TBEs: 256
  sequencer: Sequencer_0
  transitions_per_cycle: 32
L1Cache_Controller config: L1CacheController_1
  version: 1
  buffer_size: 32
  cache: l1u_1
  cache_response_latency: 12
  issue_latency: 2
  number_of_TBEs: 256
  sequencer: Sequencer_1
  transitions_per_cycle: 32
L1Cache_Controller config: L1CacheController_2
  version: 2
  buffer_size: 32
  cache: l1u_2
  cache_response_latency: 12
  issue_latency: 2
  number_of_TBEs: 256
  sequencer: Sequencer_2
  transitions_per_cycle: 32
L1Cache_Controller config: L1CacheController_3
  version: 3
  buffer_size: 32
  cache: l1u_3
  cache_response_latency: 12
  issue_latency: 2
  number_of_TBEs: 256
  sequencer: Sequencer_3
  transitions_per_cycle: 32
L1Cache_Controller config: L1CacheController_4
  version: 4
  buffer_size: 32
  cache: l1u_4
  cache_response_latency: 12
  issue_latency: 2
  number_of_TBEs: 256
  sequencer: Sequencer_4
  transitions_per_cycle: 32
L1Cache_Controller config: L1CacheController_5
  version: 5
  buffer_size: 32
  cache: l1u_5
  cache_response_latency: 12
  issue_latency: 2
  number_of_TBEs: 256
  sequencer: Sequencer_5
  transitions_per_cycle: 32
L1Cache_Controller config: L1CacheController_6
  version: 6
  buffer_size: 32
  cache: l1u_6
  cache_response_latency: 12
  issue_latency: 2
  number_of_TBEs: 256
  sequencer: Sequencer_6
  transitions_per_cycle: 32
L1Cache_Controller config: L1CacheController_7
  version: 7
  buffer_size: 32
  cache: l1u_7
  cache_response_latency: 12
  issue_latency: 2
  number_of_TBEs: 256
  sequencer: Sequencer_7
  transitions_per_cycle: 32
Cache config: l1u_0
  controller: L1CacheController_0
  cache_associativity: 8
  num_cache_sets_bits: 2
  num_cache_sets: 4
  cache_set_size_bytes: 256
  cache_set_size_Kbytes: 0.25
  cache_set_size_Mbytes: 0.000244141
  cache_size_bytes: 2048
  cache_size_Kbytes: 2
  cache_size_Mbytes: 0.00195312
Cache config: l1u_1
  controller: L1CacheController_1
  cache_associativity: 8
  num_cache_sets_bits: 2
  num_cache_sets: 4
  cache_set_size_bytes: 256
  cache_set_size_Kbytes: 0.25
  cache_set_size_Mbytes: 0.000244141
  cache_size_bytes: 2048
  cache_size_Kbytes: 2
  cache_size_Mbytes: 0.00195312
Cache config: l1u_2
  controller: L1CacheController_2
  cache_associativity: 8
  num_cache_sets_bits: 2
  num_cache_sets: 4
  cache_set_size_bytes: 256
  cache_set_size_Kbytes: 0.25
  cache_set_size_Mbytes: 0.000244141
  cache_size_bytes: 2048
  cache_size_Kbytes: 2
  cache_size_Mbytes: 0.00195312
Cache config: l1u_3
  controller: L1CacheController_3
  cache_associativity: 8
  num_cache_sets_bits: 2
  num_cache_sets: 4
  cache_set_size_bytes: 256
  cache_set_size_Kbytes: 0.25
  cache_set_size_Mbytes: 0.000244141
  cache_size_bytes: 2048
  cache_size_Kbytes: 2
  cache_size_Mbytes: 0.00195312
Cache config: l1u_4
  controller: L1CacheController_4
  cache_associativity: 8
  num_cache_sets_bits: 2
  num_cache_sets: 4
  cache_set_size_bytes: 256
  cache_set_size_Kbytes: 0.25
  cache_set_size_Mbytes: 0.000244141
  cache_size_bytes: 2048
  cache_size_Kbytes: 2
  cache_size_Mbytes: 0.00195312
Cache config: l1u_5
  controller: L1CacheController_5
  cache_associativity: 8
  num_cache_sets_bits: 2
  num_cache_sets: 4
  cache_set_size_bytes: 256
  cache_set_size_Kbytes: 0.25
  cache_set_size_Mbytes: 0.000244141
  cache_size_bytes: 2048
  cache_size_Kbytes: 2
  cache_size_Mbytes: 0.00195312
Cache config: l1u_6
  controller: L1CacheController_6
  cache_associativity: 8
  num_cache_sets_bits: 2
  num_cache_sets: 4
  cache_set_size_bytes: 256
  cache_set_size_Kbytes: 0.25
  cache_set_size_Mbytes: 0.000244141
  cache_size_bytes: 2048
  cache_size_Kbytes: 2
  cache_size_Mbytes: 0.00195312
Cache config: l1u_7
  controller: L1CacheController_7
  cache_associativity: 8
  num_cache_sets_bits: 2
  num_cache_sets: 4
  cache_set_size_bytes: 256
  cache_set_size_Kbytes: 0.25
  cache_set_size_Mbytes: 0.000244141
  cache_size_bytes: 2048
  cache_size_Kbytes: 2
  cache_size_Mbytes: 0.00195312
DirectoryMemory Global Config: 
  number of directory memories: 1
  total memory size bytes: 1073741824
  total memory size bits: 30
DirectoryMemory module config: DirectoryMemory_0
  controller: DirectoryController_0
  version: 0
  memory_bits: 30
  memory_size_bytes: 1073741824
  memory_size_Kbytes: 1.04858e+06
  memory_size_Mbytes: 1024
  memory_size_Gbytes: 1
Seqeuncer config: Sequencer_0
  controller: L1CacheController_0
  version: 0
  max_outstanding_requests: 16
  deadlock_threshold: 500000
Seqeuncer config: Sequencer_1
  controller: L1CacheController_1
  version: 1
  max_outstanding_requests: 16
  deadlock_threshold: 500000
Seqeuncer config: Sequencer_2
  controller: L1CacheController_2
  version: 2
  max_outstanding_requests: 16
  deadlock_threshold: 500000
Seqeuncer config: Sequencer_3
  controller: L1CacheController_3
  version: 3
  max_outstanding_requests: 16
  deadlock_threshold: 500000
Seqeuncer config: Sequencer_4
  controller: L1CacheController_4
  version: 4
  max_outstanding_requests: 16
  deadlock_threshold: 500000
Seqeuncer config: Sequencer_5
  controller: L1CacheController_5
  version: 5
  max_outstanding_requests: 16
  deadlock_threshold: 500000
Seqeuncer config: Sequencer_6
  controller: L1CacheController_6
  version: 6
  max_outstanding_requests: 16
  deadlock_threshold: 500000
Seqeuncer config: Sequencer_7
  controller: L1CacheController_7
  version: 7
  max_outstanding_requests: 16
  deadlock_threshold: 500000

Network Configuration
---------------------
network: SIMPLE_NETWORK
topology: theTopology

virtual_net_0: active, ordered
virtual_net_1: active, ordered
virtual_net_2: active, ordered
virtual_net_3: inactive
virtual_net_4: active, ordered
virtual_net_5: active, ordered

--- Begin Topology Print ---

Topology print ONLY indicates the _NETWORK_ latency between two machines
It does NOT include the latency within the machines

L1Cache-0 Network Latencies
  L1Cache-0 -> L1Cache-1 net_lat: 7
  L1Cache-0 -> L1Cache-2 net_lat: 7
  L1Cache-0 -> L1Cache-3 net_lat: 7
  L1Cache-0 -> L1Cache-4 net_lat: 7
  L1Cache-0 -> L1Cache-5 net_lat: 7
  L1Cache-0 -> L1Cache-6 net_lat: 7
  L1Cache-0 -> L1Cache-7 net_lat: 7
  L1Cache-0 -> Directory-0 net_lat: 7
  L1Cache-0 -> DMA-0 net_lat: 7

L1Cache-1 Network Latencies
  L1Cache-1 -> L1Cache-0 net_lat: 7
  L1Cache-1 -> L1Cache-2 net_lat: 7
  L1Cache-1 -> L1Cache-3 net_lat: 7
  L1Cache-1 -> L1Cache-4 net_lat: 7
  L1Cache-1 -> L1Cache-5 net_lat: 7
  L1Cache-1 -> L1Cache-6 net_lat: 7
  L1Cache-1 -> L1Cache-7 net_lat: 7
  L1Cache-1 -> Directory-0 net_lat: 7
  L1Cache-1 -> DMA-0 net_lat: 7

L1Cache-2 Network Latencies
  L1Cache-2 -> L1Cache-0 net_lat: 7
  L1Cache-2 -> L1Cache-1 net_lat: 7
  L1Cache-2 -> L1Cache-3 net_lat: 7
  L1Cache-2 -> L1Cache-4 net_lat: 7
  L1Cache-2 -> L1Cache-5 net_lat: 7
  L1Cache-2 -> L1Cache-6 net_lat: 7
  L1Cache-2 -> L1Cache-7 net_lat: 7
  L1Cache-2 -> Directory-0 net_lat: 7
  L1Cache-2 -> DMA-0 net_lat: 7

L1Cache-3 Network Latencies
  L1Cache-3 -> L1Cache-0 net_lat: 7
  L1Cache-3 -> L1Cache-1 net_lat: 7
  L1Cache-3 -> L1Cache-2 net_lat: 7
  L1Cache-3 -> L1Cache-4 net_lat: 7
  L1Cache-3 -> L1Cache-5 net_lat: 7
  L1Cache-3 -> L1Cache-6 net_lat: 7
  L1Cache-3 -> L1Cache-7 net_lat: 7
  L1Cache-3 -> Directory-0 net_lat: 7
  L1Cache-3 -> DMA-0 net_lat: 7

L1Cache-4 Network Latencies
  L1Cache-4 -> L1Cache-0 net_lat: 7
  L1Cache-4 -> L1Cache-1 net_lat: 7
  L1Cache-4 -> L1Cache-2 net_lat: 7
  L1Cache-4 -> L1Cache-3 net_lat: 7
  L1Cache-4 -> L1Cache-5 net_lat: 7
  L1Cache-4 -> L1Cache-6 net_lat: 7
  L1Cache-4 -> L1Cache-7 net_lat: 7
  L1Cache-4 -> Directory-0 net_lat: 7
  L1Cache-4 -> DMA-0 net_lat: 7

L1Cache-5 Network Latencies
  L1Cache-5 -> L1Cache-0 net_lat: 7
  L1Cache-5 -> L1Cache-1 net_lat: 7
  L1Cache-5 -> L1Cache-2 net_lat: 7
  L1Cache-5 -> L1Cache-3 net_lat: 7
  L1Cache-5 -> L1Cache-4 net_lat: 7
  L1Cache-5 -> L1Cache-6 net_lat: 7
  L1Cache-5 -> L1Cache-7 net_lat: 7
  L1Cache-5 -> Directory-0 net_lat: 7
  L1Cache-5 -> DMA-0 net_lat: 7

L1Cache-6 Network Latencies
  L1Cache-6 -> L1Cache-0 net_lat: 7
  L1Cache-6 -> L1Cache-1 net_lat: 7
  L1Cache-6 -> L1Cache-2 net_lat: 7
  L1Cache-6 -> L1Cache-3 net_lat: 7
  L1Cache-6 -> L1Cache-4 net_lat: 7
  L1Cache-6 -> L1Cache-5 net_lat: 7
  L1Cache-6 -> L1Cache-7 net_lat: 7
  L1Cache-6 -> Directory-0 net_lat: 7
  L1Cache-6 -> DMA-0 net_lat: 7

L1Cache-7 Network Latencies
  L1Cache-7 -> L1Cache-0 net_lat: 7
  L1Cache-7 -> L1Cache-1 net_lat: 7
  L1Cache-7 -> L1Cache-2 net_lat: 7
  L1Cache-7 -> L1Cache-3 net_lat: 7
  L1Cache-7 -> L1Cache-4 net_lat: 7
  L1Cache-7 -> L1Cache-5 net_lat: 7
  L1Cache-7 -> L1Cache-6 net_lat: 7
  L1Cache-7 -> Directory-0 net_lat: 7
  L1Cache-7 -> DMA-0 net_lat: 7

Directory-0 Network Latencies
  Directory-0 -> L1Cache-0 net_lat: 7
  Directory-0 -> L1Cache-1 net_lat: 7
  Directory-0 -> L1Cache-2 net_lat: 7
  Directory-0 -> L1Cache-3 net_lat: 7
  Directory-0 -> L1Cache-4 net_lat: 7
  Directory-0 -> L1Cache-5 net_lat: 7
  Directory-0 -> L1Cache-6 net_lat: 7
  Directory-0 -> L1Cache-7 net_lat: 7
  Directory-0 -> DMA-0 net_lat: 7

DMA-0 Network Latencies
  DMA-0 -> L1Cache-0 net_lat: 7
  DMA-0 -> L1Cache-1 net_lat: 7
  DMA-0 -> L1Cache-2 net_lat: 7
  DMA-0 -> L1Cache-3 net_lat: 7
  DMA-0 -> L1Cache-4 net_lat: 7
  DMA-0 -> L1Cache-5 net_lat: 7
  DMA-0 -> L1Cache-6 net_lat: 7
  DMA-0 -> L1Cache-7 net_lat: 7
  DMA-0 -> Directory-0 net_lat: 7

--- End Topology Print ---

Profiler Configuration
----------------------
periodic_stats_period: 1000000

================ End RubySystem Configuration Print ================


Real time: Jul/29/2009 15:40:36

Profiler Stats
--------------
Elapsed_time_in_seconds: 1279
Elapsed_time_in_minutes: 21.3167
Elapsed_time_in_hours: 0.355278
Elapsed_time_in_days: 0.0148032

Virtual_time_in_seconds: 1279.21
Virtual_time_in_minutes: 21.3202
Virtual_time_in_hours:   0.355336
Virtual_time_in_days:    0.0148057

Ruby_current_time: 31814465
Ruby_start_time: 1
Ruby_cycles: 31814464

mbytes_resident: 150.707
mbytes_total: 1502.61
resident_ratio: 0.100302

Total_misses: 0
total_misses: 0 [ 0 0 0 0 0 0 0 0 ]
user_misses: 0 [ 0 0 0 0 0 0 0 0 ]
supervisor_misses: 0 [ 0 0 0 0 0 0 0 0 ]

ruby_cycles_executed: 254515720 [ 31814465 31814465 31814465 31814465 31814465 31814465 31814465 31814465 ]

transactions_started: 0 [ 0 0 0 0 0 0 0 0 ]
transactions_ended: 0 [ 0 0 0 0 0 0 0 0 ]
cycles_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ]
misses_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ]


Memory control MemoryControl_0:
  memory_total_requests: 1388468
  memory_reads: 694293
  memory_writes: 694043
  memory_refreshes: 66280
  memory_total_request_delays: 426683648
  memory_delays_per_request: 307.305
  memory_delays_in_input_queue: 87635910
  memory_delays_behind_head_of_bank_queue: 258531255
  memory_delays_stalled_at_head_of_bank_queue: 80516483
  memory_stalls_for_bank_busy: 12165032
  memory_stalls_for_random_busy: 0
  memory_stalls_for_anti_starvation: 24715948
  memory_stalls_for_arbitration: 15631815
  memory_stalls_for_bus: 20544794
  memory_stalls_for_tfaw: 0
  memory_stalls_for_read_write_turnaround: 6014461
  memory_stalls_for_read_read_turnaround: 1444433
  accesses_per_bank: 43313  43907  44020  43692  43588  43833  44012  43419  43405  43526  43433  43395  43597  43293  43128  43416  43269  43509  43139  43194  43419  43535  43304  43225  43160  43143  43188  43018  42886  43118  43257  43127  

Busy Controller Counts:
L1Cache-0:0  L1Cache-1:0  L1Cache-2:0  L1Cache-3:0  L1Cache-4:0  L1Cache-5:1  L1Cache-6:0  L1Cache-7:0  

Directory-0:0  
DMA-0:0  

Busy Bank Count:0

sequencer_requests_outstanding: [binsize: 1 max: 16 count: 748260 average: 11.8029 | standard deviation: 3.40671 | 0 1091 2889 5609 9615 15772 23675 33311 44184 55041 64248 70323 72503 72248 68934 64870 143947 ]

All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
miss_latency: [binsize: 128 max: 20559 count: 748171 average: 3866.31 | standard deviation: 2352.95 | 21417 1969 3723 6729 8868 8455 7676 8627 10203 11965 13796 13743 11900 13009 16352 17532 16234 15941 17304 16977 16916 18538 19194 16531 16082 17521 18191 15886 15702 16749 15616 14095 14916 15648 13793 11856 12863 13378 11663 10762 11443 11095 9691 9387 10128 9009 7817 8024 8496 7458 6302 6700 6887 5633 5066 5555 5357 4326 4220 4651 4016 3318 3403 3600 3054 2613 2796 2637 2141 2011 2128 1973 1548 1420 1531 1276 1047 1080 1093 914 741 749 732 584 493 515 525 388 363 345 325 251 268 277 202 190 183 189 147 117 143 119 90 93 91 82 60 58 58 49 51 48 39 28 34 36 30 17 16 21 24 23 12 17 16 9 12 16 12 13 7 4 7 8 7 8 5 7 5 8 4 4 6 5 3 3 2 1 4 1 2 1 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_2: [binsize: 128 max: 20559 count: 486192 average: 3864.95 | standard deviation: 2353.73 | 13998 1281 2484 4424 5714 5472 5029 5648 6631 7775 8926 8800 7735 8448 10496 11466 10602 10387 11224 11076 10939 12065 12497 10830 10391 11396 11931 10259 10262 10939 10169 9130 9608 10113 8955 7714 8408 8711 7593 6973 7459 7162 6232 6134 6554 5848 5110 5134 5495 4860 4083 4319 4432 3674 3259 3647 3406 2774 2755 3099 2579 2160 2269 2367 1984 1705 1833 1725 1372 1293 1349 1289 1004 902 970 862 693 720 732 613 484 488 462 374 341 336 349 246 226 213 205 156 178 186 130 122 119 126 100 72 94 79 57 64 63 57 37 38 35 33 35 27 23 19 22 28 17 7 10 14 16 16 10 7 11 6 8 9 3 6 5 4 4 4 4 4 2 6 3 5 4 3 2 5 3 3 1 1 2 1 2 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_3: [binsize: 128 max: 19863 count: 261979 average: 3868.82 | standard deviation: 2351.5 | 7419 688 1239 2305 3154 2983 2647 2979 3572 4190 4870 4943 4165 4561 5856 6066 5632 5554 6080 5901 5977 6473 6697 5701 5691 6125 6260 5627 5440 5810 5447 4965 5308 5535 4838 4142 4455 4667 4070 3789 3984 3933 3459 3253 3574 3161 2707 2890 3001 2598 2219 2381 2455 1959 1807 1908 1951 1552 1465 1552 1437 1158 1134 1233 1070 908 963 912 769 718 779 684 544 518 561 414 354 360 361 301 257 261 270 210 152 179 176 142 137 132 120 95 90 91 72 68 64 63 47 45 49 40 33 29 28 25 23 20 23 16 16 21 16 9 12 8 13 10 6 7 8 7 2 10 5 3 4 7 9 7 2 0 3 4 3 4 3 1 2 3 0 1 4 0 0 0 1 0 2 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]

All Non-Zero Cycle SW Prefetch Requests
------------------------------------
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Request vs. RubySystem State Profile
--------------------------------


filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]

Message Delayed Cycles
----------------------
Total_delay_cycles: [binsize: 1 max: 18 count: 1496498 average: 0.0019285 | standard deviation: 0.169351 | 1496294 0 2 0 3 0 1 0 1 0 29 0 28 0 42 0 61 0 37 ]
Total_nonPF_delay_cycles: [binsize: 1 max: 18 count: 1496498 average: 0.0019285 | standard deviation: 0.169351 | 1496294 0 2 0 3 0 1 0 1 0 29 0 28 0 42 0 61 0 37 ]
  virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
  virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 748171 average:     0 | standard deviation: 0 | 748171 ]
  virtual_network_2_delay_cycles: [binsize: 1 max: 18 count: 748327 average: 0.0038566 | standard deviation: 0.239469 | 748123 0 2 0 3 0 1 0 1 0 29 0 28 0 42 0 61 0 37 ]
  virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
  virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
  virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]

Resource Usage
--------------
page_size: 4096
user_time: 1279
system_time: 0
page_reclaims: 39805
page_faults: 0
swaps: 0
block_inputs: 0
block_outputs: 0

Network Stats
-------------

switch_0_inlinks: 2
switch_0_outlinks: 2
links_utilized_percent_switch_0: 0.0183757
  links_utilized_percent_switch_0_link_0: 0.0073498 bw: 640000 base_latency: 1
  links_utilized_percent_switch_0_link_1: 0.0294016 bw: 160000 base_latency: 1

  outgoing_messages_switch_0_link_0_Response_Data: 93520 748160 [ 0 93520 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_0_link_0_Writeback_Control: 93544 748352 [ 0 0 93544 0 0 0 ] base_latency: 1
  outgoing_messages_switch_0_link_1_Control: 93523 748184 [ 93523 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_0_link_1_Data: 86916 695328 [ 86916 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_0_link_1_Response_Data: 6640 53120 [ 0 6640 0 0 0 0 ] base_latency: 1

switch_1_inlinks: 2
switch_1_outlinks: 2
links_utilized_percent_switch_1: 0.0183711
  links_utilized_percent_switch_1_link_0: 0.00734831 bw: 640000 base_latency: 1
  links_utilized_percent_switch_1_link_1: 0.0293939 bw: 160000 base_latency: 1

  outgoing_messages_switch_1_link_0_Response_Data: 93502 748016 [ 0 93502 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_1_link_0_Writeback_Control: 93524 748192 [ 0 0 93524 0 0 0 ] base_latency: 1
  outgoing_messages_switch_1_link_1_Control: 93506 748048 [ 93506 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_1_link_1_Data: 86741 693928 [ 86741 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_1_link_1_Response_Data: 6783 54264 [ 0 6783 0 0 0 0 ] base_latency: 1

switch_2_inlinks: 2
switch_2_outlinks: 2
links_utilized_percent_switch_2: 0.0183707
  links_utilized_percent_switch_2_link_0: 0.00734752 bw: 640000 base_latency: 1
  links_utilized_percent_switch_2_link_1: 0.0293939 bw: 160000 base_latency: 1

  outgoing_messages_switch_2_link_0_Response_Data: 93497 747976 [ 0 93497 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_2_link_0_Writeback_Control: 93509 748072 [ 0 0 93509 0 0 0 ] base_latency: 1
  outgoing_messages_switch_2_link_1_Control: 93510 748080 [ 93510 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_2_link_1_Data: 86829 694632 [ 86829 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_2_link_1_Response_Data: 6691 53528 [ 0 6691 0 0 0 0 ] base_latency: 1

switch_3_inlinks: 2
switch_3_outlinks: 2
links_utilized_percent_switch_3: 0.0183818
  links_utilized_percent_switch_3_link_0: 0.00735177 bw: 640000 base_latency: 1
  links_utilized_percent_switch_3_link_1: 0.0294118 bw: 160000 base_latency: 1

  outgoing_messages_switch_3_link_0_Response_Data: 93545 748360 [ 0 93545 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_3_link_0_Writeback_Control: 93569 748552 [ 0 0 93569 0 0 0 ] base_latency: 1
  outgoing_messages_switch_3_link_1_Control: 93558 748464 [ 93558 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_3_link_1_Data: 86852 694816 [ 86852 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_3_link_1_Response_Data: 6734 53872 [ 0 6734 0 0 0 0 ] base_latency: 1

switch_4_inlinks: 2
switch_4_outlinks: 2
links_utilized_percent_switch_4: 0.0183835
  links_utilized_percent_switch_4_link_0: 0.00735287 bw: 640000 base_latency: 1
  links_utilized_percent_switch_4_link_1: 0.0294141 bw: 160000 base_latency: 1

  outgoing_messages_switch_4_link_0_Response_Data: 93560 748480 [ 0 93560 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_4_link_0_Writeback_Control: 93582 748656 [ 0 0 93582 0 0 0 ] base_latency: 1
  outgoing_messages_switch_4_link_1_Control: 93567 748536 [ 93567 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_4_link_1_Data: 86798 694384 [ 86798 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_4_link_1_Response_Data: 6794 54352 [ 0 6794 0 0 0 0 ] base_latency: 1

switch_5_inlinks: 2
switch_5_outlinks: 2
links_utilized_percent_switch_5: 0.0183813
  links_utilized_percent_switch_5_link_0: 0.00735204 bw: 640000 base_latency: 1
  links_utilized_percent_switch_5_link_1: 0.0294105 bw: 160000 base_latency: 1

  outgoing_messages_switch_5_link_0_Response_Data: 93552 748416 [ 0 93552 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_5_link_0_Writeback_Control: 93569 748552 [ 0 0 93569 0 0 0 ] base_latency: 1
  outgoing_messages_switch_5_link_1_Control: 93561 748488 [ 93561 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_5_link_1_Data: 86705 693640 [ 86705 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_5_link_1_Response_Data: 6870 54960 [ 0 6870 0 0 0 0 ] base_latency: 1

switch_6_inlinks: 2
switch_6_outlinks: 2
links_utilized_percent_switch_6: 0.0183704
  links_utilized_percent_switch_6_link_0: 0.00734764 bw: 640000 base_latency: 1
  links_utilized_percent_switch_6_link_1: 0.0293932 bw: 160000 base_latency: 1

  outgoing_messages_switch_6_link_0_Response_Data: 93494 747952 [ 0 93494 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_6_link_0_Writeback_Control: 93515 748120 [ 0 0 93515 0 0 0 ] base_latency: 1
  outgoing_messages_switch_6_link_1_Control: 93502 748016 [ 93502 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_6_link_1_Data: 86898 695184 [ 86898 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_6_link_1_Response_Data: 6626 53008 [ 0 6626 0 0 0 0 ] base_latency: 1

switch_7_inlinks: 2
switch_7_outlinks: 2
links_utilized_percent_switch_7: 0.0183714
  links_utilized_percent_switch_7_link_0: 0.00734792 bw: 640000 base_latency: 1
  links_utilized_percent_switch_7_link_1: 0.0293948 bw: 160000 base_latency: 1

  outgoing_messages_switch_7_link_0_Response_Data: 93501 748008 [ 0 93501 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_7_link_0_Writeback_Control: 93515 748120 [ 0 0 93515 0 0 0 ] base_latency: 1
  outgoing_messages_switch_7_link_1_Control: 93509 748072 [ 93509 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_7_link_1_Data: 86787 694296 [ 86787 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_7_link_1_Response_Data: 6740 53920 [ 0 6740 0 0 0 0 ] base_latency: 1

switch_8_inlinks: 2
switch_8_outlinks: 2
links_utilized_percent_switch_8: 0.141705
  links_utilized_percent_switch_8_link_0: 0.0566866 bw: 640000 base_latency: 1
  links_utilized_percent_switch_8_link_1: 0.226724 bw: 160000 base_latency: 1

  outgoing_messages_switch_8_link_0_Control: 748236 5985888 [ 748236 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_8_link_0_Data: 694526 5556208 [ 694526 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_8_link_1_Response_Data: 694293 5554344 [ 0 694293 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_8_link_1_Writeback_Control: 748327 5986616 [ 0 0 748327 0 0 0 ] base_latency: 1

switch_9_inlinks: 2
switch_9_outlinks: 2
links_utilized_percent_switch_9: 0
  links_utilized_percent_switch_9_link_0: 0 bw: 640000 base_latency: 1
  links_utilized_percent_switch_9_link_1: 0 bw: 160000 base_latency: 1


switch_10_inlinks: 10
switch_10_outlinks: 10
links_utilized_percent_switch_10: 0.0461938
  links_utilized_percent_switch_10_link_0: 0.0293992 bw: 160000 base_latency: 1
  links_utilized_percent_switch_10_link_1: 0.0293932 bw: 160000 base_latency: 1
  links_utilized_percent_switch_10_link_2: 0.0293901 bw: 160000 base_latency: 1
  links_utilized_percent_switch_10_link_3: 0.0294071 bw: 160000 base_latency: 1
  links_utilized_percent_switch_10_link_4: 0.0294115 bw: 160000 base_latency: 1
  links_utilized_percent_switch_10_link_5: 0.0294082 bw: 160000 base_latency: 1
  links_utilized_percent_switch_10_link_6: 0.0293906 bw: 160000 base_latency: 1
  links_utilized_percent_switch_10_link_7: 0.0293917 bw: 160000 base_latency: 1
  links_utilized_percent_switch_10_link_8: 0.226746 bw: 160000 base_latency: 1
  links_utilized_percent_switch_10_link_9: 0 bw: 160000 base_latency: 1

  outgoing_messages_switch_10_link_0_Response_Data: 93520 748160 [ 0 93520 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_0_Writeback_Control: 93544 748352 [ 0 0 93544 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_1_Response_Data: 93502 748016 [ 0 93502 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_1_Writeback_Control: 93524 748192 [ 0 0 93524 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_2_Response_Data: 93497 747976 [ 0 93497 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_2_Writeback_Control: 93509 748072 [ 0 0 93509 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_3_Response_Data: 93545 748360 [ 0 93545 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_3_Writeback_Control: 93569 748552 [ 0 0 93569 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_4_Response_Data: 93560 748480 [ 0 93560 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_4_Writeback_Control: 93582 748656 [ 0 0 93582 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_5_Response_Data: 93552 748416 [ 0 93552 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_5_Writeback_Control: 93569 748552 [ 0 0 93569 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_6_Response_Data: 93494 747952 [ 0 93494 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_6_Writeback_Control: 93515 748120 [ 0 0 93515 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_7_Response_Data: 93501 748008 [ 0 93501 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_7_Writeback_Control: 93515 748120 [ 0 0 93515 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_8_Control: 748236 5985888 [ 748236 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_8_Data: 694526 5556208 [ 694526 0 0 0 0 0 ] base_latency: 1

l1u_0 cache stats: 
  l1u_0_total_misses: 93523
  l1u_0_total_demand_misses: 93523
  l1u_0_total_prefetches: 0
  l1u_0_total_sw_prefetches: 0
  l1u_0_total_hw_prefetches: 0
  l1u_0_misses_per_transaction: inf

  l1u_0_request_type_LD:   64.8311%
  l1u_0_request_type_ST:   35.1689%

  l1u_0_access_mode_type_SupervisorMode:   93523    100%
  l1u_0_request_size: [binsize: log2 max: 1 count: 93523 average:     1 | standard deviation: 0 | 0 93523 ]

l1u_1 cache stats: 
  l1u_1_total_misses: 93506
  l1u_1_total_demand_misses: 93506
  l1u_1_total_prefetches: 0
  l1u_1_total_sw_prefetches: 0
  l1u_1_total_hw_prefetches: 0
  l1u_1_misses_per_transaction: inf

  l1u_1_request_type_LD:   64.8162%
  l1u_1_request_type_ST:   35.1838%

  l1u_1_access_mode_type_SupervisorMode:   93506    100%
  l1u_1_request_size: [binsize: log2 max: 1 count: 93506 average:     1 | standard deviation: 0 | 0 93506 ]

l1u_2 cache stats: 
  l1u_2_total_misses: 93510
  l1u_2_total_demand_misses: 93510
  l1u_2_total_prefetches: 0
  l1u_2_total_sw_prefetches: 0
  l1u_2_total_hw_prefetches: 0
  l1u_2_misses_per_transaction: inf

  l1u_2_request_type_LD:   64.931%
  l1u_2_request_type_ST:   35.069%

  l1u_2_access_mode_type_SupervisorMode:   93510    100%
  l1u_2_request_size: [binsize: log2 max: 1 count: 93510 average:     1 | standard deviation: 0 | 0 93510 ]

l1u_3 cache stats: 
  l1u_3_total_misses: 93558
  l1u_3_total_demand_misses: 93558
  l1u_3_total_prefetches: 0
  l1u_3_total_sw_prefetches: 0
  l1u_3_total_hw_prefetches: 0
  l1u_3_misses_per_transaction: inf

  l1u_3_request_type_LD:   64.9693%
  l1u_3_request_type_ST:   35.0307%

  l1u_3_access_mode_type_SupervisorMode:   93558    100%
  l1u_3_request_size: [binsize: log2 max: 1 count: 93558 average:     1 | standard deviation: 0 | 0 93558 ]

l1u_4 cache stats: 
  l1u_4_total_misses: 93567
  l1u_4_total_demand_misses: 93567
  l1u_4_total_prefetches: 0
  l1u_4_total_sw_prefetches: 0
  l1u_4_total_hw_prefetches: 0
  l1u_4_misses_per_transaction: inf

  l1u_4_request_type_LD:   65.2474%
  l1u_4_request_type_ST:   34.7526%

  l1u_4_access_mode_type_SupervisorMode:   93567    100%
  l1u_4_request_size: [binsize: log2 max: 1 count: 93567 average:     1 | standard deviation: 0 | 0 93567 ]

l1u_5 cache stats: 
  l1u_5_total_misses: 93561
  l1u_5_total_demand_misses: 93561
  l1u_5_total_prefetches: 0
  l1u_5_total_sw_prefetches: 0
  l1u_5_total_hw_prefetches: 0
  l1u_5_misses_per_transaction: inf

  l1u_5_request_type_LD:   65.0004%
  l1u_5_request_type_ST:   34.9996%

  l1u_5_access_mode_type_SupervisorMode:   93561    100%
  l1u_5_request_size: [binsize: log2 max: 1 count: 93561 average:     1 | standard deviation: 0 | 0 93561 ]

l1u_6 cache stats: 
  l1u_6_total_misses: 93502
  l1u_6_total_demand_misses: 93502
  l1u_6_total_prefetches: 0
  l1u_6_total_sw_prefetches: 0
  l1u_6_total_hw_prefetches: 0
  l1u_6_misses_per_transaction: inf

  l1u_6_request_type_LD:   64.9569%
  l1u_6_request_type_ST:   35.0431%

  l1u_6_access_mode_type_SupervisorMode:   93502    100%
  l1u_6_request_size: [binsize: log2 max: 1 count: 93502 average:     1 | standard deviation: 0 | 0 93502 ]

l1u_7 cache stats: 
  l1u_7_total_misses: 93509
  l1u_7_total_demand_misses: 93509
  l1u_7_total_prefetches: 0
  l1u_7_total_sw_prefetches: 0
  l1u_7_total_hw_prefetches: 0
  l1u_7_misses_per_transaction: inf

  l1u_7_request_type_LD:   65.1189%
  l1u_7_request_type_ST:   34.8811%

  l1u_7_access_mode_type_SupervisorMode:   93509    100%
  l1u_7_request_size: [binsize: log2 max: 1 count: 93509 average:     1 | standard deviation: 0 | 0 93509 ]

 --- DMA 0 ---
 - Event Counts -
ReadRequest  0
WriteRequest  0
Data  0
Ack  0

 - Transitions -
READY  ReadRequest  0 <-- 
READY  WriteRequest  0 <-- 

BUSY_RD  Data  0 <-- 

BUSY_WR  Ack  0 <-- 

 --- Directory 0 ---
 - Event Counts -
GETX  7422269
GETS  0
PUTX  694113
PUTX_NotOwner  412
DMA_READ  0
DMA_WRITE  0
Memory_Data  694293
Memory_Ack  694037

 - Transitions -
I  GETX  694355
I  PUTX_NotOwner  0 <-- 
I  DMA_READ  0 <-- 
I  DMA_WRITE  0 <-- 

M  GETX  53878
M  PUTX  694113
M  PUTX_NotOwner  412
M  DMA_READ  0 <-- 
M  DMA_WRITE  0 <-- 

M_DRD  GETX  0 <-- 
M_DRD  PUTX  0 <-- 

M_DWR  GETX  0 <-- 
M_DWR  PUTX  0 <-- 

M_DWRI  Memory_Ack  0 <-- 

IM  GETX  3217688
IM  GETS  0 <-- 
IM  PUTX  0 <-- 
IM  PUTX_NotOwner  0 <-- 
IM  DMA_READ  0 <-- 
IM  DMA_WRITE  0 <-- 
IM  Memory_Data  694293

MI  GETX  3456348
MI  GETS  0 <-- 
MI  PUTX  0 <-- 
MI  PUTX_NotOwner  0 <-- 
MI  DMA_READ  0 <-- 
MI  DMA_WRITE  0 <-- 
MI  Memory_Ack  694037

ID  GETX  0 <-- 
ID  GETS  0 <-- 
ID  PUTX  0 <-- 
ID  PUTX_NotOwner  0 <-- 
ID  DMA_READ  0 <-- 
ID  DMA_WRITE  0 <-- 
ID  Memory_Data  0 <-- 

ID_W  GETX  0 <-- 
ID_W  GETS  0 <-- 
ID_W  PUTX  0 <-- 
ID_W  PUTX_NotOwner  0 <-- 
ID_W  DMA_READ  0 <-- 
ID_W  DMA_WRITE  0 <-- 
ID_W  Memory_Ack  0 <-- 

 --- L1Cache 0 ---
 - Event Counts -
Load  60632
Ifetch  0
Store  32891
Data  93520
Fwd_GETX  6640
Inv  0
Replacement  93491
Writeback_Ack  86841
Writeback_Nack  63

 - Transitions -
I  Load  60632
I  Ifetch  0 <-- 
I  Store  32891
I  Inv  0 <-- 
I  Replacement  6575

II  Writeback_Nack  63

M  Load  0 <-- 
M  Ifetch  0 <-- 
M  Store  0 <-- 
M  Fwd_GETX  6577
M  Inv  0 <-- 
M  Replacement  86916

MI  Fwd_GETX  63
MI  Inv  0 <-- 
MI  Writeback_Ack  86841

IS  Data  60630

IM  Data  32890

 --- L1Cache 1 ---
 - Event Counts -
Load  60607
Ifetch  0
Store  32899
Data  93502
Fwd_GETX  6783
Inv  0
Replacement  93474
Writeback_Ack  86692
Writeback_Nack  49

 - Transitions -
I  Load  60607
I  Ifetch  0 <-- 
I  Store  32899
I  Inv  0 <-- 
I  Replacement  6733

II  Writeback_Nack  49

M  Load  0 <-- 
M  Ifetch  0 <-- 
M  Store  0 <-- 
M  Fwd_GETX  6734
M  Inv  0 <-- 
M  Replacement  86741

MI  Fwd_GETX  49
MI  Inv  0 <-- 
MI  Writeback_Ack  86692

IS  Data  60604

IM  Data  32898

 --- L1Cache 2 ---
 - Event Counts -
Load  60717
Ifetch  0
Store  32793
Data  93497
Fwd_GETX  6691
Inv  0
Replacement  93478
Writeback_Ack  86777
Writeback_Nack  41

 - Transitions -
I  Load  60717
I  Ifetch  0 <-- 
I  Store  32793
I  Inv  0 <-- 
I  Replacement  6649

II  Writeback_Nack  41

M  Load  0 <-- 
M  Ifetch  0 <-- 
M  Store  0 <-- 
M  Fwd_GETX  6650
M  Inv  0 <-- 
M  Replacement  86829

MI  Fwd_GETX  41
MI  Inv  0 <-- 
MI  Writeback_Ack  86777

IS  Data  60709

IM  Data  32788

 --- L1Cache 3 ---
 - Event Counts -
Load  60784
Ifetch  0
Store  32774
Data  93545
Fwd_GETX  6734
Inv  0
Replacement  93526
Writeback_Ack  86775
Writeback_Nack  60

 - Transitions -
I  Load  60784
I  Ifetch  0 <-- 
I  Store  32774
I  Inv  0 <-- 
I  Replacement  6674

II  Writeback_Nack  60

M  Load  0 <-- 
M  Ifetch  0 <-- 
M  Store  0 <-- 
M  Fwd_GETX  6674
M  Inv  0 <-- 
M  Replacement  86852

MI  Fwd_GETX  60
MI  Inv  0 <-- 
MI  Writeback_Ack  86775

IS  Data  60776

IM  Data  32769

 --- L1Cache 4 ---
 - Event Counts -
Load  61050
Ifetch  0
Store  32517
Data  93560
Fwd_GETX  6794
Inv  0
Replacement  93535
Writeback_Ack  86735
Writeback_Nack  53

 - Transitions -
I  Load  61050
I  Ifetch  0 <-- 
I  Store  32517
I  Inv  0 <-- 
I  Replacement  6737

II  Writeback_Nack  53

M  Load  0 <-- 
M  Ifetch  0 <-- 
M  Store  0 <-- 
M  Fwd_GETX  6741
M  Inv  0 <-- 
M  Replacement  86798

MI  Fwd_GETX  53
MI  Inv  0 <-- 
MI  Writeback_Ack  86735

IS  Data  61047

IM  Data  32513

 --- L1Cache 5 ---
 - Event Counts -
Load  60815
Ifetch  0
Store  32746
Data  93552
Fwd_GETX  6870
Inv  0
Replacement  93529
Writeback_Ack  86654
Writeback_Nack  45

 - Transitions -
I  Load  60815
I  Ifetch  0 <-- 
I  Store  32746
I  Inv  0 <-- 
I  Replacement  6824

II  Writeback_Nack  45

M  Load  0 <-- 
M  Ifetch  0 <-- 
M  Store  0 <-- 
M  Fwd_GETX  6825
M  Inv  0 <-- 
M  Replacement  86705

MI  Fwd_GETX  45
MI  Inv  0 <-- 
MI  Writeback_Ack  86654

IS  Data  60809

IM  Data  32743

 --- L1Cache 6 ---
 - Event Counts -
Load  60736
Ifetch  0
Store  32766
Data  93494
Fwd_GETX  6626
Inv  0
Replacement  93470
Writeback_Ack  86837
Writeback_Nack  52

 - Transitions -
I  Load  60736
I  Ifetch  0 <-- 
I  Store  32766
I  Inv  0 <-- 
I  Replacement  6572

II  Writeback_Nack  52

M  Load  0 <-- 
M  Ifetch  0 <-- 
M  Store  0 <-- 
M  Fwd_GETX  6574
M  Inv  0 <-- 
M  Replacement  86898

MI  Fwd_GETX  52
MI  Inv  0 <-- 
MI  Writeback_Ack  86837

IS  Data  60730

IM  Data  32764

 --- L1Cache 7 ---
 - Event Counts -
Load  60892
Ifetch  0
Store  32617
Data  93501
Fwd_GETX  6740
Inv  0
Replacement  93477
Writeback_Ack  86726
Writeback_Nack  49

 - Transitions -
I  Load  60892
I  Ifetch  0 <-- 
I  Store  32617
I  Inv  0 <-- 
I  Replacement  6690

II  Writeback_Nack  49

M  Load  0 <-- 
M  Ifetch  0 <-- 
M  Store  0 <-- 
M  Fwd_GETX  6691
M  Inv  0 <-- 
M  Replacement  86787

MI  Fwd_GETX  49
MI  Inv  0 <-- 
MI  Writeback_Ack  86726

IS  Data  60887

IM  Data  32614