blob: e1968f98344eef4e7319dae17789a41546c8c8ac (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
|
================ Begin RubySystem Configuration Print ================
RubySystem config:
random_seed: 1234
randomization: 0
tech_nm: 45
freq_mhz: 3000
block_size_bytes: 64
block_size_bits: 6
memory_size_bytes: 1073741824
memory_size_bits: 30
DMA_Controller config: DMAController_0
version: 0
buffer_size: 32
dma_sequencer: DMASequencer_0
number_of_TBEs: 256
recycle_latency: 10
request_latency: 14
response_latency: 14
transitions_per_cycle: 32
Directory_Controller config: DirectoryController_0
version: 0
buffer_size: 32
directory: DirectoryMemory_0
directory_latency: 6
memory_control: MemoryControl_0
number_of_TBEs: 256
recycle_latency: 10
transitions_per_cycle: 32
L1Cache_Controller config: L1CacheController_0
version: 0
buffer_size: 32
dcache: l1d_0
icache: l1i_0
l2_select_low_bit: 6
l2_select_num_bits: 1
number_of_TBEs: 256
recycle_latency: 10
request_latency: 2
sequencer: Sequencer_0
transitions_per_cycle: 32
L1Cache_Controller config: L1CacheController_1
version: 1
buffer_size: 32
dcache: l1d_1
icache: l1i_1
l2_select_low_bit: 6
l2_select_num_bits: 1
number_of_TBEs: 256
recycle_latency: 10
request_latency: 2
sequencer: Sequencer_1
transitions_per_cycle: 32
L1Cache_Controller config: L1CacheController_2
version: 2
buffer_size: 32
dcache: l1d_2
icache: l1i_2
l2_select_low_bit: 6
l2_select_num_bits: 1
number_of_TBEs: 256
recycle_latency: 10
request_latency: 2
sequencer: Sequencer_2
transitions_per_cycle: 32
L1Cache_Controller config: L1CacheController_3
version: 3
buffer_size: 32
dcache: l1d_3
icache: l1i_3
l2_select_low_bit: 6
l2_select_num_bits: 1
number_of_TBEs: 256
recycle_latency: 10
request_latency: 2
sequencer: Sequencer_3
transitions_per_cycle: 32
L1Cache_Controller config: L1CacheController_4
version: 4
buffer_size: 32
dcache: l1d_4
icache: l1i_4
l2_select_low_bit: 6
l2_select_num_bits: 1
number_of_TBEs: 256
recycle_latency: 10
request_latency: 2
sequencer: Sequencer_4
transitions_per_cycle: 32
L1Cache_Controller config: L1CacheController_5
version: 5
buffer_size: 32
dcache: l1d_5
icache: l1i_5
l2_select_low_bit: 6
l2_select_num_bits: 1
number_of_TBEs: 256
recycle_latency: 10
request_latency: 2
sequencer: Sequencer_5
transitions_per_cycle: 32
L1Cache_Controller config: L1CacheController_6
version: 6
buffer_size: 32
dcache: l1d_6
icache: l1i_6
l2_select_low_bit: 6
l2_select_num_bits: 1
number_of_TBEs: 256
recycle_latency: 10
request_latency: 2
sequencer: Sequencer_6
transitions_per_cycle: 32
L1Cache_Controller config: L1CacheController_7
version: 7
buffer_size: 32
dcache: l1d_7
icache: l1i_7
l2_select_low_bit: 6
l2_select_num_bits: 1
number_of_TBEs: 256
recycle_latency: 10
request_latency: 2
sequencer: Sequencer_7
transitions_per_cycle: 32
L2Cache_Controller config: L2CacheController_0
version: 0
buffer_size: 32
cache: l2u_0
number_of_TBEs: 256
recycle_latency: 10
request_latency: 14
response_latency: 14
transitions_per_cycle: 32
L2Cache_Controller config: L2CacheController_1
version: 1
buffer_size: 32
cache: l2u_1
number_of_TBEs: 256
recycle_latency: 10
request_latency: 14
response_latency: 14
transitions_per_cycle: 32
Cache config: l1d_0
controller: L1CacheController_0
cache_associativity: 8
num_cache_sets_bits: 4
num_cache_sets: 16
cache_set_size_bytes: 1024
cache_set_size_Kbytes: 1
cache_set_size_Mbytes: 0.000976562
cache_size_bytes: 8192
cache_size_Kbytes: 8
cache_size_Mbytes: 0.0078125
Cache config: l1d_1
controller: L1CacheController_1
cache_associativity: 8
num_cache_sets_bits: 4
num_cache_sets: 16
cache_set_size_bytes: 1024
cache_set_size_Kbytes: 1
cache_set_size_Mbytes: 0.000976562
cache_size_bytes: 8192
cache_size_Kbytes: 8
cache_size_Mbytes: 0.0078125
Cache config: l1d_2
controller: L1CacheController_2
cache_associativity: 8
num_cache_sets_bits: 4
num_cache_sets: 16
cache_set_size_bytes: 1024
cache_set_size_Kbytes: 1
cache_set_size_Mbytes: 0.000976562
cache_size_bytes: 8192
cache_size_Kbytes: 8
cache_size_Mbytes: 0.0078125
Cache config: l1d_3
controller: L1CacheController_3
cache_associativity: 8
num_cache_sets_bits: 4
num_cache_sets: 16
cache_set_size_bytes: 1024
cache_set_size_Kbytes: 1
cache_set_size_Mbytes: 0.000976562
cache_size_bytes: 8192
cache_size_Kbytes: 8
cache_size_Mbytes: 0.0078125
Cache config: l1d_4
controller: L1CacheController_4
cache_associativity: 8
num_cache_sets_bits: 4
num_cache_sets: 16
cache_set_size_bytes: 1024
cache_set_size_Kbytes: 1
cache_set_size_Mbytes: 0.000976562
cache_size_bytes: 8192
cache_size_Kbytes: 8
cache_size_Mbytes: 0.0078125
Cache config: l1d_5
controller: L1CacheController_5
cache_associativity: 8
num_cache_sets_bits: 4
num_cache_sets: 16
cache_set_size_bytes: 1024
cache_set_size_Kbytes: 1
cache_set_size_Mbytes: 0.000976562
cache_size_bytes: 8192
cache_size_Kbytes: 8
cache_size_Mbytes: 0.0078125
Cache config: l1d_6
controller: L1CacheController_6
cache_associativity: 8
num_cache_sets_bits: 4
num_cache_sets: 16
cache_set_size_bytes: 1024
cache_set_size_Kbytes: 1
cache_set_size_Mbytes: 0.000976562
cache_size_bytes: 8192
cache_size_Kbytes: 8
cache_size_Mbytes: 0.0078125
Cache config: l1d_7
controller: L1CacheController_7
cache_associativity: 8
num_cache_sets_bits: 4
num_cache_sets: 16
cache_set_size_bytes: 1024
cache_set_size_Kbytes: 1
cache_set_size_Mbytes: 0.000976562
cache_size_bytes: 8192
cache_size_Kbytes: 8
cache_size_Mbytes: 0.0078125
Cache config: l1i_0
controller: L1CacheController_0
cache_associativity: 8
num_cache_sets_bits: 7
num_cache_sets: 128
cache_set_size_bytes: 8192
cache_set_size_Kbytes: 8
cache_set_size_Mbytes: 0.0078125
cache_size_bytes: 65536
cache_size_Kbytes: 64
cache_size_Mbytes: 0.0625
Cache config: l1i_1
controller: L1CacheController_1
cache_associativity: 8
num_cache_sets_bits: 7
num_cache_sets: 128
cache_set_size_bytes: 8192
cache_set_size_Kbytes: 8
cache_set_size_Mbytes: 0.0078125
cache_size_bytes: 65536
cache_size_Kbytes: 64
cache_size_Mbytes: 0.0625
Cache config: l1i_2
controller: L1CacheController_2
cache_associativity: 8
num_cache_sets_bits: 7
num_cache_sets: 128
cache_set_size_bytes: 8192
cache_set_size_Kbytes: 8
cache_set_size_Mbytes: 0.0078125
cache_size_bytes: 65536
cache_size_Kbytes: 64
cache_size_Mbytes: 0.0625
Cache config: l1i_3
controller: L1CacheController_3
cache_associativity: 8
num_cache_sets_bits: 7
num_cache_sets: 128
cache_set_size_bytes: 8192
cache_set_size_Kbytes: 8
cache_set_size_Mbytes: 0.0078125
cache_size_bytes: 65536
cache_size_Kbytes: 64
cache_size_Mbytes: 0.0625
Cache config: l1i_4
controller: L1CacheController_4
cache_associativity: 8
num_cache_sets_bits: 7
num_cache_sets: 128
cache_set_size_bytes: 8192
cache_set_size_Kbytes: 8
cache_set_size_Mbytes: 0.0078125
cache_size_bytes: 65536
cache_size_Kbytes: 64
cache_size_Mbytes: 0.0625
Cache config: l1i_5
controller: L1CacheController_5
cache_associativity: 8
num_cache_sets_bits: 7
num_cache_sets: 128
cache_set_size_bytes: 8192
cache_set_size_Kbytes: 8
cache_set_size_Mbytes: 0.0078125
cache_size_bytes: 65536
cache_size_Kbytes: 64
cache_size_Mbytes: 0.0625
Cache config: l1i_6
controller: L1CacheController_6
cache_associativity: 8
num_cache_sets_bits: 7
num_cache_sets: 128
cache_set_size_bytes: 8192
cache_set_size_Kbytes: 8
cache_set_size_Mbytes: 0.0078125
cache_size_bytes: 65536
cache_size_Kbytes: 64
cache_size_Mbytes: 0.0625
Cache config: l1i_7
controller: L1CacheController_7
cache_associativity: 8
num_cache_sets_bits: 7
num_cache_sets: 128
cache_set_size_bytes: 8192
cache_set_size_Kbytes: 8
cache_set_size_Mbytes: 0.0078125
cache_size_bytes: 65536
cache_size_Kbytes: 64
cache_size_Mbytes: 0.0625
Cache config: l2u_0
controller: L2CacheController_0
cache_associativity: 16
num_cache_sets_bits: 12
num_cache_sets: 4096
cache_set_size_bytes: 262144
cache_set_size_Kbytes: 256
cache_set_size_Mbytes: 0.25
cache_size_bytes: 4194304
cache_size_Kbytes: 4096
cache_size_Mbytes: 4
Cache config: l2u_1
controller: L2CacheController_1
cache_associativity: 16
num_cache_sets_bits: 12
num_cache_sets: 4096
cache_set_size_bytes: 262144
cache_set_size_Kbytes: 256
cache_set_size_Mbytes: 0.25
cache_size_bytes: 4194304
cache_size_Kbytes: 4096
cache_size_Mbytes: 4
DirectoryMemory Global Config:
number of directory memories: 1
total memory size bytes: 1073741824
total memory size bits: 30
DirectoryMemory module config: DirectoryMemory_0
controller: DirectoryController_0
version: 0
memory_bits: 30
memory_size_bytes: 1073741824
memory_size_Kbytes: 1.04858e+06
memory_size_Mbytes: 1024
memory_size_Gbytes: 1
Seqeuncer config: Sequencer_0
controller: L1CacheController_0
version: 0
max_outstanding_requests: 16
deadlock_threshold: 500000
Seqeuncer config: Sequencer_1
controller: L1CacheController_1
version: 1
max_outstanding_requests: 16
deadlock_threshold: 500000
Seqeuncer config: Sequencer_2
controller: L1CacheController_2
version: 2
max_outstanding_requests: 16
deadlock_threshold: 500000
Seqeuncer config: Sequencer_3
controller: L1CacheController_3
version: 3
max_outstanding_requests: 16
deadlock_threshold: 500000
Seqeuncer config: Sequencer_4
controller: L1CacheController_4
version: 4
max_outstanding_requests: 16
deadlock_threshold: 500000
Seqeuncer config: Sequencer_5
controller: L1CacheController_5
version: 5
max_outstanding_requests: 16
deadlock_threshold: 500000
Seqeuncer config: Sequencer_6
controller: L1CacheController_6
version: 6
max_outstanding_requests: 16
deadlock_threshold: 500000
Seqeuncer config: Sequencer_7
controller: L1CacheController_7
version: 7
max_outstanding_requests: 16
deadlock_threshold: 500000
Network Configuration
---------------------
network: SIMPLE_NETWORK
topology: theTopology
virtual_net_0: active, unordered
virtual_net_1: active, unordered
virtual_net_2: active, unordered
virtual_net_3: inactive
virtual_net_4: inactive
Profiler Configuration
----------------------
periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
Real time: Jan/19/2010 17:15:39
Profiler Stats
--------------
Elapsed_time_in_seconds: 219
Elapsed_time_in_minutes: 3.65
Elapsed_time_in_hours: 0.0608333
Elapsed_time_in_days: 0.00253472
Virtual_time_in_seconds: 219.56
Virtual_time_in_minutes: 3.65933
Virtual_time_in_hours: 0.0609889
Virtual_time_in_days: 0.0025412
Ruby_current_time: 4504973
Ruby_start_time: 1
Ruby_cycles: 4504972
mbytes_resident: 157.109
mbytes_total: 1381.15
resident_ratio: 0.113758
Total_misses: 0
total_misses: 0 [ 0 0 0 0 0 0 0 0 ]
user_misses: 0 [ 0 0 0 0 0 0 0 0 ]
supervisor_misses: 0 [ 0 0 0 0 0 0 0 0 ]
ruby_cycles_executed: 36039784 [ 4504973 4504973 4504973 4504973 4504973 4504973 4504973 4504973 ]
transactions_started: 0 [ 0 0 0 0 0 0 0 0 ]
transactions_ended: 0 [ 0 0 0 0 0 0 0 0 ]
cycles_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ]
misses_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ]
Memory control MemoryControl_0:
memory_total_requests: 3005
memory_reads: 3005
memory_writes: 0
memory_refreshes: 249
memory_total_request_delays: 44377
memory_delays_per_request: 14.7677
memory_delays_in_input_queue: 455
memory_delays_behind_head_of_bank_queue: 5602
memory_delays_stalled_at_head_of_bank_queue: 38320
memory_stalls_for_bank_busy: 5925
memory_stalls_for_random_busy: 3962
memory_stalls_for_anti_starvation: 2593
memory_stalls_for_arbitration: 7799
memory_stalls_for_bus: 11753
memory_stalls_for_tfaw: 0
memory_stalls_for_read_write_turnaround: 0
memory_stalls_for_read_read_turnaround: 6288
accesses_per_bank: 94 95 94 95 95 94 91 93 92 95 94 95 96 93 95 93 92 93 92 93 93 93 94 95 93 96 94 95 94 93 96 95
Busy Controller Counts:
L2Cache-0:0 L2Cache-1:0
L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0
DMA-0:0
Directory-0:0
Busy Bank Count:0
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 747279 average: 5.5893 | standard deviation: 1.87929 | 0 2677 17977 57793 118759 170403 177953 124824 52770 12769 2104 651 477 583 776 1441 5322 ]
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
miss_latency: [binsize: 8 max: 1069 count: 747275 average: 29.6123 | standard deviation: 22.3575 | 27052 0 0 716077 295 143 361 256 13 6 4 10 2 11 5 5 1 2 3 4 1 2 3 164 216 145 112 107 103 92 66 72 72 86 76 73 71 65 82 55 47 55 79 45 56 40 35 49 50 45 32 41 33 41 44 27 44 37 34 38 33 24 33 34 28 21 23 24 18 18 12 16 22 20 9 9 7 12 11 8 6 8 6 9 6 1 4 1 7 3 2 3 3 2 8 1 7 2 2 2 1 2 1 2 1 0 1 2 5 2 1 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_2: [binsize: 8 max: 1069 count: 485700 average: 29.3069 | standard deviation: 22.5252 | 17456 0 0 465505 295 1 246 160 7 6 0 8 1 7 5 0 0 1 2 4 0 1 2 111 145 94 63 67 70 67 45 42 41 53 45 49 47 45 60 38 32 35 49 26 44 23 22 40 37 29 25 20 24 31 29 16 28 26 21 33 18 18 20 19 25 15 13 15 12 13 8 12 17 12 7 4 3 8 5 8 4 4 4 9 2 1 4 1 4 2 1 2 2 0 7 1 5 1 2 0 0 0 1 1 1 0 1 1 4 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_3: [binsize: 8 max: 1059 count: 261575 average: 30.1795 | standard deviation: 22.0315 | 9596 0 0 250572 0 142 115 96 6 0 4 2 1 4 0 5 1 1 1 0 1 1 1 53 71 51 49 40 33 25 21 30 31 33 31 24 24 20 22 17 15 20 30 19 12 17 13 9 13 16 7 21 9 10 15 11 16 11 13 5 15 6 13 15 3 6 10 9 6 5 4 4 5 8 2 5 4 4 6 0 2 4 2 0 4 0 0 0 3 1 1 1 1 2 1 0 2 1 0 2 1 2 0 1 0 0 0 1 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Request vs. RubySystem State Profile
--------------------------------
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Message Delayed Cycles
----------------------
Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Resource Usage
--------------
page_size: 4096
user_time: 219
system_time: 0
page_reclaims: 41446
page_faults: 0
swaps: 0
block_inputs: 0
block_outputs: 0
Network Stats
-------------
switch_0_inlinks: 2
switch_0_outlinks: 2
links_utilized_percent_switch_0: 5.79466
links_utilized_percent_switch_0_link_0: 1.99838 bw: 640000 base_latency: 1
links_utilized_percent_switch_0_link_1: 9.59095 bw: 160000 base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 3005 216360 [ 0 0 3005 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 717218 51639696 [ 0 0 717218 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Writeback_Control: 720095 5760760 [ 720095 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Request_Control: 720227 5761816 [ 720227 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Writeback_Data: 720094 51846768 [ 0 0 720094 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Writeback_Control: 720099 5760792 [ 720099 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Unblock_Control: 720222 5761776 [ 0 0 720222 0 0 ] base_latency: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
links_utilized_percent_switch_1: 0
links_utilized_percent_switch_1_link_0: 0 bw: 640000 base_latency: 1
links_utilized_percent_switch_1_link_1: 0 bw: 160000 base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
links_utilized_percent_switch_2: 0
links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1
links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1
switch_3_inlinks: 2
switch_3_outlinks: 2
links_utilized_percent_switch_3: 0
links_utilized_percent_switch_3_link_0: 0 bw: 640000 base_latency: 1
links_utilized_percent_switch_3_link_1: 0 bw: 160000 base_latency: 1
switch_4_inlinks: 2
switch_4_outlinks: 2
links_utilized_percent_switch_4: 0
links_utilized_percent_switch_4_link_0: 0 bw: 640000 base_latency: 1
links_utilized_percent_switch_4_link_1: 0 bw: 160000 base_latency: 1
switch_5_inlinks: 2
switch_5_outlinks: 2
links_utilized_percent_switch_5: 0
links_utilized_percent_switch_5_link_0: 0 bw: 640000 base_latency: 1
links_utilized_percent_switch_5_link_1: 0 bw: 160000 base_latency: 1
switch_6_inlinks: 2
switch_6_outlinks: 2
links_utilized_percent_switch_6: 0
links_utilized_percent_switch_6_link_0: 0 bw: 640000 base_latency: 1
links_utilized_percent_switch_6_link_1: 0 bw: 160000 base_latency: 1
switch_7_inlinks: 2
switch_7_outlinks: 2
links_utilized_percent_switch_7: 0
links_utilized_percent_switch_7_link_0: 0 bw: 640000 base_latency: 1
links_utilized_percent_switch_7_link_1: 0 bw: 160000 base_latency: 1
switch_8_inlinks: 2
switch_8_outlinks: 2
links_utilized_percent_switch_8: 2.59681
links_utilized_percent_switch_8_link_0: 1.20053 bw: 640000 base_latency: 1
links_utilized_percent_switch_8_link_1: 3.99309 bw: 160000 base_latency: 1
outgoing_messages_switch_8_link_0_Request_Control: 359480 2875840 [ 359480 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_8_link_0_Response_Data: 1508 108576 [ 0 0 1508 0 0 ] base_latency: 1
outgoing_messages_switch_8_link_0_Writeback_Data: 359415 25877880 [ 0 0 359415 0 0 ] base_latency: 1
outgoing_messages_switch_8_link_0_Writeback_Control: 359416 2875328 [ 359416 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_8_link_0_Unblock_Control: 359479 2875832 [ 0 0 359479 0 0 ] base_latency: 1
outgoing_messages_switch_8_link_1_Request_Control: 1508 12064 [ 0 1508 0 0 0 ] base_latency: 1
outgoing_messages_switch_8_link_1_Response_Data: 1508 108576 [ 0 0 1508 0 0 ] base_latency: 1
outgoing_messages_switch_8_link_1_ResponseL2hit_Data: 357972 25773984 [ 0 0 357972 0 0 ] base_latency: 1
outgoing_messages_switch_8_link_1_Writeback_Control: 359416 2875328 [ 359416 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_8_link_1_Unblock_Control: 1508 12064 [ 0 0 1508 0 0 ] base_latency: 1
switch_9_inlinks: 2
switch_9_outlinks: 2
links_utilized_percent_switch_9: 2.6059
links_utilized_percent_switch_9_link_0: 1.20471 bw: 640000 base_latency: 1
links_utilized_percent_switch_9_link_1: 4.00709 bw: 160000 base_latency: 1
outgoing_messages_switch_9_link_0_Request_Control: 360746 2885968 [ 360746 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_9_link_0_Response_Data: 1497 107784 [ 0 0 1497 0 0 ] base_latency: 1
outgoing_messages_switch_9_link_0_Writeback_Data: 360679 25968888 [ 0 0 360679 0 0 ] base_latency: 1
outgoing_messages_switch_9_link_0_Writeback_Control: 360682 2885456 [ 360682 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_9_link_0_Unblock_Control: 360743 2885944 [ 0 0 360743 0 0 ] base_latency: 1
outgoing_messages_switch_9_link_1_Request_Control: 1497 11976 [ 0 1497 0 0 0 ] base_latency: 1
outgoing_messages_switch_9_link_1_Response_Data: 1497 107784 [ 0 0 1497 0 0 ] base_latency: 1
outgoing_messages_switch_9_link_1_ResponseL2hit_Data: 359247 25865784 [ 0 0 359247 0 0 ] base_latency: 1
outgoing_messages_switch_9_link_1_Writeback_Control: 360680 2885440 [ 360680 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_9_link_1_Unblock_Control: 1497 11976 [ 0 0 1497 0 0 ] base_latency: 1
switch_10_inlinks: 2
switch_10_outlinks: 2
links_utilized_percent_switch_10: 0.0158422
links_utilized_percent_switch_10_link_0: 0.0016676 bw: 640000 base_latency: 1
links_utilized_percent_switch_10_link_1: 0.0300168 bw: 160000 base_latency: 1
outgoing_messages_switch_10_link_0_Request_Control: 3005 24040 [ 0 3005 0 0 0 ] base_latency: 1
outgoing_messages_switch_10_link_0_Unblock_Control: 3005 24040 [ 0 0 3005 0 0 ] base_latency: 1
outgoing_messages_switch_10_link_1_Response_Data: 3005 216360 [ 0 0 3005 0 0 ] base_latency: 1
switch_11_inlinks: 2
switch_11_outlinks: 2
links_utilized_percent_switch_11: 0
links_utilized_percent_switch_11_link_0: 0 bw: 640000 base_latency: 1
links_utilized_percent_switch_11_link_1: 0 bw: 160000 base_latency: 1
switch_12_inlinks: 12
switch_12_outlinks: 12
links_utilized_percent_switch_12: 1.46843
links_utilized_percent_switch_12_link_0: 7.99351 bw: 160000 base_latency: 1
links_utilized_percent_switch_12_link_1: 0 bw: 160000 base_latency: 1
links_utilized_percent_switch_12_link_2: 0 bw: 160000 base_latency: 1
links_utilized_percent_switch_12_link_3: 0 bw: 160000 base_latency: 1
links_utilized_percent_switch_12_link_4: 0 bw: 160000 base_latency: 1
links_utilized_percent_switch_12_link_5: 0 bw: 160000 base_latency: 1
links_utilized_percent_switch_12_link_6: 0 bw: 160000 base_latency: 1
links_utilized_percent_switch_12_link_7: 0 bw: 160000 base_latency: 1
links_utilized_percent_switch_12_link_8: 4.80212 bw: 160000 base_latency: 1
links_utilized_percent_switch_12_link_9: 4.81885 bw: 160000 base_latency: 1
links_utilized_percent_switch_12_link_10: 0.00667041 bw: 160000 base_latency: 1
links_utilized_percent_switch_12_link_11: 0 bw: 160000 base_latency: 1
outgoing_messages_switch_12_link_0_Response_Data: 3005 216360 [ 0 0 3005 0 0 ] base_latency: 1
outgoing_messages_switch_12_link_0_ResponseL2hit_Data: 717219 51639768 [ 0 0 717219 0 0 ] base_latency: 1
outgoing_messages_switch_12_link_0_Writeback_Control: 720096 5760768 [ 720096 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_12_link_8_Request_Control: 359480 2875840 [ 359480 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_12_link_8_Response_Data: 1508 108576 [ 0 0 1508 0 0 ] base_latency: 1
outgoing_messages_switch_12_link_8_Writeback_Data: 359415 25877880 [ 0 0 359415 0 0 ] base_latency: 1
outgoing_messages_switch_12_link_8_Writeback_Control: 359416 2875328 [ 359416 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_12_link_8_Unblock_Control: 359479 2875832 [ 0 0 359479 0 0 ] base_latency: 1
outgoing_messages_switch_12_link_9_Request_Control: 360746 2885968 [ 360746 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_12_link_9_Response_Data: 1497 107784 [ 0 0 1497 0 0 ] base_latency: 1
outgoing_messages_switch_12_link_9_Writeback_Data: 360679 25968888 [ 0 0 360679 0 0 ] base_latency: 1
outgoing_messages_switch_12_link_9_Writeback_Control: 360682 2885456 [ 360682 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_12_link_9_Unblock_Control: 360743 2885944 [ 0 0 360743 0 0 ] base_latency: 1
outgoing_messages_switch_12_link_10_Request_Control: 3005 24040 [ 0 3005 0 0 0 ] base_latency: 1
outgoing_messages_switch_12_link_10_Unblock_Control: 3005 24040 [ 0 0 3005 0 0 ] base_latency: 1
Sequencer: Sequencer_0
store_waiting_on_load_cycles: 281
store_waiting_on_store_cycles: 133
load_waiting_on_load_cycles: 459
load_waiting_on_store_cycles: 265
Sequencer: Sequencer_1
store_waiting_on_load_cycles: 0
store_waiting_on_store_cycles: 0
load_waiting_on_load_cycles: 0
load_waiting_on_store_cycles: 0
Sequencer: Sequencer_2
store_waiting_on_load_cycles: 0
store_waiting_on_store_cycles: 0
load_waiting_on_load_cycles: 0
load_waiting_on_store_cycles: 0
Sequencer: Sequencer_3
store_waiting_on_load_cycles: 0
store_waiting_on_store_cycles: 0
load_waiting_on_load_cycles: 0
load_waiting_on_store_cycles: 0
Sequencer: Sequencer_4
store_waiting_on_load_cycles: 0
store_waiting_on_store_cycles: 0
load_waiting_on_load_cycles: 0
load_waiting_on_store_cycles: 0
Sequencer: Sequencer_5
store_waiting_on_load_cycles: 0
store_waiting_on_store_cycles: 0
load_waiting_on_load_cycles: 0
load_waiting_on_store_cycles: 0
Sequencer: Sequencer_6
store_waiting_on_load_cycles: 0
store_waiting_on_store_cycles: 0
load_waiting_on_load_cycles: 0
load_waiting_on_store_cycles: 0
Sequencer: Sequencer_7
store_waiting_on_load_cycles: 0
store_waiting_on_store_cycles: 0
load_waiting_on_load_cycles: 0
load_waiting_on_store_cycles: 0
l1d_0 cache stats:
l1d_0_total_misses: 0
l1d_0_total_demand_misses: 0
l1d_0_total_prefetches: 0
l1d_0_total_sw_prefetches: 0
l1d_0_total_hw_prefetches: 0
l1d_0_misses_per_transaction: nan
l1d_0_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
l1d_1 cache stats:
l1d_1_total_misses: 0
l1d_1_total_demand_misses: 0
l1d_1_total_prefetches: 0
l1d_1_total_sw_prefetches: 0
l1d_1_total_hw_prefetches: 0
l1d_1_misses_per_transaction: nan
l1d_1_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
l1d_2 cache stats:
l1d_2_total_misses: 0
l1d_2_total_demand_misses: 0
l1d_2_total_prefetches: 0
l1d_2_total_sw_prefetches: 0
l1d_2_total_hw_prefetches: 0
l1d_2_misses_per_transaction: nan
l1d_2_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
l1d_3 cache stats:
l1d_3_total_misses: 0
l1d_3_total_demand_misses: 0
l1d_3_total_prefetches: 0
l1d_3_total_sw_prefetches: 0
l1d_3_total_hw_prefetches: 0
l1d_3_misses_per_transaction: nan
l1d_3_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
l1d_4 cache stats:
l1d_4_total_misses: 0
l1d_4_total_demand_misses: 0
l1d_4_total_prefetches: 0
l1d_4_total_sw_prefetches: 0
l1d_4_total_hw_prefetches: 0
l1d_4_misses_per_transaction: nan
l1d_4_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
l1d_5 cache stats:
l1d_5_total_misses: 0
l1d_5_total_demand_misses: 0
l1d_5_total_prefetches: 0
l1d_5_total_sw_prefetches: 0
l1d_5_total_hw_prefetches: 0
l1d_5_misses_per_transaction: nan
l1d_5_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
l1d_6 cache stats:
l1d_6_total_misses: 0
l1d_6_total_demand_misses: 0
l1d_6_total_prefetches: 0
l1d_6_total_sw_prefetches: 0
l1d_6_total_hw_prefetches: 0
l1d_6_misses_per_transaction: nan
l1d_6_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
l1d_7 cache stats:
l1d_7_total_misses: 0
l1d_7_total_demand_misses: 0
l1d_7_total_prefetches: 0
l1d_7_total_sw_prefetches: 0
l1d_7_total_hw_prefetches: 0
l1d_7_misses_per_transaction: nan
l1d_7_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
l1i_0 cache stats:
l1i_0_total_misses: 0
l1i_0_total_demand_misses: 0
l1i_0_total_prefetches: 0
l1i_0_total_sw_prefetches: 0
l1i_0_total_hw_prefetches: 0
l1i_0_misses_per_transaction: nan
l1i_0_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
l1i_1 cache stats:
l1i_1_total_misses: 0
l1i_1_total_demand_misses: 0
l1i_1_total_prefetches: 0
l1i_1_total_sw_prefetches: 0
l1i_1_total_hw_prefetches: 0
l1i_1_misses_per_transaction: nan
l1i_1_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
l1i_2 cache stats:
l1i_2_total_misses: 0
l1i_2_total_demand_misses: 0
l1i_2_total_prefetches: 0
l1i_2_total_sw_prefetches: 0
l1i_2_total_hw_prefetches: 0
l1i_2_misses_per_transaction: nan
l1i_2_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
l1i_3 cache stats:
l1i_3_total_misses: 0
l1i_3_total_demand_misses: 0
l1i_3_total_prefetches: 0
l1i_3_total_sw_prefetches: 0
l1i_3_total_hw_prefetches: 0
l1i_3_misses_per_transaction: nan
l1i_3_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
l1i_4 cache stats:
l1i_4_total_misses: 0
l1i_4_total_demand_misses: 0
l1i_4_total_prefetches: 0
l1i_4_total_sw_prefetches: 0
l1i_4_total_hw_prefetches: 0
l1i_4_misses_per_transaction: nan
l1i_4_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
l1i_5 cache stats:
l1i_5_total_misses: 0
l1i_5_total_demand_misses: 0
l1i_5_total_prefetches: 0
l1i_5_total_sw_prefetches: 0
l1i_5_total_hw_prefetches: 0
l1i_5_misses_per_transaction: nan
l1i_5_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
l1i_6 cache stats:
l1i_6_total_misses: 0
l1i_6_total_demand_misses: 0
l1i_6_total_prefetches: 0
l1i_6_total_sw_prefetches: 0
l1i_6_total_hw_prefetches: 0
l1i_6_misses_per_transaction: nan
l1i_6_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
l1i_7 cache stats:
l1i_7_total_misses: 0
l1i_7_total_demand_misses: 0
l1i_7_total_prefetches: 0
l1i_7_total_sw_prefetches: 0
l1i_7_total_hw_prefetches: 0
l1i_7_misses_per_transaction: nan
l1i_7_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
l2u_0 cache stats:
l2u_0_total_misses: 0
l2u_0_total_demand_misses: 0
l2u_0_total_prefetches: 0
l2u_0_total_sw_prefetches: 0
l2u_0_total_hw_prefetches: 0
l2u_0_misses_per_transaction: nan
l2u_0_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
l2u_1 cache stats:
l2u_1_total_misses: 0
l2u_1_total_demand_misses: 0
l2u_1_total_prefetches: 0
l2u_1_total_sw_prefetches: 0
l2u_1_total_hw_prefetches: 0
l2u_1_misses_per_transaction: nan
l2u_1_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
--- DMA 0 ---
- Event Counts -
ReadRequest 0
WriteRequest 0
Data 0
DMA_Ack 0
Inv_Ack 0
All_Acks 0
- Transitions -
READY ReadRequest 0 <--
READY WriteRequest 0 <--
BUSY_RD Data 0 <--
BUSY_RD Inv_Ack 0 <--
BUSY_RD All_Acks 0 <--
BUSY_WR DMA_Ack 0 <--
BUSY_WR Inv_Ack 0 <--
BUSY_WR All_Acks 0 <--
--- Directory 0 ---
- Event Counts -
GETX 1022
GETS 1983
PUTX 0
PUTO 0
PUTO_SHARERS 0
Unblock 0
Last_Unblock 0
Exclusive_Unblock 3005
Clean_Writeback 0
Dirty_Writeback 0
Memory_Data 3005
Memory_Ack 0
DMA_READ 0
DMA_WRITE 0
Data 0
- Transitions -
I GETX 1022
I GETS 1983
I PUTX 0 <--
I PUTO 0 <--
I Memory_Data 0 <--
I Memory_Ack 0 <--
I DMA_READ 0 <--
I DMA_WRITE 0 <--
S GETX 0 <--
S GETS 0 <--
S PUTX 0 <--
S PUTO 0 <--
S Memory_Data 0 <--
S Memory_Ack 0 <--
S DMA_READ 0 <--
S DMA_WRITE 0 <--
O GETX 0 <--
O GETS 0 <--
O PUTX 0 <--
O PUTO 0 <--
O PUTO_SHARERS 0 <--
O Memory_Data 0 <--
O Memory_Ack 0 <--
O DMA_READ 0 <--
O DMA_WRITE 0 <--
M GETX 0 <--
M GETS 0 <--
M PUTX 0 <--
M PUTO 0 <--
M PUTO_SHARERS 0 <--
M Memory_Data 0 <--
M Memory_Ack 0 <--
M DMA_READ 0 <--
M DMA_WRITE 0 <--
IS GETX 0 <--
IS GETS 0 <--
IS PUTX 0 <--
IS PUTO 0 <--
IS PUTO_SHARERS 0 <--
IS Unblock 0 <--
IS Exclusive_Unblock 1983
IS Memory_Data 1983
IS Memory_Ack 0 <--
IS DMA_READ 0 <--
IS DMA_WRITE 0 <--
SS GETX 0 <--
SS GETS 0 <--
SS PUTX 0 <--
SS PUTO 0 <--
SS PUTO_SHARERS 0 <--
SS Unblock 0 <--
SS Last_Unblock 0 <--
SS Memory_Data 0 <--
SS Memory_Ack 0 <--
SS DMA_READ 0 <--
SS DMA_WRITE 0 <--
OO GETX 0 <--
OO GETS 0 <--
OO PUTX 0 <--
OO PUTO 0 <--
OO PUTO_SHARERS 0 <--
OO Unblock 0 <--
OO Last_Unblock 0 <--
OO Memory_Data 0 <--
OO Memory_Ack 0 <--
OO DMA_READ 0 <--
OO DMA_WRITE 0 <--
MO GETX 0 <--
MO GETS 0 <--
MO PUTX 0 <--
MO PUTO 0 <--
MO PUTO_SHARERS 0 <--
MO Unblock 0 <--
MO Exclusive_Unblock 0 <--
MO Memory_Data 0 <--
MO Memory_Ack 0 <--
MO DMA_READ 0 <--
MO DMA_WRITE 0 <--
MM GETX 0 <--
MM GETS 0 <--
MM PUTX 0 <--
MM PUTO 0 <--
MM PUTO_SHARERS 0 <--
MM Exclusive_Unblock 1022
MM Memory_Data 1022
MM Memory_Ack 0 <--
MM DMA_READ 0 <--
MM DMA_WRITE 0 <--
MI GETX 0 <--
MI GETS 0 <--
MI PUTX 0 <--
MI PUTO 0 <--
MI PUTO_SHARERS 0 <--
MI Unblock 0 <--
MI Clean_Writeback 0 <--
MI Dirty_Writeback 0 <--
MI Memory_Data 0 <--
MI Memory_Ack 0 <--
MI DMA_READ 0 <--
MI DMA_WRITE 0 <--
MIS GETX 0 <--
MIS GETS 0 <--
MIS PUTX 0 <--
MIS PUTO 0 <--
MIS PUTO_SHARERS 0 <--
MIS Unblock 0 <--
MIS Clean_Writeback 0 <--
MIS Dirty_Writeback 0 <--
MIS Memory_Data 0 <--
MIS Memory_Ack 0 <--
MIS DMA_READ 0 <--
MIS DMA_WRITE 0 <--
OS GETX 0 <--
OS GETS 0 <--
OS PUTX 0 <--
OS PUTO 0 <--
OS PUTO_SHARERS 0 <--
OS Unblock 0 <--
OS Clean_Writeback 0 <--
OS Dirty_Writeback 0 <--
OS Memory_Data 0 <--
OS Memory_Ack 0 <--
OS DMA_READ 0 <--
OS DMA_WRITE 0 <--
OSS GETX 0 <--
OSS GETS 0 <--
OSS PUTX 0 <--
OSS PUTO 0 <--
OSS PUTO_SHARERS 0 <--
OSS Unblock 0 <--
OSS Clean_Writeback 0 <--
OSS Dirty_Writeback 0 <--
OSS Memory_Data 0 <--
OSS Memory_Ack 0 <--
OSS DMA_READ 0 <--
OSS DMA_WRITE 0 <--
XI_M GETX 0 <--
XI_M GETS 0 <--
XI_M PUTX 0 <--
XI_M PUTO 0 <--
XI_M PUTO_SHARERS 0 <--
XI_M Memory_Data 0 <--
XI_M Memory_Ack 0 <--
XI_M DMA_READ 0 <--
XI_M DMA_WRITE 0 <--
XI_U GETX 0 <--
XI_U GETS 0 <--
XI_U PUTX 0 <--
XI_U PUTO 0 <--
XI_U PUTO_SHARERS 0 <--
XI_U Exclusive_Unblock 0 <--
XI_U Memory_Ack 0 <--
XI_U DMA_READ 0 <--
XI_U DMA_WRITE 0 <--
OI_D GETX 0 <--
OI_D GETS 0 <--
OI_D PUTX 0 <--
OI_D PUTO 0 <--
OI_D PUTO_SHARERS 0 <--
OI_D DMA_READ 0 <--
OI_D DMA_WRITE 0 <--
OI_D Data 0 <--
--- L1Cache 0 ---
- Event Counts -
Load 486730
Ifetch 0
Store 262117
L1_Replacement 721707
Own_GETX 0
Fwd_GETX 0
Fwd_GETS 0
Fwd_DMA 0
Inv 0
Ack 0
Data 0
Exclusive_Data 720223
Writeback_Ack 0
Writeback_Ack_Data 720095
Writeback_Nack 0
All_acks 251979
Use_Timeout 720212
- Transitions -
I Load 468247
I Ifetch 0 <--
I Store 251980
I L1_Replacement 0 <--
I Inv 0 <--
S Load 0 <--
S Ifetch 0 <--
S Store 0 <--
S L1_Replacement 0 <--
S Fwd_GETS 0 <--
S Fwd_DMA 0 <--
S Inv 0 <--
O Load 0 <--
O Ifetch 0 <--
O Store 0 <--
O L1_Replacement 0 <--
O Fwd_GETX 0 <--
O Fwd_GETS 0 <--
O Fwd_DMA 0 <--
M Load 10418
M Ifetch 0 <--
M Store 5725
M L1_Replacement 462033
M Fwd_GETX 0 <--
M Fwd_GETS 0 <--
M Fwd_DMA 0 <--
M_W Load 758
M_W Ifetch 0 <--
M_W Store 401
M_W L1_Replacement 22
M_W Own_GETX 0 <--
M_W Fwd_GETX 0 <--
M_W Fwd_GETS 0 <--
M_W Fwd_DMA 0 <--
M_W Inv 0 <--
M_W Use_Timeout 467835
MM Load 5853
MM Ifetch 0 <--
MM Store 3236
MM L1_Replacement 258066
MM Fwd_GETX 0 <--
MM Fwd_GETS 0 <--
MM Fwd_DMA 0 <--
MM_W Load 427
MM_W Ifetch 0 <--
MM_W Store 234
MM_W L1_Replacement 11
MM_W Own_GETX 0 <--
MM_W Fwd_GETX 0 <--
MM_W Fwd_GETS 0 <--
MM_W Fwd_DMA 0 <--
MM_W Inv 0 <--
MM_W Use_Timeout 252377
IM Load 0 <--
IM Ifetch 0 <--
IM Store 0 <--
IM L1_Replacement 400
IM Inv 0 <--
IM Ack 0 <--
IM Data 0 <--
IM Exclusive_Data 251979
SM Load 0 <--
SM Ifetch 0 <--
SM Store 0 <--
SM L1_Replacement 0 <--
SM Fwd_GETS 0 <--
SM Fwd_DMA 0 <--
SM Inv 0 <--
SM Ack 0 <--
SM Data 0 <--
SM Exclusive_Data 0 <--
OM Load 0 <--
OM Ifetch 0 <--
OM Store 0 <--
OM L1_Replacement 1
OM Own_GETX 0 <--
OM Fwd_GETX 0 <--
OM Fwd_GETS 0 <--
OM Fwd_DMA 0 <--
OM Ack 0 <--
OM All_acks 251979
IS Load 0 <--
IS Ifetch 0 <--
IS Store 0 <--
IS L1_Replacement 1174
IS Inv 0 <--
IS Data 0 <--
IS Exclusive_Data 468244
SI Load 0 <--
SI Ifetch 0 <--
SI Store 0 <--
SI L1_Replacement 0 <--
SI Fwd_GETS 0 <--
SI Fwd_DMA 0 <--
SI Inv 0 <--
SI Writeback_Ack 0 <--
SI Writeback_Ack_Data 0 <--
SI Writeback_Nack 0 <--
OI Load 0 <--
OI Ifetch 0 <--
OI Store 0 <--
OI L1_Replacement 0 <--
OI Fwd_GETX 0 <--
OI Fwd_GETS 0 <--
OI Fwd_DMA 0 <--
OI Writeback_Ack 0 <--
OI Writeback_Ack_Data 0 <--
OI Writeback_Nack 0 <--
MI Load 1027
MI Ifetch 0 <--
MI Store 541
MI L1_Replacement 0 <--
MI Fwd_GETX 0 <--
MI Fwd_GETS 0 <--
MI Fwd_DMA 0 <--
MI Writeback_Ack 0 <--
MI Writeback_Ack_Data 720095
MI Writeback_Nack 0 <--
II Load 0 <--
II Ifetch 0 <--
II Store 0 <--
II L1_Replacement 0 <--
II Inv 0 <--
II Writeback_Ack 0 <--
II Writeback_Ack_Data 0 <--
II Writeback_Nack 0 <--
--- L1Cache 1 ---
- Event Counts -
Load 0
Ifetch 0
Store 0
L1_Replacement 0
Own_GETX 0
Fwd_GETX 0
Fwd_GETS 0
Fwd_DMA 0
Inv 0
Ack 0
Data 0
Exclusive_Data 0
Writeback_Ack 0
Writeback_Ack_Data 0
Writeback_Nack 0
All_acks 0
Use_Timeout 0
- Transitions -
I Load 0 <--
I Ifetch 0 <--
I Store 0 <--
I L1_Replacement 0 <--
I Inv 0 <--
S Load 0 <--
S Ifetch 0 <--
S Store 0 <--
S L1_Replacement 0 <--
S Fwd_GETS 0 <--
S Fwd_DMA 0 <--
S Inv 0 <--
O Load 0 <--
O Ifetch 0 <--
O Store 0 <--
O L1_Replacement 0 <--
O Fwd_GETX 0 <--
O Fwd_GETS 0 <--
O Fwd_DMA 0 <--
M Load 0 <--
M Ifetch 0 <--
M Store 0 <--
M L1_Replacement 0 <--
M Fwd_GETX 0 <--
M Fwd_GETS 0 <--
M Fwd_DMA 0 <--
M_W Load 0 <--
M_W Ifetch 0 <--
M_W Store 0 <--
M_W L1_Replacement 0 <--
M_W Own_GETX 0 <--
M_W Fwd_GETX 0 <--
M_W Fwd_GETS 0 <--
M_W Fwd_DMA 0 <--
M_W Inv 0 <--
M_W Use_Timeout 0 <--
MM Load 0 <--
MM Ifetch 0 <--
MM Store 0 <--
MM L1_Replacement 0 <--
MM Fwd_GETX 0 <--
MM Fwd_GETS 0 <--
MM Fwd_DMA 0 <--
MM_W Load 0 <--
MM_W Ifetch 0 <--
MM_W Store 0 <--
MM_W L1_Replacement 0 <--
MM_W Own_GETX 0 <--
MM_W Fwd_GETX 0 <--
MM_W Fwd_GETS 0 <--
MM_W Fwd_DMA 0 <--
MM_W Inv 0 <--
MM_W Use_Timeout 0 <--
IM Load 0 <--
IM Ifetch 0 <--
IM Store 0 <--
IM L1_Replacement 0 <--
IM Inv 0 <--
IM Ack 0 <--
IM Data 0 <--
IM Exclusive_Data 0 <--
SM Load 0 <--
SM Ifetch 0 <--
SM Store 0 <--
SM L1_Replacement 0 <--
SM Fwd_GETS 0 <--
SM Fwd_DMA 0 <--
SM Inv 0 <--
SM Ack 0 <--
SM Data 0 <--
SM Exclusive_Data 0 <--
OM Load 0 <--
OM Ifetch 0 <--
OM Store 0 <--
OM L1_Replacement 0 <--
OM Own_GETX 0 <--
OM Fwd_GETX 0 <--
OM Fwd_GETS 0 <--
OM Fwd_DMA 0 <--
OM Ack 0 <--
OM All_acks 0 <--
IS Load 0 <--
IS Ifetch 0 <--
IS Store 0 <--
IS L1_Replacement 0 <--
IS Inv 0 <--
IS Data 0 <--
IS Exclusive_Data 0 <--
SI Load 0 <--
SI Ifetch 0 <--
SI Store 0 <--
SI L1_Replacement 0 <--
SI Fwd_GETS 0 <--
SI Fwd_DMA 0 <--
SI Inv 0 <--
SI Writeback_Ack 0 <--
SI Writeback_Ack_Data 0 <--
SI Writeback_Nack 0 <--
OI Load 0 <--
OI Ifetch 0 <--
OI Store 0 <--
OI L1_Replacement 0 <--
OI Fwd_GETX 0 <--
OI Fwd_GETS 0 <--
OI Fwd_DMA 0 <--
OI Writeback_Ack 0 <--
OI Writeback_Ack_Data 0 <--
OI Writeback_Nack 0 <--
MI Load 0 <--
MI Ifetch 0 <--
MI Store 0 <--
MI L1_Replacement 0 <--
MI Fwd_GETX 0 <--
MI Fwd_GETS 0 <--
MI Fwd_DMA 0 <--
MI Writeback_Ack 0 <--
MI Writeback_Ack_Data 0 <--
MI Writeback_Nack 0 <--
II Load 0 <--
II Ifetch 0 <--
II Store 0 <--
II L1_Replacement 0 <--
II Inv 0 <--
II Writeback_Ack 0 <--
II Writeback_Ack_Data 0 <--
II Writeback_Nack 0 <--
--- L1Cache 2 ---
- Event Counts -
Load 0
Ifetch 0
Store 0
L1_Replacement 0
Own_GETX 0
Fwd_GETX 0
Fwd_GETS 0
Fwd_DMA 0
Inv 0
Ack 0
Data 0
Exclusive_Data 0
Writeback_Ack 0
Writeback_Ack_Data 0
Writeback_Nack 0
All_acks 0
Use_Timeout 0
- Transitions -
I Load 0 <--
I Ifetch 0 <--
I Store 0 <--
I L1_Replacement 0 <--
I Inv 0 <--
S Load 0 <--
S Ifetch 0 <--
S Store 0 <--
S L1_Replacement 0 <--
S Fwd_GETS 0 <--
S Fwd_DMA 0 <--
S Inv 0 <--
O Load 0 <--
O Ifetch 0 <--
O Store 0 <--
O L1_Replacement 0 <--
O Fwd_GETX 0 <--
O Fwd_GETS 0 <--
O Fwd_DMA 0 <--
M Load 0 <--
M Ifetch 0 <--
M Store 0 <--
M L1_Replacement 0 <--
M Fwd_GETX 0 <--
M Fwd_GETS 0 <--
M Fwd_DMA 0 <--
M_W Load 0 <--
M_W Ifetch 0 <--
M_W Store 0 <--
M_W L1_Replacement 0 <--
M_W Own_GETX 0 <--
M_W Fwd_GETX 0 <--
M_W Fwd_GETS 0 <--
M_W Fwd_DMA 0 <--
M_W Inv 0 <--
M_W Use_Timeout 0 <--
MM Load 0 <--
MM Ifetch 0 <--
MM Store 0 <--
MM L1_Replacement 0 <--
MM Fwd_GETX 0 <--
MM Fwd_GETS 0 <--
MM Fwd_DMA 0 <--
MM_W Load 0 <--
MM_W Ifetch 0 <--
MM_W Store 0 <--
MM_W L1_Replacement 0 <--
MM_W Own_GETX 0 <--
MM_W Fwd_GETX 0 <--
MM_W Fwd_GETS 0 <--
MM_W Fwd_DMA 0 <--
MM_W Inv 0 <--
MM_W Use_Timeout 0 <--
IM Load 0 <--
IM Ifetch 0 <--
IM Store 0 <--
IM L1_Replacement 0 <--
IM Inv 0 <--
IM Ack 0 <--
IM Data 0 <--
IM Exclusive_Data 0 <--
SM Load 0 <--
SM Ifetch 0 <--
SM Store 0 <--
SM L1_Replacement 0 <--
SM Fwd_GETS 0 <--
SM Fwd_DMA 0 <--
SM Inv 0 <--
SM Ack 0 <--
SM Data 0 <--
SM Exclusive_Data 0 <--
OM Load 0 <--
OM Ifetch 0 <--
OM Store 0 <--
OM L1_Replacement 0 <--
OM Own_GETX 0 <--
OM Fwd_GETX 0 <--
OM Fwd_GETS 0 <--
OM Fwd_DMA 0 <--
OM Ack 0 <--
OM All_acks 0 <--
IS Load 0 <--
IS Ifetch 0 <--
IS Store 0 <--
IS L1_Replacement 0 <--
IS Inv 0 <--
IS Data 0 <--
IS Exclusive_Data 0 <--
SI Load 0 <--
SI Ifetch 0 <--
SI Store 0 <--
SI L1_Replacement 0 <--
SI Fwd_GETS 0 <--
SI Fwd_DMA 0 <--
SI Inv 0 <--
SI Writeback_Ack 0 <--
SI Writeback_Ack_Data 0 <--
SI Writeback_Nack 0 <--
OI Load 0 <--
OI Ifetch 0 <--
OI Store 0 <--
OI L1_Replacement 0 <--
OI Fwd_GETX 0 <--
OI Fwd_GETS 0 <--
OI Fwd_DMA 0 <--
OI Writeback_Ack 0 <--
OI Writeback_Ack_Data 0 <--
OI Writeback_Nack 0 <--
MI Load 0 <--
MI Ifetch 0 <--
MI Store 0 <--
MI L1_Replacement 0 <--
MI Fwd_GETX 0 <--
MI Fwd_GETS 0 <--
MI Fwd_DMA 0 <--
MI Writeback_Ack 0 <--
MI Writeback_Ack_Data 0 <--
MI Writeback_Nack 0 <--
II Load 0 <--
II Ifetch 0 <--
II Store 0 <--
II L1_Replacement 0 <--
II Inv 0 <--
II Writeback_Ack 0 <--
II Writeback_Ack_Data 0 <--
II Writeback_Nack 0 <--
--- L1Cache 3 ---
- Event Counts -
Load 0
Ifetch 0
Store 0
L1_Replacement 0
Own_GETX 0
Fwd_GETX 0
Fwd_GETS 0
Fwd_DMA 0
Inv 0
Ack 0
Data 0
Exclusive_Data 0
Writeback_Ack 0
Writeback_Ack_Data 0
Writeback_Nack 0
All_acks 0
Use_Timeout 0
- Transitions -
I Load 0 <--
I Ifetch 0 <--
I Store 0 <--
I L1_Replacement 0 <--
I Inv 0 <--
S Load 0 <--
S Ifetch 0 <--
S Store 0 <--
S L1_Replacement 0 <--
S Fwd_GETS 0 <--
S Fwd_DMA 0 <--
S Inv 0 <--
O Load 0 <--
O Ifetch 0 <--
O Store 0 <--
O L1_Replacement 0 <--
O Fwd_GETX 0 <--
O Fwd_GETS 0 <--
O Fwd_DMA 0 <--
M Load 0 <--
M Ifetch 0 <--
M Store 0 <--
M L1_Replacement 0 <--
M Fwd_GETX 0 <--
M Fwd_GETS 0 <--
M Fwd_DMA 0 <--
M_W Load 0 <--
M_W Ifetch 0 <--
M_W Store 0 <--
M_W L1_Replacement 0 <--
M_W Own_GETX 0 <--
M_W Fwd_GETX 0 <--
M_W Fwd_GETS 0 <--
M_W Fwd_DMA 0 <--
M_W Inv 0 <--
M_W Use_Timeout 0 <--
MM Load 0 <--
MM Ifetch 0 <--
MM Store 0 <--
MM L1_Replacement 0 <--
MM Fwd_GETX 0 <--
MM Fwd_GETS 0 <--
MM Fwd_DMA 0 <--
MM_W Load 0 <--
MM_W Ifetch 0 <--
MM_W Store 0 <--
MM_W L1_Replacement 0 <--
MM_W Own_GETX 0 <--
MM_W Fwd_GETX 0 <--
MM_W Fwd_GETS 0 <--
MM_W Fwd_DMA 0 <--
MM_W Inv 0 <--
MM_W Use_Timeout 0 <--
IM Load 0 <--
IM Ifetch 0 <--
IM Store 0 <--
IM L1_Replacement 0 <--
IM Inv 0 <--
IM Ack 0 <--
IM Data 0 <--
IM Exclusive_Data 0 <--
SM Load 0 <--
SM Ifetch 0 <--
SM Store 0 <--
SM L1_Replacement 0 <--
SM Fwd_GETS 0 <--
SM Fwd_DMA 0 <--
SM Inv 0 <--
SM Ack 0 <--
SM Data 0 <--
SM Exclusive_Data 0 <--
OM Load 0 <--
OM Ifetch 0 <--
OM Store 0 <--
OM L1_Replacement 0 <--
OM Own_GETX 0 <--
OM Fwd_GETX 0 <--
OM Fwd_GETS 0 <--
OM Fwd_DMA 0 <--
OM Ack 0 <--
OM All_acks 0 <--
IS Load 0 <--
IS Ifetch 0 <--
IS Store 0 <--
IS L1_Replacement 0 <--
IS Inv 0 <--
IS Data 0 <--
IS Exclusive_Data 0 <--
SI Load 0 <--
SI Ifetch 0 <--
SI Store 0 <--
SI L1_Replacement 0 <--
SI Fwd_GETS 0 <--
SI Fwd_DMA 0 <--
SI Inv 0 <--
SI Writeback_Ack 0 <--
SI Writeback_Ack_Data 0 <--
SI Writeback_Nack 0 <--
OI Load 0 <--
OI Ifetch 0 <--
OI Store 0 <--
OI L1_Replacement 0 <--
OI Fwd_GETX 0 <--
OI Fwd_GETS 0 <--
OI Fwd_DMA 0 <--
OI Writeback_Ack 0 <--
OI Writeback_Ack_Data 0 <--
OI Writeback_Nack 0 <--
MI Load 0 <--
MI Ifetch 0 <--
MI Store 0 <--
MI L1_Replacement 0 <--
MI Fwd_GETX 0 <--
MI Fwd_GETS 0 <--
MI Fwd_DMA 0 <--
MI Writeback_Ack 0 <--
MI Writeback_Ack_Data 0 <--
MI Writeback_Nack 0 <--
II Load 0 <--
II Ifetch 0 <--
II Store 0 <--
II L1_Replacement 0 <--
II Inv 0 <--
II Writeback_Ack 0 <--
II Writeback_Ack_Data 0 <--
II Writeback_Nack 0 <--
--- L1Cache 4 ---
- Event Counts -
Load 0
Ifetch 0
Store 0
L1_Replacement 0
Own_GETX 0
Fwd_GETX 0
Fwd_GETS 0
Fwd_DMA 0
Inv 0
Ack 0
Data 0
Exclusive_Data 0
Writeback_Ack 0
Writeback_Ack_Data 0
Writeback_Nack 0
All_acks 0
Use_Timeout 0
- Transitions -
I Load 0 <--
I Ifetch 0 <--
I Store 0 <--
I L1_Replacement 0 <--
I Inv 0 <--
S Load 0 <--
S Ifetch 0 <--
S Store 0 <--
S L1_Replacement 0 <--
S Fwd_GETS 0 <--
S Fwd_DMA 0 <--
S Inv 0 <--
O Load 0 <--
O Ifetch 0 <--
O Store 0 <--
O L1_Replacement 0 <--
O Fwd_GETX 0 <--
O Fwd_GETS 0 <--
O Fwd_DMA 0 <--
M Load 0 <--
M Ifetch 0 <--
M Store 0 <--
M L1_Replacement 0 <--
M Fwd_GETX 0 <--
M Fwd_GETS 0 <--
M Fwd_DMA 0 <--
M_W Load 0 <--
M_W Ifetch 0 <--
M_W Store 0 <--
M_W L1_Replacement 0 <--
M_W Own_GETX 0 <--
M_W Fwd_GETX 0 <--
M_W Fwd_GETS 0 <--
M_W Fwd_DMA 0 <--
M_W Inv 0 <--
M_W Use_Timeout 0 <--
MM Load 0 <--
MM Ifetch 0 <--
MM Store 0 <--
MM L1_Replacement 0 <--
MM Fwd_GETX 0 <--
MM Fwd_GETS 0 <--
MM Fwd_DMA 0 <--
MM_W Load 0 <--
MM_W Ifetch 0 <--
MM_W Store 0 <--
MM_W L1_Replacement 0 <--
MM_W Own_GETX 0 <--
MM_W Fwd_GETX 0 <--
MM_W Fwd_GETS 0 <--
MM_W Fwd_DMA 0 <--
MM_W Inv 0 <--
MM_W Use_Timeout 0 <--
IM Load 0 <--
IM Ifetch 0 <--
IM Store 0 <--
IM L1_Replacement 0 <--
IM Inv 0 <--
IM Ack 0 <--
IM Data 0 <--
IM Exclusive_Data 0 <--
SM Load 0 <--
SM Ifetch 0 <--
SM Store 0 <--
SM L1_Replacement 0 <--
SM Fwd_GETS 0 <--
SM Fwd_DMA 0 <--
SM Inv 0 <--
SM Ack 0 <--
SM Data 0 <--
SM Exclusive_Data 0 <--
OM Load 0 <--
OM Ifetch 0 <--
OM Store 0 <--
OM L1_Replacement 0 <--
OM Own_GETX 0 <--
OM Fwd_GETX 0 <--
OM Fwd_GETS 0 <--
OM Fwd_DMA 0 <--
OM Ack 0 <--
OM All_acks 0 <--
IS Load 0 <--
IS Ifetch 0 <--
IS Store 0 <--
IS L1_Replacement 0 <--
IS Inv 0 <--
IS Data 0 <--
IS Exclusive_Data 0 <--
SI Load 0 <--
SI Ifetch 0 <--
SI Store 0 <--
SI L1_Replacement 0 <--
SI Fwd_GETS 0 <--
SI Fwd_DMA 0 <--
SI Inv 0 <--
SI Writeback_Ack 0 <--
SI Writeback_Ack_Data 0 <--
SI Writeback_Nack 0 <--
OI Load 0 <--
OI Ifetch 0 <--
OI Store 0 <--
OI L1_Replacement 0 <--
OI Fwd_GETX 0 <--
OI Fwd_GETS 0 <--
OI Fwd_DMA 0 <--
OI Writeback_Ack 0 <--
OI Writeback_Ack_Data 0 <--
OI Writeback_Nack 0 <--
MI Load 0 <--
MI Ifetch 0 <--
MI Store 0 <--
MI L1_Replacement 0 <--
MI Fwd_GETX 0 <--
MI Fwd_GETS 0 <--
MI Fwd_DMA 0 <--
MI Writeback_Ack 0 <--
MI Writeback_Ack_Data 0 <--
MI Writeback_Nack 0 <--
II Load 0 <--
II Ifetch 0 <--
II Store 0 <--
II L1_Replacement 0 <--
II Inv 0 <--
II Writeback_Ack 0 <--
II Writeback_Ack_Data 0 <--
II Writeback_Nack 0 <--
--- L1Cache 5 ---
- Event Counts -
Load 0
Ifetch 0
Store 0
L1_Replacement 0
Own_GETX 0
Fwd_GETX 0
Fwd_GETS 0
Fwd_DMA 0
Inv 0
Ack 0
Data 0
Exclusive_Data 0
Writeback_Ack 0
Writeback_Ack_Data 0
Writeback_Nack 0
All_acks 0
Use_Timeout 0
- Transitions -
I Load 0 <--
I Ifetch 0 <--
I Store 0 <--
I L1_Replacement 0 <--
I Inv 0 <--
S Load 0 <--
S Ifetch 0 <--
S Store 0 <--
S L1_Replacement 0 <--
S Fwd_GETS 0 <--
S Fwd_DMA 0 <--
S Inv 0 <--
O Load 0 <--
O Ifetch 0 <--
O Store 0 <--
O L1_Replacement 0 <--
O Fwd_GETX 0 <--
O Fwd_GETS 0 <--
O Fwd_DMA 0 <--
M Load 0 <--
M Ifetch 0 <--
M Store 0 <--
M L1_Replacement 0 <--
M Fwd_GETX 0 <--
M Fwd_GETS 0 <--
M Fwd_DMA 0 <--
M_W Load 0 <--
M_W Ifetch 0 <--
M_W Store 0 <--
M_W L1_Replacement 0 <--
M_W Own_GETX 0 <--
M_W Fwd_GETX 0 <--
M_W Fwd_GETS 0 <--
M_W Fwd_DMA 0 <--
M_W Inv 0 <--
M_W Use_Timeout 0 <--
MM Load 0 <--
MM Ifetch 0 <--
MM Store 0 <--
MM L1_Replacement 0 <--
MM Fwd_GETX 0 <--
MM Fwd_GETS 0 <--
MM Fwd_DMA 0 <--
MM_W Load 0 <--
MM_W Ifetch 0 <--
MM_W Store 0 <--
MM_W L1_Replacement 0 <--
MM_W Own_GETX 0 <--
MM_W Fwd_GETX 0 <--
MM_W Fwd_GETS 0 <--
MM_W Fwd_DMA 0 <--
MM_W Inv 0 <--
MM_W Use_Timeout 0 <--
IM Load 0 <--
IM Ifetch 0 <--
IM Store 0 <--
IM L1_Replacement 0 <--
IM Inv 0 <--
IM Ack 0 <--
IM Data 0 <--
IM Exclusive_Data 0 <--
SM Load 0 <--
SM Ifetch 0 <--
SM Store 0 <--
SM L1_Replacement 0 <--
SM Fwd_GETS 0 <--
SM Fwd_DMA 0 <--
SM Inv 0 <--
SM Ack 0 <--
SM Data 0 <--
SM Exclusive_Data 0 <--
OM Load 0 <--
OM Ifetch 0 <--
OM Store 0 <--
OM L1_Replacement 0 <--
OM Own_GETX 0 <--
OM Fwd_GETX 0 <--
OM Fwd_GETS 0 <--
OM Fwd_DMA 0 <--
OM Ack 0 <--
OM All_acks 0 <--
IS Load 0 <--
IS Ifetch 0 <--
IS Store 0 <--
IS L1_Replacement 0 <--
IS Inv 0 <--
IS Data 0 <--
IS Exclusive_Data 0 <--
SI Load 0 <--
SI Ifetch 0 <--
SI Store 0 <--
SI L1_Replacement 0 <--
SI Fwd_GETS 0 <--
SI Fwd_DMA 0 <--
SI Inv 0 <--
SI Writeback_Ack 0 <--
SI Writeback_Ack_Data 0 <--
SI Writeback_Nack 0 <--
OI Load 0 <--
OI Ifetch 0 <--
OI Store 0 <--
OI L1_Replacement 0 <--
OI Fwd_GETX 0 <--
OI Fwd_GETS 0 <--
OI Fwd_DMA 0 <--
OI Writeback_Ack 0 <--
OI Writeback_Ack_Data 0 <--
OI Writeback_Nack 0 <--
MI Load 0 <--
MI Ifetch 0 <--
MI Store 0 <--
MI L1_Replacement 0 <--
MI Fwd_GETX 0 <--
MI Fwd_GETS 0 <--
MI Fwd_DMA 0 <--
MI Writeback_Ack 0 <--
MI Writeback_Ack_Data 0 <--
MI Writeback_Nack 0 <--
II Load 0 <--
II Ifetch 0 <--
II Store 0 <--
II L1_Replacement 0 <--
II Inv 0 <--
II Writeback_Ack 0 <--
II Writeback_Ack_Data 0 <--
II Writeback_Nack 0 <--
--- L1Cache 6 ---
- Event Counts -
Load 0
Ifetch 0
Store 0
L1_Replacement 0
Own_GETX 0
Fwd_GETX 0
Fwd_GETS 0
Fwd_DMA 0
Inv 0
Ack 0
Data 0
Exclusive_Data 0
Writeback_Ack 0
Writeback_Ack_Data 0
Writeback_Nack 0
All_acks 0
Use_Timeout 0
- Transitions -
I Load 0 <--
I Ifetch 0 <--
I Store 0 <--
I L1_Replacement 0 <--
I Inv 0 <--
S Load 0 <--
S Ifetch 0 <--
S Store 0 <--
S L1_Replacement 0 <--
S Fwd_GETS 0 <--
S Fwd_DMA 0 <--
S Inv 0 <--
O Load 0 <--
O Ifetch 0 <--
O Store 0 <--
O L1_Replacement 0 <--
O Fwd_GETX 0 <--
O Fwd_GETS 0 <--
O Fwd_DMA 0 <--
M Load 0 <--
M Ifetch 0 <--
M Store 0 <--
M L1_Replacement 0 <--
M Fwd_GETX 0 <--
M Fwd_GETS 0 <--
M Fwd_DMA 0 <--
M_W Load 0 <--
M_W Ifetch 0 <--
M_W Store 0 <--
M_W L1_Replacement 0 <--
M_W Own_GETX 0 <--
M_W Fwd_GETX 0 <--
M_W Fwd_GETS 0 <--
M_W Fwd_DMA 0 <--
M_W Inv 0 <--
M_W Use_Timeout 0 <--
MM Load 0 <--
MM Ifetch 0 <--
MM Store 0 <--
MM L1_Replacement 0 <--
MM Fwd_GETX 0 <--
MM Fwd_GETS 0 <--
MM Fwd_DMA 0 <--
MM_W Load 0 <--
MM_W Ifetch 0 <--
MM_W Store 0 <--
MM_W L1_Replacement 0 <--
MM_W Own_GETX 0 <--
MM_W Fwd_GETX 0 <--
MM_W Fwd_GETS 0 <--
MM_W Fwd_DMA 0 <--
MM_W Inv 0 <--
MM_W Use_Timeout 0 <--
IM Load 0 <--
IM Ifetch 0 <--
IM Store 0 <--
IM L1_Replacement 0 <--
IM Inv 0 <--
IM Ack 0 <--
IM Data 0 <--
IM Exclusive_Data 0 <--
SM Load 0 <--
SM Ifetch 0 <--
SM Store 0 <--
SM L1_Replacement 0 <--
SM Fwd_GETS 0 <--
SM Fwd_DMA 0 <--
SM Inv 0 <--
SM Ack 0 <--
SM Data 0 <--
SM Exclusive_Data 0 <--
OM Load 0 <--
OM Ifetch 0 <--
OM Store 0 <--
OM L1_Replacement 0 <--
OM Own_GETX 0 <--
OM Fwd_GETX 0 <--
OM Fwd_GETS 0 <--
OM Fwd_DMA 0 <--
OM Ack 0 <--
OM All_acks 0 <--
IS Load 0 <--
IS Ifetch 0 <--
IS Store 0 <--
IS L1_Replacement 0 <--
IS Inv 0 <--
IS Data 0 <--
IS Exclusive_Data 0 <--
SI Load 0 <--
SI Ifetch 0 <--
SI Store 0 <--
SI L1_Replacement 0 <--
SI Fwd_GETS 0 <--
SI Fwd_DMA 0 <--
SI Inv 0 <--
SI Writeback_Ack 0 <--
SI Writeback_Ack_Data 0 <--
SI Writeback_Nack 0 <--
OI Load 0 <--
OI Ifetch 0 <--
OI Store 0 <--
OI L1_Replacement 0 <--
OI Fwd_GETX 0 <--
OI Fwd_GETS 0 <--
OI Fwd_DMA 0 <--
OI Writeback_Ack 0 <--
OI Writeback_Ack_Data 0 <--
OI Writeback_Nack 0 <--
MI Load 0 <--
MI Ifetch 0 <--
MI Store 0 <--
MI L1_Replacement 0 <--
MI Fwd_GETX 0 <--
MI Fwd_GETS 0 <--
MI Fwd_DMA 0 <--
MI Writeback_Ack 0 <--
MI Writeback_Ack_Data 0 <--
MI Writeback_Nack 0 <--
II Load 0 <--
II Ifetch 0 <--
II Store 0 <--
II L1_Replacement 0 <--
II Inv 0 <--
II Writeback_Ack 0 <--
II Writeback_Ack_Data 0 <--
II Writeback_Nack 0 <--
--- L1Cache 7 ---
- Event Counts -
Load 0
Ifetch 0
Store 0
L1_Replacement 0
Own_GETX 0
Fwd_GETX 0
Fwd_GETS 0
Fwd_DMA 0
Inv 0
Ack 0
Data 0
Exclusive_Data 0
Writeback_Ack 0
Writeback_Ack_Data 0
Writeback_Nack 0
All_acks 0
Use_Timeout 0
- Transitions -
I Load 0 <--
I Ifetch 0 <--
I Store 0 <--
I L1_Replacement 0 <--
I Inv 0 <--
S Load 0 <--
S Ifetch 0 <--
S Store 0 <--
S L1_Replacement 0 <--
S Fwd_GETS 0 <--
S Fwd_DMA 0 <--
S Inv 0 <--
O Load 0 <--
O Ifetch 0 <--
O Store 0 <--
O L1_Replacement 0 <--
O Fwd_GETX 0 <--
O Fwd_GETS 0 <--
O Fwd_DMA 0 <--
M Load 0 <--
M Ifetch 0 <--
M Store 0 <--
M L1_Replacement 0 <--
M Fwd_GETX 0 <--
M Fwd_GETS 0 <--
M Fwd_DMA 0 <--
M_W Load 0 <--
M_W Ifetch 0 <--
M_W Store 0 <--
M_W L1_Replacement 0 <--
M_W Own_GETX 0 <--
M_W Fwd_GETX 0 <--
M_W Fwd_GETS 0 <--
M_W Fwd_DMA 0 <--
M_W Inv 0 <--
M_W Use_Timeout 0 <--
MM Load 0 <--
MM Ifetch 0 <--
MM Store 0 <--
MM L1_Replacement 0 <--
MM Fwd_GETX 0 <--
MM Fwd_GETS 0 <--
MM Fwd_DMA 0 <--
MM_W Load 0 <--
MM_W Ifetch 0 <--
MM_W Store 0 <--
MM_W L1_Replacement 0 <--
MM_W Own_GETX 0 <--
MM_W Fwd_GETX 0 <--
MM_W Fwd_GETS 0 <--
MM_W Fwd_DMA 0 <--
MM_W Inv 0 <--
MM_W Use_Timeout 0 <--
IM Load 0 <--
IM Ifetch 0 <--
IM Store 0 <--
IM L1_Replacement 0 <--
IM Inv 0 <--
IM Ack 0 <--
IM Data 0 <--
IM Exclusive_Data 0 <--
SM Load 0 <--
SM Ifetch 0 <--
SM Store 0 <--
SM L1_Replacement 0 <--
SM Fwd_GETS 0 <--
SM Fwd_DMA 0 <--
SM Inv 0 <--
SM Ack 0 <--
SM Data 0 <--
SM Exclusive_Data 0 <--
OM Load 0 <--
OM Ifetch 0 <--
OM Store 0 <--
OM L1_Replacement 0 <--
OM Own_GETX 0 <--
OM Fwd_GETX 0 <--
OM Fwd_GETS 0 <--
OM Fwd_DMA 0 <--
OM Ack 0 <--
OM All_acks 0 <--
IS Load 0 <--
IS Ifetch 0 <--
IS Store 0 <--
IS L1_Replacement 0 <--
IS Inv 0 <--
IS Data 0 <--
IS Exclusive_Data 0 <--
SI Load 0 <--
SI Ifetch 0 <--
SI Store 0 <--
SI L1_Replacement 0 <--
SI Fwd_GETS 0 <--
SI Fwd_DMA 0 <--
SI Inv 0 <--
SI Writeback_Ack 0 <--
SI Writeback_Ack_Data 0 <--
SI Writeback_Nack 0 <--
OI Load 0 <--
OI Ifetch 0 <--
OI Store 0 <--
OI L1_Replacement 0 <--
OI Fwd_GETX 0 <--
OI Fwd_GETS 0 <--
OI Fwd_DMA 0 <--
OI Writeback_Ack 0 <--
OI Writeback_Ack_Data 0 <--
OI Writeback_Nack 0 <--
MI Load 0 <--
MI Ifetch 0 <--
MI Store 0 <--
MI L1_Replacement 0 <--
MI Fwd_GETX 0 <--
MI Fwd_GETS 0 <--
MI Fwd_DMA 0 <--
MI Writeback_Ack 0 <--
MI Writeback_Ack_Data 0 <--
MI Writeback_Nack 0 <--
II Load 0 <--
II Ifetch 0 <--
II Store 0 <--
II L1_Replacement 0 <--
II Inv 0 <--
II Writeback_Ack 0 <--
II Writeback_Ack_Data 0 <--
II Writeback_Nack 0 <--
--- L2Cache 0 ---
- Event Counts -
L1_GETS 233916
L1_GETX 125680
L1_PUTO 0
L1_PUTX 359416
L1_PUTS_only 0
L1_PUTS 0
Fwd_GETX 0
Fwd_GETS 0
Fwd_DMA 0
Own_GETX 0
Inv 0
IntAck 0
ExtAck 0
All_Acks 516
Data 516
Data_Exclusive 992
L1_WBCLEANDATA 2649
L1_WBDIRTYDATA 356765
Writeback_Ack 0
Writeback_Nack 0
Unblock 0
Exclusive_Unblock 359478
L2_Replacement 0
- Transitions -
NP L1_GETS 992
NP L1_GETX 516
NP L1_PUTO 0 <--
NP L1_PUTX 0 <--
NP L1_PUTS 0 <--
NP Inv 0 <--
I L1_GETS 0 <--
I L1_GETX 0 <--
I L1_PUTO 0 <--
I L1_PUTX 0 <--
I L1_PUTS 0 <--
I Inv 0 <--
I L2_Replacement 0 <--
ILS L1_GETS 0 <--
ILS L1_GETX 0 <--
ILS L1_PUTO 0 <--
ILS L1_PUTX 0 <--
ILS L1_PUTS_only 0 <--
ILS L1_PUTS 0 <--
ILS Inv 0 <--
ILS L2_Replacement 0 <--
ILX L1_GETS 0 <--
ILX L1_GETX 0 <--
ILX L1_PUTO 0 <--
ILX L1_PUTX 359416
ILX L1_PUTS_only 0 <--
ILX L1_PUTS 0 <--
ILX Fwd_GETX 0 <--
ILX Fwd_GETS 0 <--
ILX Fwd_DMA 0 <--
ILX Inv 0 <--
ILX Data 0 <--
ILX L2_Replacement 0 <--
ILO L1_GETS 0 <--
ILO L1_GETX 0 <--
ILO L1_PUTO 0 <--
ILO L1_PUTX 0 <--
ILO L1_PUTS 0 <--
ILO Fwd_GETX 0 <--
ILO Fwd_GETS 0 <--
ILO Fwd_DMA 0 <--
ILO Inv 0 <--
ILO Data 0 <--
ILO L2_Replacement 0 <--
ILOX L1_GETS 0 <--
ILOX L1_GETX 0 <--
ILOX L1_PUTO 0 <--
ILOX L1_PUTX 0 <--
ILOX L1_PUTS 0 <--
ILOX Fwd_GETX 0 <--
ILOX Fwd_GETS 0 <--
ILOX Fwd_DMA 0 <--
ILOX Data 0 <--
ILOS L1_GETS 0 <--
ILOS L1_GETX 0 <--
ILOS L1_PUTO 0 <--
ILOS L1_PUTX 0 <--
ILOS L1_PUTS_only 0 <--
ILOS L1_PUTS 0 <--
ILOS Fwd_GETX 0 <--
ILOS Fwd_GETS 0 <--
ILOS Fwd_DMA 0 <--
ILOS Data 0 <--
ILOS L2_Replacement 0 <--
ILOSX L1_GETS 0 <--
ILOSX L1_GETX 0 <--
ILOSX L1_PUTO 0 <--
ILOSX L1_PUTX 0 <--
ILOSX L1_PUTS_only 0 <--
ILOSX L1_PUTS 0 <--
ILOSX Fwd_GETX 0 <--
ILOSX Fwd_GETS 0 <--
ILOSX Fwd_DMA 0 <--
ILOSX Data 0 <--
S L1_GETS 0 <--
S L1_GETX 0 <--
S L1_PUTX 0 <--
S L1_PUTS 0 <--
S Inv 0 <--
S L2_Replacement 0 <--
O L1_GETS 0 <--
O L1_GETX 0 <--
O L1_PUTX 0 <--
O Fwd_GETX 0 <--
O Fwd_GETS 0 <--
O Fwd_DMA 0 <--
O L2_Replacement 0 <--
OLS L1_GETS 0 <--
OLS L1_GETX 0 <--
OLS L1_PUTX 0 <--
OLS L1_PUTS_only 0 <--
OLS L1_PUTS 0 <--
OLS Fwd_GETX 0 <--
OLS Fwd_GETS 0 <--
OLS Fwd_DMA 0 <--
OLS L2_Replacement 0 <--
OLSX L1_GETS 0 <--
OLSX L1_GETX 0 <--
OLSX L1_PUTO 0 <--
OLSX L1_PUTX 0 <--
OLSX L1_PUTS_only 0 <--
OLSX L1_PUTS 0 <--
OLSX Fwd_GETX 0 <--
OLSX Fwd_GETS 0 <--
OLSX Fwd_DMA 0 <--
OLSX L2_Replacement 0 <--
SLS L1_GETS 0 <--
SLS L1_GETX 0 <--
SLS L1_PUTX 0 <--
SLS L1_PUTS_only 0 <--
SLS L1_PUTS 0 <--
SLS Inv 0 <--
SLS L2_Replacement 0 <--
M L1_GETS 232846
M L1_GETX 125126
M L1_PUTO 0 <--
M L1_PUTX 0 <--
M L1_PUTS 0 <--
M Fwd_GETX 0 <--
M Fwd_GETS 0 <--
M Fwd_DMA 0 <--
M L2_Replacement 0 <--
IFGX L1_GETS 0 <--
IFGX L1_GETX 0 <--
IFGX L1_PUTO 0 <--
IFGX L1_PUTX 0 <--
IFGX L1_PUTS_only 0 <--
IFGX L1_PUTS 0 <--
IFGX Fwd_GETX 0 <--
IFGX Fwd_GETS 0 <--
IFGX Fwd_DMA 0 <--
IFGX Inv 0 <--
IFGX Data 0 <--
IFGX Data_Exclusive 0 <--
IFGX L2_Replacement 0 <--
IFGS L1_GETS 0 <--
IFGS L1_GETX 0 <--
IFGS L1_PUTO 0 <--
IFGS L1_PUTX 0 <--
IFGS L1_PUTS_only 0 <--
IFGS L1_PUTS 0 <--
IFGS Fwd_GETX 0 <--
IFGS Fwd_GETS 0 <--
IFGS Fwd_DMA 0 <--
IFGS Inv 0 <--
IFGS Data 0 <--
IFGS Data_Exclusive 0 <--
IFGS L2_Replacement 0 <--
ISFGS L1_GETS 0 <--
ISFGS L1_GETX 0 <--
ISFGS L1_PUTO 0 <--
ISFGS L1_PUTX 0 <--
ISFGS L1_PUTS_only 0 <--
ISFGS L1_PUTS 0 <--
ISFGS Fwd_GETX 0 <--
ISFGS Fwd_GETS 0 <--
ISFGS Fwd_DMA 0 <--
ISFGS Inv 0 <--
ISFGS Data 0 <--
ISFGS L2_Replacement 0 <--
IFGXX L1_GETS 0 <--
IFGXX L1_GETX 0 <--
IFGXX L1_PUTO 0 <--
IFGXX L1_PUTX 0 <--
IFGXX L1_PUTS_only 0 <--
IFGXX L1_PUTS 0 <--
IFGXX Fwd_GETX 0 <--
IFGXX Fwd_GETS 0 <--
IFGXX Fwd_DMA 0 <--
IFGXX Inv 0 <--
IFGXX IntAck 0 <--
IFGXX All_Acks 0 <--
IFGXX Data_Exclusive 0 <--
IFGXX L2_Replacement 0 <--
OFGX L1_GETS 0 <--
OFGX L1_GETX 0 <--
OFGX L1_PUTO 0 <--
OFGX L1_PUTX 0 <--
OFGX L1_PUTS_only 0 <--
OFGX L1_PUTS 0 <--
OFGX Fwd_GETX 0 <--
OFGX Fwd_GETS 0 <--
OFGX Fwd_DMA 0 <--
OFGX Inv 0 <--
OFGX L2_Replacement 0 <--
OLSF L1_GETS 0 <--
OLSF L1_GETX 0 <--
OLSF L1_PUTO 0 <--
OLSF L1_PUTX 0 <--
OLSF L1_PUTS_only 0 <--
OLSF L1_PUTS 0 <--
OLSF Fwd_GETX 0 <--
OLSF Fwd_GETS 0 <--
OLSF Fwd_DMA 0 <--
OLSF Inv 0 <--
OLSF IntAck 0 <--
OLSF All_Acks 0 <--
OLSF L2_Replacement 0 <--
ILOW L1_GETS 0 <--
ILOW L1_GETX 0 <--
ILOW L1_PUTO 0 <--
ILOW L1_PUTX 0 <--
ILOW L1_PUTS_only 0 <--
ILOW L1_PUTS 0 <--
ILOW Fwd_GETX 0 <--
ILOW Fwd_GETS 0 <--
ILOW Fwd_DMA 0 <--
ILOW Inv 0 <--
ILOW L1_WBCLEANDATA 0 <--
ILOW L1_WBDIRTYDATA 0 <--
ILOW Unblock 0 <--
ILOW L2_Replacement 0 <--
ILOXW L1_GETS 0 <--
ILOXW L1_GETX 0 <--
ILOXW L1_PUTO 0 <--
ILOXW L1_PUTX 0 <--
ILOXW L1_PUTS_only 0 <--
ILOXW L1_PUTS 0 <--
ILOXW Fwd_GETX 0 <--
ILOXW Fwd_GETS 0 <--
ILOXW Fwd_DMA 0 <--
ILOXW Inv 0 <--
ILOXW L1_WBCLEANDATA 0 <--
ILOXW L1_WBDIRTYDATA 0 <--
ILOXW Unblock 0 <--
ILOXW L2_Replacement 0 <--
ILOSW L1_GETS 0 <--
ILOSW L1_GETX 0 <--
ILOSW L1_PUTO 0 <--
ILOSW L1_PUTX 0 <--
ILOSW L1_PUTS_only 0 <--
ILOSW L1_PUTS 0 <--
ILOSW Fwd_GETX 0 <--
ILOSW Fwd_GETS 0 <--
ILOSW Fwd_DMA 0 <--
ILOSW Inv 0 <--
ILOSW L1_WBCLEANDATA 0 <--
ILOSW L1_WBDIRTYDATA 0 <--
ILOSW Unblock 0 <--
ILOSW L2_Replacement 0 <--
ILOSXW L1_GETS 0 <--
ILOSXW L1_GETX 0 <--
ILOSXW L1_PUTO 0 <--
ILOSXW L1_PUTX 0 <--
ILOSXW L1_PUTS_only 0 <--
ILOSXW L1_PUTS 0 <--
ILOSXW Fwd_GETX 0 <--
ILOSXW Fwd_GETS 0 <--
ILOSXW Fwd_DMA 0 <--
ILOSXW Inv 0 <--
ILOSXW L1_WBCLEANDATA 0 <--
ILOSXW L1_WBDIRTYDATA 0 <--
ILOSXW Unblock 0 <--
ILOSXW L2_Replacement 0 <--
SLSW L1_GETS 0 <--
SLSW L1_GETX 0 <--
SLSW L1_PUTO 0 <--
SLSW L1_PUTX 0 <--
SLSW L1_PUTS_only 0 <--
SLSW L1_PUTS 0 <--
SLSW Fwd_GETX 0 <--
SLSW Fwd_GETS 0 <--
SLSW Fwd_DMA 0 <--
SLSW Inv 0 <--
SLSW Unblock 0 <--
SLSW L2_Replacement 0 <--
OLSW L1_GETS 0 <--
OLSW L1_GETX 0 <--
OLSW L1_PUTO 0 <--
OLSW L1_PUTX 0 <--
OLSW L1_PUTS_only 0 <--
OLSW L1_PUTS 0 <--
OLSW Fwd_GETX 0 <--
OLSW Fwd_GETS 0 <--
OLSW Fwd_DMA 0 <--
OLSW Inv 0 <--
OLSW Unblock 0 <--
OLSW L2_Replacement 0 <--
ILSW L1_GETS 0 <--
ILSW L1_GETX 0 <--
ILSW L1_PUTO 0 <--
ILSW L1_PUTX 0 <--
ILSW L1_PUTS_only 0 <--
ILSW L1_PUTS 0 <--
ILSW Fwd_GETX 0 <--
ILSW Fwd_GETS 0 <--
ILSW Fwd_DMA 0 <--
ILSW Inv 0 <--
ILSW L1_WBCLEANDATA 0 <--
ILSW Unblock 0 <--
ILSW L2_Replacement 0 <--
IW L1_GETS 0 <--
IW L1_GETX 0 <--
IW L1_PUTO 0 <--
IW L1_PUTX 0 <--
IW L1_PUTS_only 0 <--
IW L1_PUTS 0 <--
IW Fwd_GETX 0 <--
IW Fwd_GETS 0 <--
IW Fwd_DMA 0 <--
IW Inv 0 <--
IW L1_WBCLEANDATA 0 <--
IW L2_Replacement 0 <--
OW L1_GETS 0 <--
OW L1_GETX 0 <--
OW L1_PUTO 0 <--
OW L1_PUTX 0 <--
OW L1_PUTS_only 0 <--
OW L1_PUTS 0 <--
OW Fwd_GETX 0 <--
OW Fwd_GETS 0 <--
OW Fwd_DMA 0 <--
OW Inv 0 <--
OW Unblock 0 <--
OW L2_Replacement 0 <--
SW L1_GETS 0 <--
SW L1_GETX 0 <--
SW L1_PUTO 0 <--
SW L1_PUTX 0 <--
SW L1_PUTS_only 0 <--
SW L1_PUTS 0 <--
SW Fwd_GETX 0 <--
SW Fwd_GETS 0 <--
SW Fwd_DMA 0 <--
SW Inv 0 <--
SW Unblock 0 <--
SW L2_Replacement 0 <--
OXW L1_GETS 0 <--
OXW L1_GETX 0 <--
OXW L1_PUTO 0 <--
OXW L1_PUTX 0 <--
OXW L1_PUTS_only 0 <--
OXW L1_PUTS 0 <--
OXW Fwd_GETX 0 <--
OXW Fwd_GETS 0 <--
OXW Fwd_DMA 0 <--
OXW Inv 0 <--
OXW Unblock 0 <--
OXW L2_Replacement 0 <--
OLSXW L1_GETS 0 <--
OLSXW L1_GETX 0 <--
OLSXW L1_PUTO 0 <--
OLSXW L1_PUTX 0 <--
OLSXW L1_PUTS_only 0 <--
OLSXW L1_PUTS 0 <--
OLSXW Fwd_GETX 0 <--
OLSXW Fwd_GETS 0 <--
OLSXW Fwd_DMA 0 <--
OLSXW Inv 0 <--
OLSXW Unblock 0 <--
OLSXW L2_Replacement 0 <--
ILXW L1_GETS 78
ILXW L1_GETX 38
ILXW L1_PUTO 0 <--
ILXW L1_PUTX 0 <--
ILXW L1_PUTS_only 0 <--
ILXW L1_PUTS 0 <--
ILXW Fwd_GETX 0 <--
ILXW Fwd_GETS 0 <--
ILXW Fwd_DMA 0 <--
ILXW Inv 0 <--
ILXW Data 0 <--
ILXW L1_WBCLEANDATA 2649
ILXW L1_WBDIRTYDATA 356765
ILXW Unblock 0 <--
ILXW L2_Replacement 0 <--
IFLS L1_GETS 0 <--
IFLS L1_GETX 0 <--
IFLS L1_PUTO 0 <--
IFLS L1_PUTX 0 <--
IFLS L1_PUTS_only 0 <--
IFLS L1_PUTS 0 <--
IFLS Fwd_GETX 0 <--
IFLS Fwd_GETS 0 <--
IFLS Fwd_DMA 0 <--
IFLS Inv 0 <--
IFLS Unblock 0 <--
IFLS L2_Replacement 0 <--
IFLO L1_GETS 0 <--
IFLO L1_GETX 0 <--
IFLO L1_PUTO 0 <--
IFLO L1_PUTX 0 <--
IFLO L1_PUTS_only 0 <--
IFLO L1_PUTS 0 <--
IFLO Fwd_GETX 0 <--
IFLO Fwd_GETS 0 <--
IFLO Fwd_DMA 0 <--
IFLO Inv 0 <--
IFLO Unblock 0 <--
IFLO L2_Replacement 0 <--
IFLOX L1_GETS 0 <--
IFLOX L1_GETX 0 <--
IFLOX L1_PUTO 0 <--
IFLOX L1_PUTX 0 <--
IFLOX L1_PUTS_only 0 <--
IFLOX L1_PUTS 0 <--
IFLOX Fwd_GETX 0 <--
IFLOX Fwd_GETS 0 <--
IFLOX Fwd_DMA 0 <--
IFLOX Inv 0 <--
IFLOX Unblock 0 <--
IFLOX Exclusive_Unblock 0 <--
IFLOX L2_Replacement 0 <--
IFLOXX L1_GETS 0 <--
IFLOXX L1_GETX 0 <--
IFLOXX L1_PUTO 0 <--
IFLOXX L1_PUTX 0 <--
IFLOXX L1_PUTS_only 0 <--
IFLOXX L1_PUTS 0 <--
IFLOXX Fwd_GETX 0 <--
IFLOXX Fwd_GETS 0 <--
IFLOXX Fwd_DMA 0 <--
IFLOXX Inv 0 <--
IFLOXX Unblock 0 <--
IFLOXX Exclusive_Unblock 0 <--
IFLOXX L2_Replacement 0 <--
IFLOSX L1_GETS 0 <--
IFLOSX L1_GETX 0 <--
IFLOSX L1_PUTO 0 <--
IFLOSX L1_PUTX 0 <--
IFLOSX L1_PUTS_only 0 <--
IFLOSX L1_PUTS 0 <--
IFLOSX Fwd_GETX 0 <--
IFLOSX Fwd_GETS 0 <--
IFLOSX Fwd_DMA 0 <--
IFLOSX Inv 0 <--
IFLOSX Unblock 0 <--
IFLOSX Exclusive_Unblock 0 <--
IFLOSX L2_Replacement 0 <--
IFLXO L1_GETS 0 <--
IFLXO L1_GETX 0 <--
IFLXO L1_PUTO 0 <--
IFLXO L1_PUTX 0 <--
IFLXO L1_PUTS_only 0 <--
IFLXO L1_PUTS 0 <--
IFLXO Fwd_GETX 0 <--
IFLXO Fwd_GETS 0 <--
IFLXO Fwd_DMA 0 <--
IFLXO Inv 0 <--
IFLXO Exclusive_Unblock 0 <--
IFLXO L2_Replacement 0 <--
IGS L1_GETS 0 <--
IGS L1_GETX 0 <--
IGS L1_PUTO 0 <--
IGS L1_PUTX 0 <--
IGS L1_PUTS_only 0 <--
IGS L1_PUTS 0 <--
IGS Fwd_GETX 0 <--
IGS Fwd_GETS 0 <--
IGS Fwd_DMA 0 <--
IGS Own_GETX 0 <--
IGS Inv 0 <--
IGS Data 0 <--
IGS Data_Exclusive 992
IGS Unblock 0 <--
IGS Exclusive_Unblock 992
IGS L2_Replacement 0 <--
IGM L1_GETS 0 <--
IGM L1_GETX 0 <--
IGM L1_PUTO 0 <--
IGM L1_PUTX 0 <--
IGM L1_PUTS_only 0 <--
IGM L1_PUTS 0 <--
IGM Fwd_GETX 0 <--
IGM Fwd_GETS 0 <--
IGM Fwd_DMA 0 <--
IGM Own_GETX 0 <--
IGM Inv 0 <--
IGM ExtAck 0 <--
IGM Data 516
IGM Data_Exclusive 0 <--
IGM L2_Replacement 0 <--
IGMLS L1_GETS 0 <--
IGMLS L1_GETX 0 <--
IGMLS L1_PUTO 0 <--
IGMLS L1_PUTX 0 <--
IGMLS L1_PUTS_only 0 <--
IGMLS L1_PUTS 0 <--
IGMLS Inv 0 <--
IGMLS IntAck 0 <--
IGMLS ExtAck 0 <--
IGMLS All_Acks 0 <--
IGMLS Data 0 <--
IGMLS Data_Exclusive 0 <--
IGMLS L2_Replacement 0 <--
IGMO L1_GETS 0 <--
IGMO L1_GETX 0 <--
IGMO L1_PUTO 0 <--
IGMO L1_PUTX 0 <--
IGMO L1_PUTS_only 0 <--
IGMO L1_PUTS 0 <--
IGMO Fwd_GETX 0 <--
IGMO Fwd_GETS 0 <--
IGMO Fwd_DMA 0 <--
IGMO Own_GETX 0 <--
IGMO ExtAck 0 <--
IGMO All_Acks 516
IGMO Exclusive_Unblock 516
IGMO L2_Replacement 0 <--
IGMIO L1_GETS 0 <--
IGMIO L1_GETX 0 <--
IGMIO L1_PUTO 0 <--
IGMIO L1_PUTX 0 <--
IGMIO L1_PUTS_only 0 <--
IGMIO L1_PUTS 0 <--
IGMIO Fwd_GETX 0 <--
IGMIO Fwd_GETS 0 <--
IGMIO Fwd_DMA 0 <--
IGMIO Own_GETX 0 <--
IGMIO ExtAck 0 <--
IGMIO All_Acks 0 <--
OGMIO L1_GETS 0 <--
OGMIO L1_GETX 0 <--
OGMIO L1_PUTO 0 <--
OGMIO L1_PUTX 0 <--
OGMIO L1_PUTS_only 0 <--
OGMIO L1_PUTS 0 <--
OGMIO Fwd_GETX 0 <--
OGMIO Fwd_GETS 0 <--
OGMIO Fwd_DMA 0 <--
OGMIO Own_GETX 0 <--
OGMIO ExtAck 0 <--
OGMIO All_Acks 0 <--
IGMIOF L1_GETS 0 <--
IGMIOF L1_GETX 0 <--
IGMIOF L1_PUTO 0 <--
IGMIOF L1_PUTX 0 <--
IGMIOF L1_PUTS_only 0 <--
IGMIOF L1_PUTS 0 <--
IGMIOF IntAck 0 <--
IGMIOF All_Acks 0 <--
IGMIOF Data_Exclusive 0 <--
IGMIOFS L1_GETS 0 <--
IGMIOFS L1_GETX 0 <--
IGMIOFS L1_PUTO 0 <--
IGMIOFS L1_PUTX 0 <--
IGMIOFS L1_PUTS_only 0 <--
IGMIOFS L1_PUTS 0 <--
IGMIOFS Fwd_GETX 0 <--
IGMIOFS Fwd_GETS 0 <--
IGMIOFS Fwd_DMA 0 <--
IGMIOFS Inv 0 <--
IGMIOFS Data 0 <--
IGMIOFS L2_Replacement 0 <--
OGMIOF L1_GETS 0 <--
OGMIOF L1_GETX 0 <--
OGMIOF L1_PUTO 0 <--
OGMIOF L1_PUTX 0 <--
OGMIOF L1_PUTS_only 0 <--
OGMIOF L1_PUTS 0 <--
OGMIOF IntAck 0 <--
OGMIOF All_Acks 0 <--
II L1_GETS 0 <--
II L1_GETX 0 <--
II L1_PUTO 0 <--
II L1_PUTX 0 <--
II L1_PUTS_only 0 <--
II L1_PUTS 0 <--
II IntAck 0 <--
II All_Acks 0 <--
MM L1_GETS 0 <--
MM L1_GETX 0 <--
MM L1_PUTO 0 <--
MM L1_PUTX 0 <--
MM L1_PUTS_only 0 <--
MM L1_PUTS 0 <--
MM Fwd_GETX 0 <--
MM Fwd_GETS 0 <--
MM Fwd_DMA 0 <--
MM Inv 0 <--
MM Exclusive_Unblock 125126
MM L2_Replacement 0 <--
SS L1_GETS 0 <--
SS L1_GETX 0 <--
SS L1_PUTO 0 <--
SS L1_PUTX 0 <--
SS L1_PUTS_only 0 <--
SS L1_PUTS 0 <--
SS Fwd_GETX 0 <--
SS Fwd_GETS 0 <--
SS Fwd_DMA 0 <--
SS Inv 0 <--
SS Unblock 0 <--
SS L2_Replacement 0 <--
OO L1_GETS 0 <--
OO L1_GETX 0 <--
OO L1_PUTO 0 <--
OO L1_PUTX 0 <--
OO L1_PUTS_only 0 <--
OO L1_PUTS 0 <--
OO Fwd_GETX 0 <--
OO Fwd_GETS 0 <--
OO Fwd_DMA 0 <--
OO Inv 0 <--
OO Unblock 0 <--
OO Exclusive_Unblock 232844
OO L2_Replacement 0 <--
OLSS L1_GETS 0 <--
OLSS L1_GETX 0 <--
OLSS L1_PUTO 0 <--
OLSS L1_PUTX 0 <--
OLSS L1_PUTS_only 0 <--
OLSS L1_PUTS 0 <--
OLSS Fwd_GETX 0 <--
OLSS Fwd_GETS 0 <--
OLSS Fwd_DMA 0 <--
OLSS Inv 0 <--
OLSS Unblock 0 <--
OLSS L2_Replacement 0 <--
OLSXS L1_GETS 0 <--
OLSXS L1_GETX 0 <--
OLSXS L1_PUTO 0 <--
OLSXS L1_PUTX 0 <--
OLSXS L1_PUTS_only 0 <--
OLSXS L1_PUTS 0 <--
OLSXS Fwd_GETX 0 <--
OLSXS Fwd_GETS 0 <--
OLSXS Fwd_DMA 0 <--
OLSXS Inv 0 <--
OLSXS Unblock 0 <--
OLSXS L2_Replacement 0 <--
SLSS L1_GETS 0 <--
SLSS L1_GETX 0 <--
SLSS L1_PUTO 0 <--
SLSS L1_PUTX 0 <--
SLSS L1_PUTS_only 0 <--
SLSS L1_PUTS 0 <--
SLSS Fwd_GETX 0 <--
SLSS Fwd_GETS 0 <--
SLSS Fwd_DMA 0 <--
SLSS Inv 0 <--
SLSS Unblock 0 <--
SLSS L2_Replacement 0 <--
OI L1_GETS 0 <--
OI L1_GETX 0 <--
OI L1_PUTO 0 <--
OI L1_PUTX 0 <--
OI L1_PUTS_only 0 <--
OI L1_PUTS 0 <--
OI Fwd_GETX 0 <--
OI Fwd_GETS 0 <--
OI Fwd_DMA 0 <--
OI Writeback_Ack 0 <--
OI Writeback_Nack 0 <--
OI L2_Replacement 0 <--
MI L1_GETS 0 <--
MI L1_GETX 0 <--
MI L1_PUTO 0 <--
MI L1_PUTX 0 <--
MI L1_PUTS_only 0 <--
MI L1_PUTS 0 <--
MI Fwd_GETX 0 <--
MI Fwd_GETS 0 <--
MI Fwd_DMA 0 <--
MI Writeback_Ack 0 <--
MI L2_Replacement 0 <--
MII L1_GETS 0 <--
MII L1_GETX 0 <--
MII L1_PUTO 0 <--
MII L1_PUTX 0 <--
MII L1_PUTS_only 0 <--
MII L1_PUTS 0 <--
MII Writeback_Ack 0 <--
MII Writeback_Nack 0 <--
MII L2_Replacement 0 <--
OLSI L1_GETS 0 <--
OLSI L1_GETX 0 <--
OLSI L1_PUTO 0 <--
OLSI L1_PUTX 0 <--
OLSI L1_PUTS_only 0 <--
OLSI L1_PUTS 0 <--
OLSI Fwd_GETX 0 <--
OLSI Fwd_GETS 0 <--
OLSI Fwd_DMA 0 <--
OLSI Writeback_Ack 0 <--
OLSI L2_Replacement 0 <--
ILSI L1_GETS 0 <--
ILSI L1_GETX 0 <--
ILSI L1_PUTO 0 <--
ILSI L1_PUTX 0 <--
ILSI L1_PUTS_only 0 <--
ILSI L1_PUTS 0 <--
ILSI IntAck 0 <--
ILSI All_Acks 0 <--
ILSI Writeback_Ack 0 <--
ILSI L2_Replacement 0 <--
--- L2Cache 1 ---
- Event Counts -
L1_GETS 234483
L1_GETX 126367
L1_PUTO 0
L1_PUTX 360682
L1_PUTS_only 0
L1_PUTS 0
Fwd_GETX 0
Fwd_GETS 0
Fwd_DMA 0
Own_GETX 0
Inv 0
IntAck 0
ExtAck 0
All_Acks 506
Data 506
Data_Exclusive 991
L1_WBCLEANDATA 2626
L1_WBDIRTYDATA 358053
Writeback_Ack 0
Writeback_Nack 0
Unblock 0
Exclusive_Unblock 360743
L2_Replacement 0
- Transitions -
NP L1_GETS 991
NP L1_GETX 506
NP L1_PUTO 0 <--
NP L1_PUTX 0 <--
NP L1_PUTS 0 <--
NP Inv 0 <--
I L1_GETS 0 <--
I L1_GETX 0 <--
I L1_PUTO 0 <--
I L1_PUTX 0 <--
I L1_PUTS 0 <--
I Inv 0 <--
I L2_Replacement 0 <--
ILS L1_GETS 0 <--
ILS L1_GETX 0 <--
ILS L1_PUTO 0 <--
ILS L1_PUTX 0 <--
ILS L1_PUTS_only 0 <--
ILS L1_PUTS 0 <--
ILS Inv 0 <--
ILS L2_Replacement 0 <--
ILX L1_GETS 0 <--
ILX L1_GETX 0 <--
ILX L1_PUTO 0 <--
ILX L1_PUTX 360682
ILX L1_PUTS_only 0 <--
ILX L1_PUTS 0 <--
ILX Fwd_GETX 0 <--
ILX Fwd_GETS 0 <--
ILX Fwd_DMA 0 <--
ILX Inv 0 <--
ILX Data 0 <--
ILX L2_Replacement 0 <--
ILO L1_GETS 0 <--
ILO L1_GETX 0 <--
ILO L1_PUTO 0 <--
ILO L1_PUTX 0 <--
ILO L1_PUTS 0 <--
ILO Fwd_GETX 0 <--
ILO Fwd_GETS 0 <--
ILO Fwd_DMA 0 <--
ILO Inv 0 <--
ILO Data 0 <--
ILO L2_Replacement 0 <--
ILOX L1_GETS 0 <--
ILOX L1_GETX 0 <--
ILOX L1_PUTO 0 <--
ILOX L1_PUTX 0 <--
ILOX L1_PUTS 0 <--
ILOX Fwd_GETX 0 <--
ILOX Fwd_GETS 0 <--
ILOX Fwd_DMA 0 <--
ILOX Data 0 <--
ILOS L1_GETS 0 <--
ILOS L1_GETX 0 <--
ILOS L1_PUTO 0 <--
ILOS L1_PUTX 0 <--
ILOS L1_PUTS_only 0 <--
ILOS L1_PUTS 0 <--
ILOS Fwd_GETX 0 <--
ILOS Fwd_GETS 0 <--
ILOS Fwd_DMA 0 <--
ILOS Data 0 <--
ILOS L2_Replacement 0 <--
ILOSX L1_GETS 0 <--
ILOSX L1_GETX 0 <--
ILOSX L1_PUTO 0 <--
ILOSX L1_PUTX 0 <--
ILOSX L1_PUTS_only 0 <--
ILOSX L1_PUTS 0 <--
ILOSX Fwd_GETX 0 <--
ILOSX Fwd_GETS 0 <--
ILOSX Fwd_DMA 0 <--
ILOSX Data 0 <--
S L1_GETS 0 <--
S L1_GETX 0 <--
S L1_PUTX 0 <--
S L1_PUTS 0 <--
S Inv 0 <--
S L2_Replacement 0 <--
O L1_GETS 0 <--
O L1_GETX 0 <--
O L1_PUTX 0 <--
O Fwd_GETX 0 <--
O Fwd_GETS 0 <--
O Fwd_DMA 0 <--
O L2_Replacement 0 <--
OLS L1_GETS 0 <--
OLS L1_GETX 0 <--
OLS L1_PUTX 0 <--
OLS L1_PUTS_only 0 <--
OLS L1_PUTS 0 <--
OLS Fwd_GETX 0 <--
OLS Fwd_GETS 0 <--
OLS Fwd_DMA 0 <--
OLS L2_Replacement 0 <--
OLSX L1_GETS 0 <--
OLSX L1_GETX 0 <--
OLSX L1_PUTO 0 <--
OLSX L1_PUTX 0 <--
OLSX L1_PUTS_only 0 <--
OLSX L1_PUTS 0 <--
OLSX Fwd_GETX 0 <--
OLSX Fwd_GETS 0 <--
OLSX Fwd_DMA 0 <--
OLSX L2_Replacement 0 <--
SLS L1_GETS 0 <--
SLS L1_GETX 0 <--
SLS L1_PUTX 0 <--
SLS L1_PUTS_only 0 <--
SLS L1_PUTS 0 <--
SLS Inv 0 <--
SLS L2_Replacement 0 <--
M L1_GETS 233418
M L1_GETX 125831
M L1_PUTO 0 <--
M L1_PUTX 0 <--
M L1_PUTS 0 <--
M Fwd_GETX 0 <--
M Fwd_GETS 0 <--
M Fwd_DMA 0 <--
M L2_Replacement 0 <--
IFGX L1_GETS 0 <--
IFGX L1_GETX 0 <--
IFGX L1_PUTO 0 <--
IFGX L1_PUTX 0 <--
IFGX L1_PUTS_only 0 <--
IFGX L1_PUTS 0 <--
IFGX Fwd_GETX 0 <--
IFGX Fwd_GETS 0 <--
IFGX Fwd_DMA 0 <--
IFGX Inv 0 <--
IFGX Data 0 <--
IFGX Data_Exclusive 0 <--
IFGX L2_Replacement 0 <--
IFGS L1_GETS 0 <--
IFGS L1_GETX 0 <--
IFGS L1_PUTO 0 <--
IFGS L1_PUTX 0 <--
IFGS L1_PUTS_only 0 <--
IFGS L1_PUTS 0 <--
IFGS Fwd_GETX 0 <--
IFGS Fwd_GETS 0 <--
IFGS Fwd_DMA 0 <--
IFGS Inv 0 <--
IFGS Data 0 <--
IFGS Data_Exclusive 0 <--
IFGS L2_Replacement 0 <--
ISFGS L1_GETS 0 <--
ISFGS L1_GETX 0 <--
ISFGS L1_PUTO 0 <--
ISFGS L1_PUTX 0 <--
ISFGS L1_PUTS_only 0 <--
ISFGS L1_PUTS 0 <--
ISFGS Fwd_GETX 0 <--
ISFGS Fwd_GETS 0 <--
ISFGS Fwd_DMA 0 <--
ISFGS Inv 0 <--
ISFGS Data 0 <--
ISFGS L2_Replacement 0 <--
IFGXX L1_GETS 0 <--
IFGXX L1_GETX 0 <--
IFGXX L1_PUTO 0 <--
IFGXX L1_PUTX 0 <--
IFGXX L1_PUTS_only 0 <--
IFGXX L1_PUTS 0 <--
IFGXX Fwd_GETX 0 <--
IFGXX Fwd_GETS 0 <--
IFGXX Fwd_DMA 0 <--
IFGXX Inv 0 <--
IFGXX IntAck 0 <--
IFGXX All_Acks 0 <--
IFGXX Data_Exclusive 0 <--
IFGXX L2_Replacement 0 <--
OFGX L1_GETS 0 <--
OFGX L1_GETX 0 <--
OFGX L1_PUTO 0 <--
OFGX L1_PUTX 0 <--
OFGX L1_PUTS_only 0 <--
OFGX L1_PUTS 0 <--
OFGX Fwd_GETX 0 <--
OFGX Fwd_GETS 0 <--
OFGX Fwd_DMA 0 <--
OFGX Inv 0 <--
OFGX L2_Replacement 0 <--
OLSF L1_GETS 0 <--
OLSF L1_GETX 0 <--
OLSF L1_PUTO 0 <--
OLSF L1_PUTX 0 <--
OLSF L1_PUTS_only 0 <--
OLSF L1_PUTS 0 <--
OLSF Fwd_GETX 0 <--
OLSF Fwd_GETS 0 <--
OLSF Fwd_DMA 0 <--
OLSF Inv 0 <--
OLSF IntAck 0 <--
OLSF All_Acks 0 <--
OLSF L2_Replacement 0 <--
ILOW L1_GETS 0 <--
ILOW L1_GETX 0 <--
ILOW L1_PUTO 0 <--
ILOW L1_PUTX 0 <--
ILOW L1_PUTS_only 0 <--
ILOW L1_PUTS 0 <--
ILOW Fwd_GETX 0 <--
ILOW Fwd_GETS 0 <--
ILOW Fwd_DMA 0 <--
ILOW Inv 0 <--
ILOW L1_WBCLEANDATA 0 <--
ILOW L1_WBDIRTYDATA 0 <--
ILOW Unblock 0 <--
ILOW L2_Replacement 0 <--
ILOXW L1_GETS 0 <--
ILOXW L1_GETX 0 <--
ILOXW L1_PUTO 0 <--
ILOXW L1_PUTX 0 <--
ILOXW L1_PUTS_only 0 <--
ILOXW L1_PUTS 0 <--
ILOXW Fwd_GETX 0 <--
ILOXW Fwd_GETS 0 <--
ILOXW Fwd_DMA 0 <--
ILOXW Inv 0 <--
ILOXW L1_WBCLEANDATA 0 <--
ILOXW L1_WBDIRTYDATA 0 <--
ILOXW Unblock 0 <--
ILOXW L2_Replacement 0 <--
ILOSW L1_GETS 0 <--
ILOSW L1_GETX 0 <--
ILOSW L1_PUTO 0 <--
ILOSW L1_PUTX 0 <--
ILOSW L1_PUTS_only 0 <--
ILOSW L1_PUTS 0 <--
ILOSW Fwd_GETX 0 <--
ILOSW Fwd_GETS 0 <--
ILOSW Fwd_DMA 0 <--
ILOSW Inv 0 <--
ILOSW L1_WBCLEANDATA 0 <--
ILOSW L1_WBDIRTYDATA 0 <--
ILOSW Unblock 0 <--
ILOSW L2_Replacement 0 <--
ILOSXW L1_GETS 0 <--
ILOSXW L1_GETX 0 <--
ILOSXW L1_PUTO 0 <--
ILOSXW L1_PUTX 0 <--
ILOSXW L1_PUTS_only 0 <--
ILOSXW L1_PUTS 0 <--
ILOSXW Fwd_GETX 0 <--
ILOSXW Fwd_GETS 0 <--
ILOSXW Fwd_DMA 0 <--
ILOSXW Inv 0 <--
ILOSXW L1_WBCLEANDATA 0 <--
ILOSXW L1_WBDIRTYDATA 0 <--
ILOSXW Unblock 0 <--
ILOSXW L2_Replacement 0 <--
SLSW L1_GETS 0 <--
SLSW L1_GETX 0 <--
SLSW L1_PUTO 0 <--
SLSW L1_PUTX 0 <--
SLSW L1_PUTS_only 0 <--
SLSW L1_PUTS 0 <--
SLSW Fwd_GETX 0 <--
SLSW Fwd_GETS 0 <--
SLSW Fwd_DMA 0 <--
SLSW Inv 0 <--
SLSW Unblock 0 <--
SLSW L2_Replacement 0 <--
OLSW L1_GETS 0 <--
OLSW L1_GETX 0 <--
OLSW L1_PUTO 0 <--
OLSW L1_PUTX 0 <--
OLSW L1_PUTS_only 0 <--
OLSW L1_PUTS 0 <--
OLSW Fwd_GETX 0 <--
OLSW Fwd_GETS 0 <--
OLSW Fwd_DMA 0 <--
OLSW Inv 0 <--
OLSW Unblock 0 <--
OLSW L2_Replacement 0 <--
ILSW L1_GETS 0 <--
ILSW L1_GETX 0 <--
ILSW L1_PUTO 0 <--
ILSW L1_PUTX 0 <--
ILSW L1_PUTS_only 0 <--
ILSW L1_PUTS 0 <--
ILSW Fwd_GETX 0 <--
ILSW Fwd_GETS 0 <--
ILSW Fwd_DMA 0 <--
ILSW Inv 0 <--
ILSW L1_WBCLEANDATA 0 <--
ILSW Unblock 0 <--
ILSW L2_Replacement 0 <--
IW L1_GETS 0 <--
IW L1_GETX 0 <--
IW L1_PUTO 0 <--
IW L1_PUTX 0 <--
IW L1_PUTS_only 0 <--
IW L1_PUTS 0 <--
IW Fwd_GETX 0 <--
IW Fwd_GETS 0 <--
IW Fwd_DMA 0 <--
IW Inv 0 <--
IW L1_WBCLEANDATA 0 <--
IW L2_Replacement 0 <--
OW L1_GETS 0 <--
OW L1_GETX 0 <--
OW L1_PUTO 0 <--
OW L1_PUTX 0 <--
OW L1_PUTS_only 0 <--
OW L1_PUTS 0 <--
OW Fwd_GETX 0 <--
OW Fwd_GETS 0 <--
OW Fwd_DMA 0 <--
OW Inv 0 <--
OW Unblock 0 <--
OW L2_Replacement 0 <--
SW L1_GETS 0 <--
SW L1_GETX 0 <--
SW L1_PUTO 0 <--
SW L1_PUTX 0 <--
SW L1_PUTS_only 0 <--
SW L1_PUTS 0 <--
SW Fwd_GETX 0 <--
SW Fwd_GETS 0 <--
SW Fwd_DMA 0 <--
SW Inv 0 <--
SW Unblock 0 <--
SW L2_Replacement 0 <--
OXW L1_GETS 0 <--
OXW L1_GETX 0 <--
OXW L1_PUTO 0 <--
OXW L1_PUTX 0 <--
OXW L1_PUTS_only 0 <--
OXW L1_PUTS 0 <--
OXW Fwd_GETX 0 <--
OXW Fwd_GETS 0 <--
OXW Fwd_DMA 0 <--
OXW Inv 0 <--
OXW Unblock 0 <--
OXW L2_Replacement 0 <--
OLSXW L1_GETS 0 <--
OLSXW L1_GETX 0 <--
OLSXW L1_PUTO 0 <--
OLSXW L1_PUTX 0 <--
OLSXW L1_PUTS_only 0 <--
OLSXW L1_PUTS 0 <--
OLSXW Fwd_GETX 0 <--
OLSXW Fwd_GETS 0 <--
OLSXW Fwd_DMA 0 <--
OLSXW Inv 0 <--
OLSXW Unblock 0 <--
OLSXW L2_Replacement 0 <--
ILXW L1_GETS 74
ILXW L1_GETX 30
ILXW L1_PUTO 0 <--
ILXW L1_PUTX 0 <--
ILXW L1_PUTS_only 0 <--
ILXW L1_PUTS 0 <--
ILXW Fwd_GETX 0 <--
ILXW Fwd_GETS 0 <--
ILXW Fwd_DMA 0 <--
ILXW Inv 0 <--
ILXW Data 0 <--
ILXW L1_WBCLEANDATA 2626
ILXW L1_WBDIRTYDATA 358053
ILXW Unblock 0 <--
ILXW L2_Replacement 0 <--
IFLS L1_GETS 0 <--
IFLS L1_GETX 0 <--
IFLS L1_PUTO 0 <--
IFLS L1_PUTX 0 <--
IFLS L1_PUTS_only 0 <--
IFLS L1_PUTS 0 <--
IFLS Fwd_GETX 0 <--
IFLS Fwd_GETS 0 <--
IFLS Fwd_DMA 0 <--
IFLS Inv 0 <--
IFLS Unblock 0 <--
IFLS L2_Replacement 0 <--
IFLO L1_GETS 0 <--
IFLO L1_GETX 0 <--
IFLO L1_PUTO 0 <--
IFLO L1_PUTX 0 <--
IFLO L1_PUTS_only 0 <--
IFLO L1_PUTS 0 <--
IFLO Fwd_GETX 0 <--
IFLO Fwd_GETS 0 <--
IFLO Fwd_DMA 0 <--
IFLO Inv 0 <--
IFLO Unblock 0 <--
IFLO L2_Replacement 0 <--
IFLOX L1_GETS 0 <--
IFLOX L1_GETX 0 <--
IFLOX L1_PUTO 0 <--
IFLOX L1_PUTX 0 <--
IFLOX L1_PUTS_only 0 <--
IFLOX L1_PUTS 0 <--
IFLOX Fwd_GETX 0 <--
IFLOX Fwd_GETS 0 <--
IFLOX Fwd_DMA 0 <--
IFLOX Inv 0 <--
IFLOX Unblock 0 <--
IFLOX Exclusive_Unblock 0 <--
IFLOX L2_Replacement 0 <--
IFLOXX L1_GETS 0 <--
IFLOXX L1_GETX 0 <--
IFLOXX L1_PUTO 0 <--
IFLOXX L1_PUTX 0 <--
IFLOXX L1_PUTS_only 0 <--
IFLOXX L1_PUTS 0 <--
IFLOXX Fwd_GETX 0 <--
IFLOXX Fwd_GETS 0 <--
IFLOXX Fwd_DMA 0 <--
IFLOXX Inv 0 <--
IFLOXX Unblock 0 <--
IFLOXX Exclusive_Unblock 0 <--
IFLOXX L2_Replacement 0 <--
IFLOSX L1_GETS 0 <--
IFLOSX L1_GETX 0 <--
IFLOSX L1_PUTO 0 <--
IFLOSX L1_PUTX 0 <--
IFLOSX L1_PUTS_only 0 <--
IFLOSX L1_PUTS 0 <--
IFLOSX Fwd_GETX 0 <--
IFLOSX Fwd_GETS 0 <--
IFLOSX Fwd_DMA 0 <--
IFLOSX Inv 0 <--
IFLOSX Unblock 0 <--
IFLOSX Exclusive_Unblock 0 <--
IFLOSX L2_Replacement 0 <--
IFLXO L1_GETS 0 <--
IFLXO L1_GETX 0 <--
IFLXO L1_PUTO 0 <--
IFLXO L1_PUTX 0 <--
IFLXO L1_PUTS_only 0 <--
IFLXO L1_PUTS 0 <--
IFLXO Fwd_GETX 0 <--
IFLXO Fwd_GETS 0 <--
IFLXO Fwd_DMA 0 <--
IFLXO Inv 0 <--
IFLXO Exclusive_Unblock 0 <--
IFLXO L2_Replacement 0 <--
IGS L1_GETS 0 <--
IGS L1_GETX 0 <--
IGS L1_PUTO 0 <--
IGS L1_PUTX 0 <--
IGS L1_PUTS_only 0 <--
IGS L1_PUTS 0 <--
IGS Fwd_GETX 0 <--
IGS Fwd_GETS 0 <--
IGS Fwd_DMA 0 <--
IGS Own_GETX 0 <--
IGS Inv 0 <--
IGS Data 0 <--
IGS Data_Exclusive 991
IGS Unblock 0 <--
IGS Exclusive_Unblock 991
IGS L2_Replacement 0 <--
IGM L1_GETS 0 <--
IGM L1_GETX 0 <--
IGM L1_PUTO 0 <--
IGM L1_PUTX 0 <--
IGM L1_PUTS_only 0 <--
IGM L1_PUTS 0 <--
IGM Fwd_GETX 0 <--
IGM Fwd_GETS 0 <--
IGM Fwd_DMA 0 <--
IGM Own_GETX 0 <--
IGM Inv 0 <--
IGM ExtAck 0 <--
IGM Data 506
IGM Data_Exclusive 0 <--
IGM L2_Replacement 0 <--
IGMLS L1_GETS 0 <--
IGMLS L1_GETX 0 <--
IGMLS L1_PUTO 0 <--
IGMLS L1_PUTX 0 <--
IGMLS L1_PUTS_only 0 <--
IGMLS L1_PUTS 0 <--
IGMLS Inv 0 <--
IGMLS IntAck 0 <--
IGMLS ExtAck 0 <--
IGMLS All_Acks 0 <--
IGMLS Data 0 <--
IGMLS Data_Exclusive 0 <--
IGMLS L2_Replacement 0 <--
IGMO L1_GETS 0 <--
IGMO L1_GETX 0 <--
IGMO L1_PUTO 0 <--
IGMO L1_PUTX 0 <--
IGMO L1_PUTS_only 0 <--
IGMO L1_PUTS 0 <--
IGMO Fwd_GETX 0 <--
IGMO Fwd_GETS 0 <--
IGMO Fwd_DMA 0 <--
IGMO Own_GETX 0 <--
IGMO ExtAck 0 <--
IGMO All_Acks 506
IGMO Exclusive_Unblock 506
IGMO L2_Replacement 0 <--
IGMIO L1_GETS 0 <--
IGMIO L1_GETX 0 <--
IGMIO L1_PUTO 0 <--
IGMIO L1_PUTX 0 <--
IGMIO L1_PUTS_only 0 <--
IGMIO L1_PUTS 0 <--
IGMIO Fwd_GETX 0 <--
IGMIO Fwd_GETS 0 <--
IGMIO Fwd_DMA 0 <--
IGMIO Own_GETX 0 <--
IGMIO ExtAck 0 <--
IGMIO All_Acks 0 <--
OGMIO L1_GETS 0 <--
OGMIO L1_GETX 0 <--
OGMIO L1_PUTO 0 <--
OGMIO L1_PUTX 0 <--
OGMIO L1_PUTS_only 0 <--
OGMIO L1_PUTS 0 <--
OGMIO Fwd_GETX 0 <--
OGMIO Fwd_GETS 0 <--
OGMIO Fwd_DMA 0 <--
OGMIO Own_GETX 0 <--
OGMIO ExtAck 0 <--
OGMIO All_Acks 0 <--
IGMIOF L1_GETS 0 <--
IGMIOF L1_GETX 0 <--
IGMIOF L1_PUTO 0 <--
IGMIOF L1_PUTX 0 <--
IGMIOF L1_PUTS_only 0 <--
IGMIOF L1_PUTS 0 <--
IGMIOF IntAck 0 <--
IGMIOF All_Acks 0 <--
IGMIOF Data_Exclusive 0 <--
IGMIOFS L1_GETS 0 <--
IGMIOFS L1_GETX 0 <--
IGMIOFS L1_PUTO 0 <--
IGMIOFS L1_PUTX 0 <--
IGMIOFS L1_PUTS_only 0 <--
IGMIOFS L1_PUTS 0 <--
IGMIOFS Fwd_GETX 0 <--
IGMIOFS Fwd_GETS 0 <--
IGMIOFS Fwd_DMA 0 <--
IGMIOFS Inv 0 <--
IGMIOFS Data 0 <--
IGMIOFS L2_Replacement 0 <--
OGMIOF L1_GETS 0 <--
OGMIOF L1_GETX 0 <--
OGMIOF L1_PUTO 0 <--
OGMIOF L1_PUTX 0 <--
OGMIOF L1_PUTS_only 0 <--
OGMIOF L1_PUTS 0 <--
OGMIOF IntAck 0 <--
OGMIOF All_Acks 0 <--
II L1_GETS 0 <--
II L1_GETX 0 <--
II L1_PUTO 0 <--
II L1_PUTX 0 <--
II L1_PUTS_only 0 <--
II L1_PUTS 0 <--
II IntAck 0 <--
II All_Acks 0 <--
MM L1_GETS 0 <--
MM L1_GETX 0 <--
MM L1_PUTO 0 <--
MM L1_PUTX 0 <--
MM L1_PUTS_only 0 <--
MM L1_PUTS 0 <--
MM Fwd_GETX 0 <--
MM Fwd_GETS 0 <--
MM Fwd_DMA 0 <--
MM Inv 0 <--
MM Exclusive_Unblock 125831
MM L2_Replacement 0 <--
SS L1_GETS 0 <--
SS L1_GETX 0 <--
SS L1_PUTO 0 <--
SS L1_PUTX 0 <--
SS L1_PUTS_only 0 <--
SS L1_PUTS 0 <--
SS Fwd_GETX 0 <--
SS Fwd_GETS 0 <--
SS Fwd_DMA 0 <--
SS Inv 0 <--
SS Unblock 0 <--
SS L2_Replacement 0 <--
OO L1_GETS 0 <--
OO L1_GETX 0 <--
OO L1_PUTO 0 <--
OO L1_PUTX 0 <--
OO L1_PUTS_only 0 <--
OO L1_PUTS 0 <--
OO Fwd_GETX 0 <--
OO Fwd_GETS 0 <--
OO Fwd_DMA 0 <--
OO Inv 0 <--
OO Unblock 0 <--
OO Exclusive_Unblock 233415
OO L2_Replacement 0 <--
OLSS L1_GETS 0 <--
OLSS L1_GETX 0 <--
OLSS L1_PUTO 0 <--
OLSS L1_PUTX 0 <--
OLSS L1_PUTS_only 0 <--
OLSS L1_PUTS 0 <--
OLSS Fwd_GETX 0 <--
OLSS Fwd_GETS 0 <--
OLSS Fwd_DMA 0 <--
OLSS Inv 0 <--
OLSS Unblock 0 <--
OLSS L2_Replacement 0 <--
OLSXS L1_GETS 0 <--
OLSXS L1_GETX 0 <--
OLSXS L1_PUTO 0 <--
OLSXS L1_PUTX 0 <--
OLSXS L1_PUTS_only 0 <--
OLSXS L1_PUTS 0 <--
OLSXS Fwd_GETX 0 <--
OLSXS Fwd_GETS 0 <--
OLSXS Fwd_DMA 0 <--
OLSXS Inv 0 <--
OLSXS Unblock 0 <--
OLSXS L2_Replacement 0 <--
SLSS L1_GETS 0 <--
SLSS L1_GETX 0 <--
SLSS L1_PUTO 0 <--
SLSS L1_PUTX 0 <--
SLSS L1_PUTS_only 0 <--
SLSS L1_PUTS 0 <--
SLSS Fwd_GETX 0 <--
SLSS Fwd_GETS 0 <--
SLSS Fwd_DMA 0 <--
SLSS Inv 0 <--
SLSS Unblock 0 <--
SLSS L2_Replacement 0 <--
OI L1_GETS 0 <--
OI L1_GETX 0 <--
OI L1_PUTO 0 <--
OI L1_PUTX 0 <--
OI L1_PUTS_only 0 <--
OI L1_PUTS 0 <--
OI Fwd_GETX 0 <--
OI Fwd_GETS 0 <--
OI Fwd_DMA 0 <--
OI Writeback_Ack 0 <--
OI Writeback_Nack 0 <--
OI L2_Replacement 0 <--
MI L1_GETS 0 <--
MI L1_GETX 0 <--
MI L1_PUTO 0 <--
MI L1_PUTX 0 <--
MI L1_PUTS_only 0 <--
MI L1_PUTS 0 <--
MI Fwd_GETX 0 <--
MI Fwd_GETS 0 <--
MI Fwd_DMA 0 <--
MI Writeback_Ack 0 <--
MI L2_Replacement 0 <--
MII L1_GETS 0 <--
MII L1_GETX 0 <--
MII L1_PUTO 0 <--
MII L1_PUTX 0 <--
MII L1_PUTS_only 0 <--
MII L1_PUTS 0 <--
MII Writeback_Ack 0 <--
MII Writeback_Nack 0 <--
MII L2_Replacement 0 <--
OLSI L1_GETS 0 <--
OLSI L1_GETX 0 <--
OLSI L1_PUTO 0 <--
OLSI L1_PUTX 0 <--
OLSI L1_PUTS_only 0 <--
OLSI L1_PUTS 0 <--
OLSI Fwd_GETX 0 <--
OLSI Fwd_GETS 0 <--
OLSI Fwd_DMA 0 <--
OLSI Writeback_Ack 0 <--
OLSI L2_Replacement 0 <--
ILSI L1_GETS 0 <--
ILSI L1_GETX 0 <--
ILSI L1_PUTO 0 <--
ILSI L1_PUTX 0 <--
ILSI L1_PUTS_only 0 <--
ILSI L1_PUTS 0 <--
ILSI IntAck 0 <--
ILSI All_Acks 0 <--
ILSI Writeback_Ack 0 <--
ILSI L2_Replacement 0 <--
|
