summaryrefslogtreecommitdiff
path: root/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout
blob: 96bce5cecadf83b4ca1f567afd5cce6082220ff5 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Redirecting stdout to build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby/simerr
M5 Simulator System

Copyright (c) 2001-2008
The Regents of The University of Michigan
All Rights Reserved


M5 compiled Nov 18 2009 16:36:52
M5 revision c1d634e76817 6798 default qtip tip brad/ruby_memtest_refresh
M5 started Nov 18 2009 16:37:05
M5 executing on cabr0354
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0.  Starting simulation...
Exiting @ tick 60455258 because maximum number of loads reached