path: root/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.963613                       # Number of seconds simulated
sim_ticks                                1963612574000                       # Number of ticks simulated
final_tick                               1963612574000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 811462                       # Simulator instruction rate (inst/s)
host_op_rate                                   811461                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            26156331100                       # Simulator tick rate (ticks/s)
host_mem_usage                                 332076                       # Number of bytes of host memory used
host_seconds                                    75.07                       # Real time elapsed on the host
sim_insts                                    60918165                       # Number of instructions simulated
sim_ops                                      60918165                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.inst           830784                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         24731648                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst            28416                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           436224                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             26028032                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       830784                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst        28416                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          859200                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7709248                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7709248                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst             12981                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            386432                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst               444                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              6816                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                406688                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          120457                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               120457                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              423090                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            12594973                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               14471                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              222154                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide               489                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                13255177                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         423090                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          14471                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             437561                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3926053                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3926053                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3926053                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             423090                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           12594973                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              14471                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             222154                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide              489                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               17181230                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        406688                       # Number of read requests accepted
system.physmem.writeReqs                       120457                       # Number of write requests accepted
system.physmem.readBursts                      406688                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     120457                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 26019904                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      8128                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7707200                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  26028032                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7709248                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      127                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               25130                       # Per bank write bursts
system.physmem.perBankRdBursts::1               25381                       # Per bank write bursts
system.physmem.perBankRdBursts::2               25483                       # Per bank write bursts
system.physmem.perBankRdBursts::3               24909                       # Per bank write bursts
system.physmem.perBankRdBursts::4               25165                       # Per bank write bursts
system.physmem.perBankRdBursts::5               25252                       # Per bank write bursts
system.physmem.perBankRdBursts::6               25797                       # Per bank write bursts
system.physmem.perBankRdBursts::7               25541                       # Per bank write bursts
system.physmem.perBankRdBursts::8               25672                       # Per bank write bursts
system.physmem.perBankRdBursts::9               25333                       # Per bank write bursts
system.physmem.perBankRdBursts::10              25279                       # Per bank write bursts
system.physmem.perBankRdBursts::11              25593                       # Per bank write bursts
system.physmem.perBankRdBursts::12              25647                       # Per bank write bursts
system.physmem.perBankRdBursts::13              25645                       # Per bank write bursts
system.physmem.perBankRdBursts::14              25712                       # Per bank write bursts
system.physmem.perBankRdBursts::15              25022                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7825                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7603                       # Per bank write bursts
system.physmem.perBankWrBursts::2                7492                       # Per bank write bursts
system.physmem.perBankWrBursts::3                6933                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7149                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7135                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7628                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7255                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7538                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7229                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7235                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7425                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7840                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8302                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8309                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7527                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          17                       # Number of times write queue was full causing retry
system.physmem.totGap                    1963565980500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  406688                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 120457                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    406481                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                        67                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1864                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3207                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5887                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6006                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6734                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6782                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7812                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     9118                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7274                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     8021                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8672                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     7905                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7057                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7090                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     6181                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     5787                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5675                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5594                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      147                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      185                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      128                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      129                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       80                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                       99                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                       95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                       88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      157                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      224                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      150                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      165                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      147                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      178                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      114                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      134                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      141                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      148                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      129                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       64                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      120                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       59                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       38                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       55                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        66393                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      507.991867                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     305.024910                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     413.812380                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          15899     23.95%     23.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        12177     18.34%     42.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5415      8.16%     50.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3379      5.09%     55.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2311      3.48%     59.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         2006      3.02%     62.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1513      2.28%     64.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1280      1.93%     66.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        22413     33.76%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          66393                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5392                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        75.397255                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     2872.179140                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191           5389     99.94%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5392                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5392                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        22.334013                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.995867                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       21.838616                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23            4788     88.80%     88.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31              33      0.61%     89.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39             252      4.67%     94.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47              18      0.33%     94.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55               6      0.11%     94.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63              13      0.24%     94.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71              10      0.19%     94.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79               1      0.02%     94.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87              18      0.33%     95.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95              18      0.33%     95.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103            190      3.52%     99.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111             3      0.06%     99.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119             1      0.02%     99.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127             7      0.13%     99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135             1      0.02%     99.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143             1      0.02%     99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151             1      0.02%     99.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159             2      0.04%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167             1      0.02%     99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175             6      0.11%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183             2      0.04%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191             2      0.04%     99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199             3      0.06%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215             1      0.02%     99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231            13      0.24%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5392                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2148968000                       # Total ticks spent queuing
system.physmem.totMemAccLat                9771986750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2032805000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        5285.72                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  24035.72                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          13.25                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.93                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       13.26                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.93                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.13                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.10                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.84                       # Average write queue length when enqueuing
system.physmem.readRowHits                     364299                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     96294                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   89.61                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  79.94                       # Row buffer hit rate for writes
system.physmem.avgGap                      3724906.77                       # Average gap between requests
system.physmem.pageHitRate                      87.40                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  248179680                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  135415500                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1580732400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                382449600                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           128253237840                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            66024340605                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1120248020250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1316872375875                       # Total energy per rank (pJ)
system.physmem_0.averagePower              670.639531                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   1863393486000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     65569140000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     34644235250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  253751400                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  138455625                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1590443400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                397904400                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           128253237840                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            66573650745                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1119766169250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1316973612660                       # Total energy per rank (pJ)
system.physmem_1.averagePower              670.691088                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   1862592163500                       # Time in different power states
system.physmem_1.memoryStateTime::REF     65569140000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     35445557750                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     7494168                       # DTB read hits
system.cpu0.dtb.read_misses                      7443                       # DTB read misses
system.cpu0.dtb.read_acv                          210                       # DTB read access violations
system.cpu0.dtb.read_accesses                  490673                       # DTB read accesses
system.cpu0.dtb.write_hits                    5065702                       # DTB write hits
system.cpu0.dtb.write_misses                      813                       # DTB write misses
system.cpu0.dtb.write_acv                         134                       # DTB write access violations
system.cpu0.dtb.write_accesses                 187452                       # DTB write accesses
system.cpu0.dtb.data_hits                    12559870                       # DTB hits
system.cpu0.dtb.data_misses                      8256                       # DTB misses
system.cpu0.dtb.data_acv                          344                       # DTB access violations
system.cpu0.dtb.data_accesses                  678125                       # DTB accesses
system.cpu0.itb.fetch_hits                    3501177                       # ITB hits
system.cpu0.itb.fetch_misses                     3871                       # ITB misses
system.cpu0.itb.fetch_acv                         184                       # ITB acv
system.cpu0.itb.fetch_accesses                3505048                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numPwrStateTransitions              13591                       # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples         6796                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean    272307750.367863                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev   432682187.397928                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10         6796    100.00%    100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value        55000                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value   2000000000                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total           6796                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON   113009102500                       # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 1850603471500                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                      3925790590                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    6796                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    164911                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   56822     40.19%     40.19% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    131      0.09%     40.28% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1974      1.40%     41.68% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                    422      0.30%     41.97% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                  82045     58.03%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              141394                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    56288     49.08%     49.08% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     131      0.11%     49.20% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1974      1.72%     50.92% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                     422      0.37%     51.29% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   55866     48.71%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               114681                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1901241129000     96.86%     96.86% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               93739000      0.00%     96.86% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              789776000      0.04%     96.90% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30              316619500      0.02%     96.92% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            60454001500      3.08%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1962895265000                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.990602                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.680919                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.811074                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         8      3.60%      3.60% # number of syscalls executed
system.cpu0.kern.syscall::3                        19      8.56%     12.16% # number of syscalls executed
system.cpu0.kern.syscall::4                         4      1.80%     13.96% # number of syscalls executed
system.cpu0.kern.syscall::6                        32     14.41%     28.38% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.45%     28.83% # number of syscalls executed
system.cpu0.kern.syscall::17                        9      4.05%     32.88% # number of syscalls executed
system.cpu0.kern.syscall::19                       10      4.50%     37.39% # number of syscalls executed
system.cpu0.kern.syscall::20                        6      2.70%     40.09% # number of syscalls executed
system.cpu0.kern.syscall::23                        1      0.45%     40.54% # number of syscalls executed
system.cpu0.kern.syscall::24                        3      1.35%     41.89% # number of syscalls executed
system.cpu0.kern.syscall::33                        7      3.15%     45.05% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.90%     45.95% # number of syscalls executed
system.cpu0.kern.syscall::45                       36     16.22%     62.16% # number of syscalls executed
system.cpu0.kern.syscall::47                        3      1.35%     63.51% # number of syscalls executed
system.cpu0.kern.syscall::48                       10      4.50%     68.02% # number of syscalls executed
system.cpu0.kern.syscall::54                       10      4.50%     72.52% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.45%     72.97% # number of syscalls executed
system.cpu0.kern.syscall::59                        6      2.70%     75.68% # number of syscalls executed
system.cpu0.kern.syscall::71                       23     10.36%     86.04% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.35%     87.39% # number of syscalls executed
system.cpu0.kern.syscall::74                        6      2.70%     90.09% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.45%     90.54% # number of syscalls executed
system.cpu0.kern.syscall::90                        3      1.35%     91.89% # number of syscalls executed
system.cpu0.kern.syscall::92                        9      4.05%     95.95% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.90%     96.85% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.90%     97.75% # number of syscalls executed
system.cpu0.kern.syscall::132                       1      0.45%     98.20% # number of syscalls executed
system.cpu0.kern.syscall::144                       2      0.90%     99.10% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.90%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   222                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                  504      0.34%      0.34% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.34% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.34% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.34% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3063      2.05%      2.39% # number of callpals executed
system.cpu0.kern.callpal::tbi                      51      0.03%      2.42% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.42% # number of callpals executed
system.cpu0.kern.callpal::swpipl               134533     89.85%     92.28% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6700      4.47%     96.75% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.75% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     3      0.00%     96.75% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     9      0.01%     96.76% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     96.76% # number of callpals executed
system.cpu0.kern.callpal::rti                    4333      2.89%     99.65% # number of callpals executed
system.cpu0.kern.callpal::callsys                 381      0.25%     99.91% # number of callpals executed
system.cpu0.kern.callpal::imb                     136      0.09%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                149727                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             6886                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1282                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1282                      
system.cpu0.kern.mode_good::user                 1282                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch_good::kernel     0.186175                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.313908                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1959142459500     99.82%     99.82% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          3540793500      0.18%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3064                       # number of times the context was actually changed
system.cpu0.committedInsts                   47755591                       # Number of instructions committed
system.cpu0.committedOps                     47755591                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             44289668                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                210363                       # Number of float alu accesses
system.cpu0.num_func_calls                    1202061                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      5613734                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    44289668                       # number of integer instructions
system.cpu0.num_fp_insts                       210363                       # number of float instructions
system.cpu0.num_int_register_reads           60881629                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          33006420                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              102169                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             104020                       # number of times the floating registers were written
system.cpu0.num_mem_refs                     12600044                       # number of memory refs
system.cpu0.num_load_insts                    7521304                       # Number of load instructions
system.cpu0.num_store_insts                   5078740                       # Number of store instructions
system.cpu0.num_idle_cycles              3699854946.150013                       # Number of idle cycles
system.cpu0.num_busy_cycles              225935643.849987                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.057552                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.942448                       # Percentage of idle cycles
system.cpu0.Branches                          7206590                       # Number of branches fetched
system.cpu0.op_class::No_OpClass              2726655      5.71%      5.71% # Class of executed instruction
system.cpu0.op_class::IntAlu                 31439878     65.82%     71.53% # Class of executed instruction
system.cpu0.op_class::IntMult                   52896      0.11%     71.64% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     71.64% # Class of executed instruction
system.cpu0.op_class::FloatAdd                  25705      0.05%     71.70% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     71.70% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     71.70% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     71.70% # Class of executed instruction
system.cpu0.op_class::FloatDiv                   1656      0.00%     71.70% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     71.70% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     71.70% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     71.70% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     71.70% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     71.70% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     71.70% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     71.70% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     71.70% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     71.70% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     71.70% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     71.70% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     71.70% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     71.70% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     71.70% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     71.70% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     71.70% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     71.70% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc                 0      0.00%     71.70% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     71.70% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     71.70% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     71.70% # Class of executed instruction
system.cpu0.op_class::MemRead                 7696642     16.11%     87.81% # Class of executed instruction
system.cpu0.op_class::MemWrite                5084839     10.65%     98.46% # Class of executed instruction
system.cpu0.op_class::IprAccess                735920      1.54%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                  47764191                       # Class of executed instruction
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements          1179864                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          505.229406                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           11369687                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          1180280                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs             9.633042                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        114940500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.229406                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.986776                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.986776                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          416                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          369                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3           47                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.812500                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         51471495                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        51471495                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data      6411173                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        6411173                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      4657733                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       4657733                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       143918                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       143918                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       147952                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       147952                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     11068906                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        11068906                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     11068906                       # number of overall hits
system.cpu0.dcache.overall_hits::total       11068906                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       937797                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       937797                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       251494                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       251494                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13653                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        13653                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         5444                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         5444                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1189291                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1189291                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1189291                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1189291                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  29158420500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  29158420500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  10960256500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  10960256500                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    150265500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    150265500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     47401000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     47401000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  40118677000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  40118677000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  40118677000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  40118677000                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      7348970                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      7348970                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      4909227                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      4909227                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       157571                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       157571                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       153396                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       153396                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     12258197                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     12258197                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     12258197                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     12258197                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.127609                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.127609                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.051229                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.051229                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.086647                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.086647                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.035490                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.035490                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.097020                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.097020                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.097020                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.097020                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31092.465107                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 31092.465107                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43580.588404                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 43580.588404                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11006.042628                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11006.042628                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  8707.016899                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  8707.016899                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33733.272176                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 33733.272176                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33733.272176                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 33733.272176                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks       678308                       # number of writebacks
system.cpu0.dcache.writebacks::total           678308                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       937797                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       937797                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       251494                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       251494                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        13653                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        13653                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         5444                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         5444                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      1189291                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      1189291                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      1189291                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      1189291                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data         7110                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total         7110                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        10837                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        10837                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        17947                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        17947                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  28220623500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  28220623500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  10708762500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  10708762500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    136612500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    136612500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     41957000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     41957000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  38929386000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  38929386000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  38929386000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  38929386000                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1578468500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1578468500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   1578468500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1578468500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.127609                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.127609                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.051229                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.051229                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.086647                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.086647                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.035490                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.035490                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.097020                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.097020                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.097020                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.097020                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 30092.465107                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 30092.465107                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42580.588404                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42580.588404                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10006.042628                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10006.042628                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  7707.016899                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  7707.016899                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32733.272176                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32733.272176                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32733.272176                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32733.272176                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222006.821378                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222006.821378                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87951.663231                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87951.663231                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements           698162                       # number of replacements
system.cpu0.icache.tags.tagsinuse          508.148952                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           47065399                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           698674                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            67.363891                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      42439448500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   508.148952                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.992478                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.992478                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          351                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3          161                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         48462983                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        48462983                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst     47065399                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       47065399                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     47065399                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        47065399                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     47065399                       # number of overall hits
system.cpu0.icache.overall_hits::total       47065399                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       698792                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       698792                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       698792                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        698792                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       698792                       # number of overall misses
system.cpu0.icache.overall_misses::total       698792                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10197257500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  10197257500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  10197257500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  10197257500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  10197257500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  10197257500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     47764191                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     47764191                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     47764191                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     47764191                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     47764191                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     47764191                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014630                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.014630                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014630                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.014630                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014630                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.014630                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14592.693534                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14592.693534                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14592.693534                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14592.693534                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14592.693534                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14592.693534                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks       698162                       # number of writebacks
system.cpu0.icache.writebacks::total           698162                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       698792                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       698792                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       698792                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       698792                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       698792                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       698792                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   9498465500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   9498465500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   9498465500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   9498465500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   9498465500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   9498465500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014630                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014630                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014630                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.014630                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014630                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.014630                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13592.693534                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13592.693534                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13592.693534                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13592.693534                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13592.693534                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13592.693534                       # average overall mshr miss latency
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     2421538                       # DTB read hits
system.cpu1.dtb.read_misses                      2992                       # DTB read misses
system.cpu1.dtb.read_acv                            0                       # DTB read access violations
system.cpu1.dtb.read_accesses                  239363                       # DTB read accesses
system.cpu1.dtb.write_hits                    1759460                       # DTB write hits
system.cpu1.dtb.write_misses                      341                       # DTB write misses
system.cpu1.dtb.write_acv                          29                       # DTB write access violations
system.cpu1.dtb.write_accesses                 105247                       # DTB write accesses
system.cpu1.dtb.data_hits                     4180998                       # DTB hits
system.cpu1.dtb.data_misses                      3333                       # DTB misses
system.cpu1.dtb.data_acv                           29                       # DTB access violations
system.cpu1.dtb.data_accesses                  344610                       # DTB accesses
system.cpu1.itb.fetch_hits                    1965348                       # ITB hits
system.cpu1.itb.fetch_misses                     1216                       # ITB misses
system.cpu1.itb.fetch_acv                           0                       # ITB acv
system.cpu1.itb.fetch_accesses                1966564                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numPwrStateTransitions               5480                       # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples         2740                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean    707616074.452555                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev   409900069.702285                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10         2740    100.00%    100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value        76500                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value    974673500                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total           2740                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON    24744530000                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 1938868044000                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                      3927225148                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2740                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                     78631                       # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0                   26567     38.35%     38.35% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1968      2.84%     41.19% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                    504      0.73%     41.91% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  40242     58.09%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               69281                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                    25724     48.16%     48.16% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1968      3.68%     51.84% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                     504      0.94%     52.79% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                   25220     47.21%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                53416                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1910368546000     97.29%     97.29% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              730956000      0.04%     97.33% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30              356511000      0.02%     97.34% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            52155834000      2.66%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1963611847000                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.968269                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.626708                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total             0.771005                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3                        11     10.58%     10.58% # number of syscalls executed
system.cpu1.kern.syscall::6                        10      9.62%     20.19% # number of syscalls executed
system.cpu1.kern.syscall::15                        1      0.96%     21.15% # number of syscalls executed
system.cpu1.kern.syscall::17                        6      5.77%     26.92% # number of syscalls executed
system.cpu1.kern.syscall::23                        3      2.88%     29.81% # number of syscalls executed
system.cpu1.kern.syscall::24                        3      2.88%     32.69% # number of syscalls executed
system.cpu1.kern.syscall::33                        4      3.85%     36.54% # number of syscalls executed
system.cpu1.kern.syscall::45                       18     17.31%     53.85% # number of syscalls executed
system.cpu1.kern.syscall::47                        3      2.88%     56.73% # number of syscalls executed
system.cpu1.kern.syscall::59                        1      0.96%     57.69% # number of syscalls executed
system.cpu1.kern.syscall::71                       31     29.81%     87.50% # number of syscalls executed
system.cpu1.kern.syscall::74                       10      9.62%     97.12% # number of syscalls executed
system.cpu1.kern.syscall::132                       3      2.88%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                   104                       # number of syscalls executed
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                  422      0.59%      0.59% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.59% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.59% # number of callpals executed
system.cpu1.kern.callpal::swpctx                 2001      2.80%      3.39% # number of callpals executed
system.cpu1.kern.callpal::tbi                       3      0.00%      3.39% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.01%      3.40% # number of callpals executed
system.cpu1.kern.callpal::swpipl                63030     88.06%     91.46% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2146      3.00%     94.46% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.46% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     4      0.01%     94.46% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.00%     94.47% # number of callpals executed
system.cpu1.kern.callpal::rti                    3778      5.28%     99.75% # number of callpals executed
system.cpu1.kern.callpal::callsys                 136      0.19%     99.94% # number of callpals executed
system.cpu1.kern.callpal::imb                      44      0.06%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 71579                       # number of callpals executed
system.cpu1.kern.mode_switch::kernel             2069                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                464                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2878                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                892                      
system.cpu1.kern.mode_good::user                  464                      
system.cpu1.kern.mode_good::idle                  428                      
system.cpu1.kern.mode_switch_good::kernel     0.431126                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.148714                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     0.329699                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel       17834392500      0.91%      0.91% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user          1709021000      0.09%      1.00% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1944068431500     99.00%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                    2002                       # number of times the context was actually changed
system.cpu1.committedInsts                   13162574                       # Number of instructions committed
system.cpu1.committedOps                     13162574                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             12139381                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                173446                       # Number of float alu accesses
system.cpu1.num_func_calls                     411749                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      1304648                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    12139381                       # number of integer instructions
system.cpu1.num_fp_insts                       173446                       # number of float instructions
system.cpu1.num_int_register_reads           16710166                       # number of times the integer registers were read
system.cpu1.num_int_register_writes           8908141                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads               90735                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes              92616                       # number of times the floating registers were written
system.cpu1.num_mem_refs                      4204594                       # number of memory refs
system.cpu1.num_load_insts                    2435865                       # Number of load instructions
system.cpu1.num_store_insts                   1768729                       # Number of store instructions
system.cpu1.num_idle_cycles              3877736087.998025                       # Number of idle cycles
system.cpu1.num_busy_cycles              49489060.001975                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.012602                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.987398                       # Percentage of idle cycles
system.cpu1.Branches                          1871255                       # Number of branches fetched
system.cpu1.op_class::No_OpClass               705493      5.36%      5.36% # Class of executed instruction
system.cpu1.op_class::IntAlu                  7781042     59.10%     64.46% # Class of executed instruction
system.cpu1.op_class::IntMult                   21322      0.16%     64.62% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     64.62% # Class of executed instruction
system.cpu1.op_class::FloatAdd                  14181      0.11%     64.73% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     64.73% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     64.73% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     64.73% # Class of executed instruction
system.cpu1.op_class::FloatDiv                   1986      0.02%     64.74% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     64.74% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     64.74% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     64.74% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     64.74% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     64.74% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     64.74% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     64.74% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     64.74% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     64.74% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     64.74% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     64.74% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     64.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     64.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     64.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     64.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     64.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     64.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc                 0      0.00%     64.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     64.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     64.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     64.74% # Class of executed instruction
system.cpu1.op_class::MemRead                 2507774     19.05%     83.79% # Class of executed instruction
system.cpu1.op_class::MemWrite                1769717     13.44%     97.23% # Class of executed instruction
system.cpu1.op_class::IprAccess                364421      2.77%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  13165936                       # Class of executed instruction
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements           166516                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          486.373615                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            4012325                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           167028                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            24.021871                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle      70707818000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   486.373615                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.949948                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.949948                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0          192                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          255                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           65                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         16958396                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        16958396                       # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data      2257201                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        2257201                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      1642023                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       1642023                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        48215                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        48215                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        50821                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        50821                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      3899224                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         3899224                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      3899224                       # number of overall hits
system.cpu1.dcache.overall_hits::total        3899224                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       118432                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       118432                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data        62660                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total        62660                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         8936                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         8936                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data         5856                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total         5856                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       181092                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        181092                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       181092                       # number of overall misses
system.cpu1.dcache.overall_misses::total       181092                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1454494000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   1454494000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   1265962000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   1265962000                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     82083000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total     82083000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     49296000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     49296000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data         5500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total         5500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   2720456000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   2720456000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   2720456000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   2720456000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      2375633                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      2375633                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      1704683                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      1704683                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        57151                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        57151                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        56677                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        56677                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      4080316                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      4080316                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      4080316                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      4080316                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.049853                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.049853                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.036758                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.036758                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.156358                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.156358                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.103322                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.103322                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.044382                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.044382                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.044382                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.044382                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12281.258444                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12281.258444                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20203.670603                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 20203.670603                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9185.653536                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9185.653536                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  8418.032787                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  8418.032787                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15022.507897                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 15022.507897                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15022.507897                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 15022.507897                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks       114398                       # number of writebacks
system.cpu1.dcache.writebacks::total           114398                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       118432                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       118432                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        62660                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        62660                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         8936                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         8936                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         5856                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total         5856                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       181092                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       181092                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       181092                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       181092                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data           89                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total           89                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         3221                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         3221                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         3310                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total         3310                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1336062000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1336062000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1203302000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1203302000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     73147000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     73147000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     43441000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     43441000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data         4500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total         4500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   2539364000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   2539364000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   2539364000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   2539364000                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     20174000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     20174000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data     20174000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total     20174000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.049853                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.049853                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036758                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.036758                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.156358                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.156358                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.103322                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.103322                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.044382                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.044382                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.044382                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.044382                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11281.258444                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11281.258444                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19203.670603                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19203.670603                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8185.653536                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8185.653536                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  7418.203552                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  7418.203552                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14022.507897                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14022.507897                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14022.507897                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14022.507897                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 226674.157303                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 226674.157303                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data  6094.864048                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total  6094.864048                       # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements           316153                       # number of replacements
system.cpu1.icache.tags.tagsinuse          445.936315                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           12849230                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           316665                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            40.576729                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     1962762014000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   445.936315                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.870969                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.870969                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1            3                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          444                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3           13                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         13482644                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        13482644                       # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst     12849230                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       12849230                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     12849230                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        12849230                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     12849230                       # number of overall hits
system.cpu1.icache.overall_hits::total       12849230                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       316707                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       316707                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       316707                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        316707                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       316707                       # number of overall misses
system.cpu1.icache.overall_misses::total       316707                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4252859000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   4252859000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   4252859000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   4252859000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   4252859000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   4252859000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     13165937                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     13165937                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     13165937                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     13165937                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     13165937                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     13165937                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024055                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.024055                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024055                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.024055                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024055                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.024055                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13428.370702                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13428.370702                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13428.370702                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13428.370702                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13428.370702                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13428.370702                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks       316153                       # number of writebacks
system.cpu1.icache.writebacks::total           316153                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       316707                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       316707                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       316707                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       316707                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       316707                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       316707                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3936152000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   3936152000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3936152000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   3936152000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3936152000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   3936152000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.024055                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.024055                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.024055                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.024055                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.024055                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.024055                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12428.370702                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12428.370702                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12428.370702                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 12428.370702                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12428.370702                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 12428.370702                       # average overall mshr miss latency
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.iobus.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                 7373                       # Transaction distribution
system.iobus.trans_dist::ReadResp                7373                       # Transaction distribution
system.iobus.trans_dist::WriteReq               55610                       # Transaction distribution
system.iobus.trans_dist::WriteResp              55610                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        13904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1014                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18148                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2474                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        42514                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83452                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        83452                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  125966                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        55616                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2749                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9074                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9876                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total        81882                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661616                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total      2661616                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2743498                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             14957500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               764000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 9500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                10000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy              175000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            15839500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy             2459000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             6056000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy               82500                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           216128057                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            28456000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            41948000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements                41694                       # number of replacements
system.iocache.tags.tagsinuse                0.569299                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41710                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1756488432000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     0.569299                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.035581                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.035581                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               375534                       # Number of tag accesses
system.iocache.tags.data_accesses              375534                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::tsunami.ide          174                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
system.iocache.demand_misses::tsunami.ide        41726                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41726                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41726                       # number of overall misses
system.iocache.overall_misses::total            41726                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21854883                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21854883                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::tsunami.ide   4858321174                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4858321174                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide   4880176057                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   4880176057                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide   4880176057                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   4880176057                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          174                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41726                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41726                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41726                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41726                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125602.775862                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 125602.775862                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116921.476078                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 116921.476078                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 116957.677635                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 116957.677635                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 116957.677635                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 116957.677635                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             1                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    1                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs            1                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           41520                       # number of writebacks
system.iocache.writebacks::total                41520                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          174                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          174                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41726                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41726                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41726                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41726                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13154883                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     13154883                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2778324656                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2778324656                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide   2791479539                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   2791479539                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide   2791479539                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   2791479539                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75602.775862                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 75602.775862                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66863.800924                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66863.800924                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66900.242990                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 66900.242990                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66900.242990                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 66900.242990                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                   341504                       # number of replacements
system.l2c.tags.tagsinuse                65213.029486                       # Cycle average of tags in use
system.l2c.tags.total_refs                    3680110                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   406507                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     9.053005                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               9200946000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   55179.216512                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4842.215722                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     5040.815485                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      110.867276                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data       39.914491                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.841968                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.073886                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.076917                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.001692                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.000609                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.995072                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024        65003                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          184                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1         1114                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         5002                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         6095                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        52608                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.991867                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 35882279                       # Number of tag accesses
system.l2c.tags.data_accesses                35882279                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks       792706                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          792706                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks       747201                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total          747201                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data             175                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             534                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 709                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            33                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            24                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                57                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           126431                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            47312                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               173743                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst        685790                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst        316251                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total           1002041                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       663459                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       109055                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           772514                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.inst              685790                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              789890                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              316251                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              156367                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1948298                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst             685790                       # number of overall hits
system.l2c.overall_hits::cpu0.data             789890                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             316251                       # number of overall hits
system.l2c.overall_hits::cpu1.data             156367                       # number of overall hits
system.l2c.overall_hits::total                1948298                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data          2941                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1732                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              4673                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          898                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          897                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1795                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         115557                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           6591                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             122148                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst        12981                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst          455                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           13436                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       271641                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data          237                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         271878                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.inst             12981                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            387198                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst               455                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              6828                       # number of demand (read+write) misses
system.l2c.demand_misses::total                407462                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst            12981                       # number of overall misses
system.l2c.overall_misses::cpu0.data           387198                       # number of overall misses
system.l2c.overall_misses::cpu1.inst              455                       # number of overall misses
system.l2c.overall_misses::cpu1.data             6828                       # number of overall misses
system.l2c.overall_misses::total               407462                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data      1599000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     12643000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     14242000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1259500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       178000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      1437500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   8901595500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    544185500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   9445781000                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst   1065078500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst     37559000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   1102637500                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  19890941000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data     19543500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  19910484500                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1065078500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  28792536500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst     37559000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    563729000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     30458903000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1065078500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  28792536500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst     37559000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    563729000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    30458903000                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks       792706                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       792706                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks       747201                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total       747201                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         3116                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         2266                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            5382                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          931                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          921                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1852                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       241988                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        53903                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           295891                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst       698771                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst       316706                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total       1015477                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       935100                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       109292                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      1044392                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst          698771                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1177088                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          316706                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          163195                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2355760                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         698771                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1177088                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         316706                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         163195                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2355760                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.943838                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.764342                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.868265                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.964554                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.973941                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.969222                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.477532                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.122275                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.412814                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.018577                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.001437                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.013231                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.290494                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.002169                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.260322                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.018577                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.328946                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.001437                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.041840                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.172964                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.018577                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.328946                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.001437                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.041840                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.172964                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   543.692622                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  7299.653580                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  3047.720950                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1402.561247                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   198.439242                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total   800.835655                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 77032.075080                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82564.937035                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 77330.623506                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 82049.033202                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 82547.252747                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 82065.905031                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 73225.105930                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82462.025316                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 73233.157887                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 82049.033202                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 74361.273819                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 82547.252747                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 82561.364968                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 74752.745041                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 82049.033202                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 74361.273819                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 82547.252747                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 82561.364968                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 74752.745041                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks               78937                       # number of writebacks
system.l2c.writebacks::total                    78937                       # number of writebacks
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst           11                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total           11                       # number of ReadCleanReq MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             11                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 11                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            11                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                11                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks           10                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total           10                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         2941                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1732                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         4673                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          898                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          897                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1795                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       115557                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         6591                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        122148                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        12981                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst          444                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        13425                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       271641                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data          237                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       271878                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        12981                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       387198                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst          444                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         6828                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           407451                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        12981                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       387198                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst          444                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         6828                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          407451                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.data         7110                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data           89                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total         7199                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        10837                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         3221                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        14058                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        17947                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data         3310                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        21257                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     58492500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     34311000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     92803500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     17536000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     17907500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     35443500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   7746025500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    478275500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   8224301000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst    935268500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst     32302501                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total    967571001                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  17174531000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data     17173500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  17191704500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    935268500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  24920556500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst     32302501                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    495449000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  26383576501                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    935268500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  24920556500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst     32302501                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    495449000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  26383576501                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1489559500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     19061000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   1508620500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   1489559500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data     19061000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   1508620500                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.943838                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.764342                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.868265                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.964554                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.973941                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.969222                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.477532                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.122275                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.412814                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.018577                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.001402                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.013220                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.290494                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.002169                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.260322                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.018577                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.328946                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.001402                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.041840                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.172959                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.018577                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.328946                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.001402                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.041840                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.172959                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19888.643319                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19810.046189                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19859.512091                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19527.839644                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19963.768116                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 19745.682451                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 67032.075080                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72564.937035                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 67330.623506                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72049.033202                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72753.380631                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72072.327821                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63225.105930                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72462.025316                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63233.157887                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72049.033202                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64361.273819                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72753.380631                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72561.364968                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 64752.759230                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72049.033202                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64361.273819                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72753.380631                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72561.364968                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 64752.759230                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209502.039381                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 214168.539326                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209559.730518                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82997.687636                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data  5758.610272                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 70970.527356                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests        859272                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       411340                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests          409                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq                7199                       # Transaction distribution
system.membus.trans_dist::ReadResp             292676                       # Transaction distribution
system.membus.trans_dist::WriteReq              14058                       # Transaction distribution
system.membus.trans_dist::WriteResp             14058                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       120457                       # Transaction distribution
system.membus.trans_dist::CleanEvict           261938                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            16120                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          11242                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               3                       # Transaction distribution
system.membus.trans_dist::ReadExReq            122469                       # Transaction distribution
system.membus.trans_dist::ReadExResp           121633                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        285477                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        42514                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1182508                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      1225022                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83435                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        83435                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1308457                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        81882                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31079040                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     31160922                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2658240                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2658240                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                33819162                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                            21640                       # Total snoops (count)
system.membus.snoopTraffic                      27008                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            498117                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.001313                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.036211                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  497463     99.87%     99.87% # Request fanout histogram
system.membus.snoop_fanout::1                     654      0.13%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              498117                       # Request fanout histogram
system.membus.reqLayer0.occupancy            40353000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy          1324238537                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer1.occupancy         2174676250                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy             893117                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests      4780466                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      2390280                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests       355276                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops            975                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops          915                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops           60                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq               7199                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2101675                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             14058                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            14058                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       871643                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean      1014315                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          816241                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           16314                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         11299                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          27613                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp            1                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           297840                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          297840                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq       1015499                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      1078979                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq          227                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2095725                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3605435                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       949566                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       535407                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               7186133                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     89403712                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    118812032                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     40502976                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     17791322                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              266510042                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          398828                       # Total snoops (count)
system.toL2Bus.snoopTraffic                   7391616                       # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples          2782920                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.138526                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.345713                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                2397661     86.16%     86.16% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 385012     13.83%     99.99% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                    245      0.01%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                      2      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            2782920                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         4214914494                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           296383                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        1048435504                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1811762602                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         476230655                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         281513896                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states
system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1963612574000                       # Cumulative time (in ticks) in various power states

---------- End Simulation Statistics   ----------