blob: de241166d4904ba421bfb5476b971e936b998a0c (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
|
---------- Begin Simulation Statistics ----------
sim_seconds 1.962054 # Number of seconds simulated
sim_ticks 1962054431000 # Number of ticks simulated
final_tick 1962054431000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2014980 # Simulator instruction rate (inst/s)
host_op_rate 2014979 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 66592137800 # Simulator tick rate (ticks/s)
host_mem_usage 297124 # Number of bytes of host memory used
host_seconds 29.46 # Real time elapsed on the host
sim_insts 59368818 # Number of instructions simulated
sim_ops 59368818 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 834816 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 24594240 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 29056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 572928 # Number of bytes read from this memory
system.physmem.bytes_read::total 28681856 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 834816 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 29056 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 863872 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7716416 # Number of bytes written to this memory
system.physmem.bytes_written::total 7716416 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst 13044 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 384285 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 454 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 8952 # Number of read requests responded to by this memory
system.physmem.num_reads::total 448154 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 120569 # Number of write requests responded to by this memory
system.physmem.num_writes::total 120569 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst 425481 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 12534943 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1351041 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 14809 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 292004 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14618277 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 425481 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 14809 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 440290 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3932825 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3932825 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3932825 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 425481 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 12534943 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1351041 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 14809 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 292004 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 18551102 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 341254 # number of replacements
system.l2c.tagsinuse 65290.172220 # Cycle average of tags in use
system.l2c.total_refs 2492312 # Total number of references to valid blocks.
system.l2c.sampled_refs 406269 # Sample count of references to valid blocks.
system.l2c.avg_refs 6.134635 # Average number of references to valid blocks.
system.l2c.warmup_cycle 7854344000 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 55481.040218 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 4824.761707 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 4855.330442 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 116.015324 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 13.024529 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.846573 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.073620 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.074086 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.001770 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.000199 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.996249 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst 902302 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 773944 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 86739 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 31910 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1794895 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 820354 # number of Writeback hits
system.l2c.Writeback_hits::total 820354 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 162 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 57 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 219 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 23 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 21 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 44 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 172408 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 12341 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 184749 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst 902302 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 946352 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 86739 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 44251 # number of demand (read+write) hits
system.l2c.demand_hits::total 1979644 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 902302 # number of overall hits
system.l2c.overall_hits::cpu0.data 946352 # number of overall hits
system.l2c.overall_hits::cpu1.inst 86739 # number of overall hits
system.l2c.overall_hits::cpu1.data 44251 # number of overall hits
system.l2c.overall_hits::total 1979644 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 13044 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 271462 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 465 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 325 # number of ReadReq misses
system.l2c.ReadReq_misses::total 285296 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 2436 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 489 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2925 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 35 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 73 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 108 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 113191 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 8669 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 121860 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst 13044 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 384653 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 465 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 8994 # number of demand (read+write) misses
system.l2c.demand_misses::total 407156 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 13044 # number of overall misses
system.l2c.overall_misses::cpu0.data 384653 # number of overall misses
system.l2c.overall_misses::cpu1.inst 465 # number of overall misses
system.l2c.overall_misses::cpu1.data 8994 # number of overall misses
system.l2c.overall_misses::total 407156 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst 678900500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 14120860000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 24120000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 17316000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 14841196500 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 1412000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 1560000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 2972000 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 156000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 208000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 364000 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 5886266000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 450808000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 6337074000 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst 678900500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 20007126000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 24120000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 468124000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 21178270500 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst 678900500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 20007126000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 24120000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 468124000 # number of overall miss cycles
system.l2c.overall_miss_latency::total 21178270500 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst 915346 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 1045406 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 87204 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 32235 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2080191 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 820354 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 820354 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 2598 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 546 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 3144 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 58 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 94 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 152 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 285599 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 21010 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 306609 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 915346 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 1331005 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 87204 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 53245 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2386800 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 915346 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 1331005 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 87204 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 53245 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2386800 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.014250 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.259671 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.005332 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.010082 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.137149 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.937644 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.895604 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.930344 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.603448 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.776596 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.710526 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.396328 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.412613 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.397444 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.014250 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.288994 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.005332 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.168917 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.170587 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.014250 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.288994 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.005332 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.168917 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.170587 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52046.956455 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52017.814648 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51870.967742 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 53280 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52020.345536 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 579.638752 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3190.184049 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 1016.068376 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4457.142857 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2849.315068 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 3370.370370 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.950765 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52002.307071 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52002.904973 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 52046.956455 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52013.440686 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 51870.967742 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 52048.476762 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52015.125652 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 52046.956455 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52013.440686 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 51870.967742 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 52048.476762 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52015.125652 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 79049 # number of writebacks
system.l2c.writebacks::total 79049 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst 13044 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 271462 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 454 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 325 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 285285 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 2436 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 489 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 2925 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 35 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 73 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 108 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 113191 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 8669 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 121860 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 13044 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 384653 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 454 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 8994 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 407145 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 13044 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 384653 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 454 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 8994 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 407145 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 522369000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10863316000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 18183000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 13416000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 11417284000 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 97500000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 19560000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 117060000 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1400000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2920000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 4320000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4527974000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 346780000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 4874754000 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 522369000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 15391290000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 18183000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 360196000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 16292038000 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 522369000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 15391290000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 18183000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 360196000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 16292038000 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1370658000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 19250000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 1389908000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1967340000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 505194000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 2472534000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3337998000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 524444000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 3862442000 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014250 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.259671 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005206 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.010082 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.137144 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.937644 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.895604 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.930344 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.603448 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.776596 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.710526 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.396328 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.412613 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.397444 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014250 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.288994 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005206 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.168917 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.170582 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014250 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.288994 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005206 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.168917 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.170582 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40046.688132 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40017.814648 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40050.660793 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41280 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.624989 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40024.630542 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40020.512821 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.950765 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40002.307071 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.904973 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40046.688132 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.440686 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40050.660793 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40048.476762 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40015.321323 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40046.688132 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.440686 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40050.660793 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40048.476762 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40015.321323 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 41698 # number of replacements
system.iocache.tagsinuse 0.566768 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 41714 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.warmup_cycle 1754521474000 # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide 0.566768 # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide 0.035423 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.035423 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses
system.iocache.ReadReq_misses::total 178 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses
system.iocache.demand_misses::total 41730 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses
system.iocache.overall_misses::total 41730 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 21239998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 21239998 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide 7628774806 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 7628774806 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 7650014804 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 7650014804 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 7650014804 # number of overall miss cycles
system.iocache.overall_miss_latency::total 7650014804 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119325.831461 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 119325.831461 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183595.851126 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 183595.851126 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 183321.706302 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 183321.706302 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 183321.706302 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 183321.706302 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 7551000 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 7072 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 1067.731900 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 41520 # number of writebacks
system.iocache.writebacks::total 41520 # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11983000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 11983000 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5467915000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 5467915000 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 5479898000 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 5479898000 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 5479898000 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 5479898000 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67320.224719 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 67320.224719 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131592.101463 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 131592.101463 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131317.948718 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 131317.948718 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131317.948718 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 131317.948718 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
system.cpu0.dtb.read_hits 8658373 # DTB read hits
system.cpu0.dtb.read_misses 7687 # DTB read misses
system.cpu0.dtb.read_acv 174 # DTB read access violations
system.cpu0.dtb.read_accesses 524201 # DTB read accesses
system.cpu0.dtb.write_hits 6036768 # DTB write hits
system.cpu0.dtb.write_misses 798 # DTB write misses
system.cpu0.dtb.write_acv 115 # DTB write access violations
system.cpu0.dtb.write_accesses 195659 # DTB write accesses
system.cpu0.dtb.data_hits 14695141 # DTB hits
system.cpu0.dtb.data_misses 8485 # DTB misses
system.cpu0.dtb.data_acv 289 # DTB access violations
system.cpu0.dtb.data_accesses 719860 # DTB accesses
system.cpu0.itb.fetch_hits 3948342 # ITB hits
system.cpu0.itb.fetch_misses 3841 # ITB misses
system.cpu0.itb.fetch_acv 143 # ITB acv
system.cpu0.itb.fetch_accesses 3952183 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.numCycles 3924108862 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 54115388 # Number of instructions committed
system.cpu0.committedOps 54115388 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 50086021 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 302769 # Number of float alu accesses
system.cpu0.num_func_calls 1426994 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 6243543 # number of instructions that are conditional controls
system.cpu0.num_int_insts 50086021 # number of integer instructions
system.cpu0.num_fp_insts 302769 # number of float instructions
system.cpu0.num_int_register_reads 68608752 # number of times the integer registers were read
system.cpu0.num_int_register_writes 37121526 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 149232 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 152287 # number of times the floating registers were written
system.cpu0.num_mem_refs 14741011 # number of memory refs
system.cpu0.num_load_insts 8689642 # Number of load instructions
system.cpu0.num_store_insts 6051369 # Number of store instructions
system.cpu0.num_idle_cycles 3676810844.998126 # Number of idle cycles
system.cpu0.num_busy_cycles 247298017.001874 # Number of busy cycles
system.cpu0.not_idle_fraction 0.063020 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.936980 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 6365 # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei 202758 # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0 72603 40.61% 40.61% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 134 0.07% 40.69% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1979 1.11% 41.79% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31 104051 58.20% 100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total 178773 # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0 71234 49.27% 49.27% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 134 0.09% 49.36% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1979 1.37% 50.73% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 71230 49.27% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 144583 # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0 1900684456500 96.87% 96.87% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 103099000 0.01% 96.88% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 795217500 0.04% 96.92% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30 5572000 0.00% 96.92% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 60465248000 3.08% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1962053593000 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.981144 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31 0.684568 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total 0.808752 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 6 2.68% 2.68% # number of syscalls executed
system.cpu0.kern.syscall::3 19 8.48% 11.16% # number of syscalls executed
system.cpu0.kern.syscall::4 3 1.34% 12.50% # number of syscalls executed
system.cpu0.kern.syscall::6 30 13.39% 25.89% # number of syscalls executed
system.cpu0.kern.syscall::12 1 0.45% 26.34% # number of syscalls executed
system.cpu0.kern.syscall::15 1 0.45% 26.79% # number of syscalls executed
system.cpu0.kern.syscall::17 10 4.46% 31.25% # number of syscalls executed
system.cpu0.kern.syscall::19 6 2.68% 33.93% # number of syscalls executed
system.cpu0.kern.syscall::20 4 1.79% 35.71% # number of syscalls executed
system.cpu0.kern.syscall::23 2 0.89% 36.61% # number of syscalls executed
system.cpu0.kern.syscall::24 4 1.79% 38.39% # number of syscalls executed
system.cpu0.kern.syscall::33 8 3.57% 41.96% # number of syscalls executed
system.cpu0.kern.syscall::41 2 0.89% 42.86% # number of syscalls executed
system.cpu0.kern.syscall::45 39 17.41% 60.27% # number of syscalls executed
system.cpu0.kern.syscall::47 4 1.79% 62.05% # number of syscalls executed
system.cpu0.kern.syscall::48 7 3.12% 65.18% # number of syscalls executed
system.cpu0.kern.syscall::54 9 4.02% 69.20% # number of syscalls executed
system.cpu0.kern.syscall::58 1 0.45% 69.64% # number of syscalls executed
system.cpu0.kern.syscall::59 5 2.23% 71.88% # number of syscalls executed
system.cpu0.kern.syscall::71 32 14.29% 86.16% # number of syscalls executed
system.cpu0.kern.syscall::73 3 1.34% 87.50% # number of syscalls executed
system.cpu0.kern.syscall::74 9 4.02% 91.52% # number of syscalls executed
system.cpu0.kern.syscall::87 1 0.45% 91.96% # number of syscalls executed
system.cpu0.kern.syscall::90 2 0.89% 92.86% # number of syscalls executed
system.cpu0.kern.syscall::92 7 3.12% 95.98% # number of syscalls executed
system.cpu0.kern.syscall::97 2 0.89% 96.87% # number of syscalls executed
system.cpu0.kern.syscall::98 2 0.89% 97.77% # number of syscalls executed
system.cpu0.kern.syscall::132 2 0.89% 98.66% # number of syscalls executed
system.cpu0.kern.syscall::144 1 0.45% 99.11% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 224 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir 91 0.05% 0.05% # number of callpals executed
system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed
system.cpu0.kern.callpal::swpctx 3870 2.06% 2.11% # number of callpals executed
system.cpu0.kern.callpal::tbi 44 0.02% 2.13% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed
system.cpu0.kern.callpal::swpipl 171949 91.52% 93.66% # number of callpals executed
system.cpu0.kern.callpal::rdps 6691 3.56% 97.22% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 97.22% # number of callpals executed
system.cpu0.kern.callpal::wrusp 4 0.00% 97.22% # number of callpals executed
system.cpu0.kern.callpal::rdusp 7 0.00% 97.23% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 97.23% # number of callpals executed
system.cpu0.kern.callpal::rti 4706 2.50% 99.73% # number of callpals executed
system.cpu0.kern.callpal::callsys 356 0.19% 99.92% # number of callpals executed
system.cpu0.kern.callpal::imb 149 0.08% 100.00% # number of callpals executed
system.cpu0.kern.callpal::total 187881 # number of callpals executed
system.cpu0.kern.mode_switch::kernel 7232 # number of protection mode switches
system.cpu0.kern.mode_switch::user 1230 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu0.kern.mode_good::kernel 1229
system.cpu0.kern.mode_good::user 1230
system.cpu0.kern.mode_good::idle 0
system.cpu0.kern.mode_switch_good::kernel 0.169939 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total 0.290593 # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel 1958392751000 99.81% 99.81% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 3660835000 0.19% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context 3871 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
system.cpu0.icache.replacements 914730 # number of replacements
system.cpu0.icache.tagsinuse 508.781983 # Cycle average of tags in use
system.cpu0.icache.total_refs 53208794 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 915241 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 58.136375 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 36528993000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 508.781983 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.993715 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.993715 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 53208794 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 53208794 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 53208794 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 53208794 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 53208794 # number of overall hits
system.cpu0.icache.overall_hits::total 53208794 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 915369 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 915369 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 915369 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 915369 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 915369 # number of overall misses
system.cpu0.icache.overall_misses::total 915369 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13645389000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 13645389000 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 13645389000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 13645389000 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 13645389000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 13645389000 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 54124163 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 54124163 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 54124163 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 54124163 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 54124163 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 54124163 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016912 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.016912 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016912 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.016912 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016912 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.016912 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14906.981775 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14906.981775 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14906.981775 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14906.981775 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14906.981775 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14906.981775 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915369 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 915369 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 915369 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 915369 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 915369 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 915369 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10898588000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 10898588000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10898588000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 10898588000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10898588000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 10898588000 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016912 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016912 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016912 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.016912 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016912 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.016912 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11906.223610 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11906.223610 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11906.223610 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11906.223610 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11906.223610 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11906.223610 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 1337806 # number of replacements
system.cpu0.dcache.tagsinuse 506.531092 # Cycle average of tags in use
system.cpu0.dcache.total_refs 13370025 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 1338318 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 9.990170 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 101834000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data 506.531092 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.989319 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.989319 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 7444474 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 7444474 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 5554839 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 5554839 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 175825 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 175825 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191178 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 191178 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 12999313 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 12999313 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 12999313 # number of overall hits
system.cpu0.dcache.overall_hits::total 12999313 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 1037616 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1037616 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 289306 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 289306 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16762 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 16762 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 448 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 448 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 1326922 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1326922 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 1326922 # number of overall misses
system.cpu0.dcache.overall_misses::total 1326922 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 26113316000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 26113316000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8963970000 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 8963970000 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 238512000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 238512000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4951000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 4951000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 35077286000 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 35077286000 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 35077286000 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 35077286000 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 8482090 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 8482090 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5844145 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 5844145 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 192587 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 192587 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 191626 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 191626 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 14326235 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 14326235 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 14326235 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 14326235 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122330 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.122330 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049504 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.049504 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.087036 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.087036 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002338 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002338 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092622 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.092622 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092622 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.092622 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25166.647392 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 25166.647392 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30984.390230 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 30984.390230 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14229.328242 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14229.328242 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11051.339286 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11051.339286 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26435.077570 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 26435.077570 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26435.077570 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 26435.077570 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 785164 # number of writebacks
system.cpu0.dcache.writebacks::total 785164 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1037616 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 1037616 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 289306 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 289306 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16762 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16762 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 448 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 448 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326922 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 1326922 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 1326922 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 1326922 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23000405022 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 23000405022 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8096051001 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8096051001 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 188226000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 188226000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3606001 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3606001 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31096456023 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 31096456023 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31096456023 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 31096456023 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1463096000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1463096000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2089087000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2089087000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3552183000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3552183000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122330 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122330 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049504 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049504 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087036 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087036 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002338 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002338 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092622 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.092622 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092622 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.092622 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22166.586697 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22166.586697 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27984.386777 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27984.386777 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11229.328242 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11229.328242 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8049.109375 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8049.109375 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23435.029356 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23435.029356 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23435.029356 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23435.029356 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
system.cpu1.dtb.read_hits 1027490 # DTB read hits
system.cpu1.dtb.read_misses 2750 # DTB read misses
system.cpu1.dtb.read_acv 36 # DTB read access violations
system.cpu1.dtb.read_accesses 205838 # DTB read accesses
system.cpu1.dtb.write_hits 663174 # DTB write hits
system.cpu1.dtb.write_misses 356 # DTB write misses
system.cpu1.dtb.write_acv 48 # DTB write access violations
system.cpu1.dtb.write_accesses 97040 # DTB write accesses
system.cpu1.dtb.data_hits 1690664 # DTB hits
system.cpu1.dtb.data_misses 3106 # DTB misses
system.cpu1.dtb.data_acv 84 # DTB access violations
system.cpu1.dtb.data_accesses 302878 # DTB accesses
system.cpu1.itb.fetch_hits 1394882 # ITB hits
system.cpu1.itb.fetch_misses 1246 # ITB misses
system.cpu1.itb.fetch_acv 41 # ITB acv
system.cpu1.itb.fetch_accesses 1396128 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.numCycles 3923836450 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 5253430 # Number of instructions committed
system.cpu1.committedOps 5253430 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 4920456 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 25430 # Number of float alu accesses
system.cpu1.num_func_calls 157592 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 506756 # number of instructions that are conditional controls
system.cpu1.num_int_insts 4920456 # number of integer instructions
system.cpu1.num_fp_insts 25430 # number of float instructions
system.cpu1.num_int_register_reads 6826440 # number of times the integer registers were read
system.cpu1.num_int_register_writes 3699681 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 16282 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 16129 # number of times the floating registers were written
system.cpu1.num_mem_refs 1700289 # number of memory refs
system.cpu1.num_load_insts 1033544 # Number of load instructions
system.cpu1.num_store_insts 666745 # Number of store instructions
system.cpu1.num_idle_cycles 3903109824.944130 # Number of idle cycles
system.cpu1.num_busy_cycles 20726625.055870 # Number of busy cycles
system.cpu1.not_idle_fraction 0.005282 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.994718 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 2331 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 35943 # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0 9143 31.85% 31.85% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22 1973 6.87% 38.72% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30 91 0.32% 39.04% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31 17500 60.96% 100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total 28707 # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0 9135 45.13% 45.13% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22 1973 9.75% 54.87% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30 91 0.45% 55.32% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31 9044 44.68% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total 20243 # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0 1920768070500 97.90% 97.90% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22 725778000 0.04% 97.94% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30 67189500 0.00% 97.94% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31 40357157000 2.06% 100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total 1961918195000 # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0 0.999125 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31 0.516800 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total 0.705159 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::2 2 1.96% 1.96% # number of syscalls executed
system.cpu1.kern.syscall::3 11 10.78% 12.75% # number of syscalls executed
system.cpu1.kern.syscall::4 1 0.98% 13.73% # number of syscalls executed
system.cpu1.kern.syscall::6 12 11.76% 25.49% # number of syscalls executed
system.cpu1.kern.syscall::17 5 4.90% 30.39% # number of syscalls executed
system.cpu1.kern.syscall::19 4 3.92% 34.31% # number of syscalls executed
system.cpu1.kern.syscall::20 2 1.96% 36.27% # number of syscalls executed
system.cpu1.kern.syscall::23 2 1.96% 38.24% # number of syscalls executed
system.cpu1.kern.syscall::24 2 1.96% 40.20% # number of syscalls executed
system.cpu1.kern.syscall::33 3 2.94% 43.14% # number of syscalls executed
system.cpu1.kern.syscall::45 15 14.71% 57.84% # number of syscalls executed
system.cpu1.kern.syscall::47 2 1.96% 59.80% # number of syscalls executed
system.cpu1.kern.syscall::48 3 2.94% 62.75% # number of syscalls executed
system.cpu1.kern.syscall::54 1 0.98% 63.73% # number of syscalls executed
system.cpu1.kern.syscall::59 2 1.96% 65.69% # number of syscalls executed
system.cpu1.kern.syscall::71 22 21.57% 87.25% # number of syscalls executed
system.cpu1.kern.syscall::74 7 6.86% 94.12% # number of syscalls executed
system.cpu1.kern.syscall::90 1 0.98% 95.10% # number of syscalls executed
system.cpu1.kern.syscall::92 2 1.96% 97.06% # number of syscalls executed
system.cpu1.kern.syscall::132 2 1.96% 99.02% # number of syscalls executed
system.cpu1.kern.syscall::144 1 0.98% 100.00% # number of syscalls executed
system.cpu1.kern.syscall::total 102 # number of syscalls executed
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed
system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed
system.cpu1.kern.callpal::swpctx 365 1.24% 1.27% # number of callpals executed
system.cpu1.kern.callpal::tbi 10 0.03% 1.31% # number of callpals executed
system.cpu1.kern.callpal::wrent 7 0.02% 1.33% # number of callpals executed
system.cpu1.kern.callpal::swpipl 24055 81.82% 83.15% # number of callpals executed
system.cpu1.kern.callpal::rdps 2165 7.36% 90.51% # number of callpals executed
system.cpu1.kern.callpal::wrkgp 1 0.00% 90.52% # number of callpals executed
system.cpu1.kern.callpal::wrusp 3 0.01% 90.53% # number of callpals executed
system.cpu1.kern.callpal::rdusp 2 0.01% 90.53% # number of callpals executed
system.cpu1.kern.callpal::whami 3 0.01% 90.54% # number of callpals executed
system.cpu1.kern.callpal::rti 2587 8.80% 99.34% # number of callpals executed
system.cpu1.kern.callpal::callsys 161 0.55% 99.89% # number of callpals executed
system.cpu1.kern.callpal::imb 31 0.11% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
system.cpu1.kern.callpal::total 29400 # number of callpals executed
system.cpu1.kern.mode_switch::kernel 879 # number of protection mode switches
system.cpu1.kern.mode_switch::user 516 # number of protection mode switches
system.cpu1.kern.mode_switch::idle 2075 # number of protection mode switches
system.cpu1.kern.mode_good::kernel 532
system.cpu1.kern.mode_good::user 516
system.cpu1.kern.mode_good::idle 16
system.cpu1.kern.mode_switch_good::kernel 0.605233 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle 0.007711 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total 0.306628 # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel 4074736000 0.21% 0.21% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 1594048000 0.08% 0.29% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 1955463610000 99.71% 100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context 366 # number of times the context was actually changed
system.cpu1.icache.replacements 86665 # number of replacements
system.cpu1.icache.tagsinuse 419.761966 # Cycle average of tags in use
system.cpu1.icache.total_refs 5169415 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 87177 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 59.297923 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 1958459766000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst 419.761966 # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst 0.819848 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.819848 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst 5169415 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 5169415 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 5169415 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 5169415 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 5169415 # number of overall hits
system.cpu1.icache.overall_hits::total 5169415 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 87205 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 87205 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 87205 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 87205 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 87205 # number of overall misses
system.cpu1.icache.overall_misses::total 87205 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1314538500 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 1314538500 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 1314538500 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 1314538500 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 1314538500 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 1314538500 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 5256620 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 5256620 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 5256620 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 5256620 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 5256620 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 5256620 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016590 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.016590 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016590 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.016590 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016590 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.016590 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15074.118457 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 15074.118457 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15074.118457 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 15074.118457 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15074.118457 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 15074.118457 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 87205 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 87205 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 87205 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 87205 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 87205 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 87205 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1052891500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 1052891500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1052891500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 1052891500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1052891500 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 1052891500 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016590 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.016590 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.016590 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12073.751505 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12073.751505 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12073.751505 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 12073.751505 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12073.751505 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 12073.751505 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 53525 # number of replacements
system.cpu1.dcache.tagsinuse 416.811918 # Cycle average of tags in use
system.cpu1.dcache.total_refs 1627176 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 53933 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 30.170322 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 1941569697000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data 416.811918 # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data 0.814086 # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total 0.814086 # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data 982724 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 982724 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 626457 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 626457 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 11310 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 11310 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11708 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 11708 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 1609181 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 1609181 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 1609181 # number of overall hits
system.cpu1.dcache.overall_hits::total 1609181 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 35620 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 35620 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 22610 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 22610 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1003 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 1003 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 543 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 543 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 58230 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 58230 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 58230 # number of overall misses
system.cpu1.dcache.overall_misses::total 58230 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 484449000 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 484449000 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 694363000 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 694363000 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 12193000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 12193000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 7082000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 7082000 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 1178812000 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 1178812000 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 1178812000 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 1178812000 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 1018344 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 1018344 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 649067 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 649067 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 12313 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 12313 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 12251 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 12251 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 1667411 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 1667411 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 1667411 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 1667411 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.034978 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.034978 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034835 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.034835 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081459 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.081459 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044323 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044323 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034922 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.034922 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034922 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.034922 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13600.477260 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 13600.477260 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30710.437859 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 30710.437859 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12156.530409 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12156.530409 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13042.357274 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13042.357274 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20244.066632 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 20244.066632 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20244.066632 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 20244.066632 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 35190 # number of writebacks
system.cpu1.dcache.writebacks::total 35190 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 35620 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 35620 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 22610 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 22610 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1003 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1003 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 543 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 543 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 58230 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 58230 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 58230 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 58230 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 377581004 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 377581004 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 626529004 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 626529004 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 9184000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 9184000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5453000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5453000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1004110008 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 1004110008 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1004110008 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 1004110008 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 20565000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 20565000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 534607500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 534607500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 555172500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 555172500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.034978 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.034978 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034835 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034835 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.081459 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.081459 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.044323 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.044323 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034922 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.034922 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034922 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.034922 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10600.252779 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10600.252779 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27710.261123 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27710.261123 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9156.530409 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9156.530409 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10042.357274 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10042.357274 # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17243.860690 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17243.860690 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17243.860690 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17243.860690 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|