path: root/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.962613                       # Number of seconds simulated
sim_ticks                                1962612686500                       # Number of ticks simulated
final_tick                               1962612686500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1118839                       # Simulator instruction rate (inst/s)
host_op_rate                                  1118839                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            36057415911                       # Simulator tick rate (ticks/s)
host_mem_usage                                 319640                       # Number of bytes of host memory used
host_seconds                                    54.43                       # Real time elapsed on the host
sim_insts                                    60898638                       # Number of instructions simulated
sim_ops                                      60898638                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.inst           836288                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         24736704                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst            28736                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           435776                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             26038464                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       836288                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst        28736                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          865024                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7702400                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7702400                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst             13067                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            386511                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst               449                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              6809                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                406851                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          120350                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               120350                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              426110                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            12603966                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               14642                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              222039                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide               489                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                13267245                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         426110                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          14642                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             440751                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3924564                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3924564                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3924564                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             426110                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           12603966                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              14642                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             222039                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide              489                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               17191810                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        406851                       # Number of read requests accepted
system.physmem.writeReqs                       161902                       # Number of write requests accepted
system.physmem.readBursts                      406851                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     161902                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 26031872                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      6592                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8721536                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  26038464                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               10361728                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      103                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                   25609                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           6974                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               25141                       # Per bank write bursts
system.physmem.perBankRdBursts::1               25398                       # Per bank write bursts
system.physmem.perBankRdBursts::2               25524                       # Per bank write bursts
system.physmem.perBankRdBursts::3               24918                       # Per bank write bursts
system.physmem.perBankRdBursts::4               25169                       # Per bank write bursts
system.physmem.perBankRdBursts::5               25258                       # Per bank write bursts
system.physmem.perBankRdBursts::6               25808                       # Per bank write bursts
system.physmem.perBankRdBursts::7               25541                       # Per bank write bursts
system.physmem.perBankRdBursts::8               25675                       # Per bank write bursts
system.physmem.perBankRdBursts::9               25330                       # Per bank write bursts
system.physmem.perBankRdBursts::10              25284                       # Per bank write bursts
system.physmem.perBankRdBursts::11              25615                       # Per bank write bursts
system.physmem.perBankRdBursts::12              25647                       # Per bank write bursts
system.physmem.perBankRdBursts::13              25653                       # Per bank write bursts
system.physmem.perBankRdBursts::14              25754                       # Per bank write bursts
system.physmem.perBankRdBursts::15              25033                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8965                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8625                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8456                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7799                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8065                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8041                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8610                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8172                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8465                       # Per bank write bursts
system.physmem.perBankWrBursts::9                8053                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8222                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8481                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8850                       # Per bank write bursts
system.physmem.perBankWrBursts::13               9510                       # Per bank write bursts
system.physmem.perBankWrBursts::14               9309                       # Per bank write bursts
system.physmem.perBankWrBursts::15               8651                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          56                       # Number of times write queue was full causing retry
system.physmem.totGap                    1962566141500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  406851                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 161902                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    406672                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                        63                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1460                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6003                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5516                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5615                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5716                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5563                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5727                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5534                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     5815                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5644                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     6772                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     6056                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     6547                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     7778                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7034                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6302                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5982                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      734                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1284                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     1530                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     1250                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      943                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1372                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     1883                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     1543                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     1933                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     2085                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     1989                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     2372                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     2742                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     2945                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     2155                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                     1733                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                     1295                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                     1319                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      765                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      520                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      349                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      204                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      223                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      189                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      136                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      113                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      145                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       78                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       76                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       98                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        67633                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      513.852823                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     307.797069                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     417.051196                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          16141     23.87%     23.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        12717     18.80%     42.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5311      7.85%     50.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2897      4.28%     54.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2115      3.13%     57.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1690      2.50%     60.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         2144      3.17%     63.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1403      2.07%     65.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        23215     34.32%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          67633                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          4988                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        81.544306                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     2972.635603                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191           4985     99.94%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            4988                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          4988                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        27.320369                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.529999                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       62.006905                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-31            4741     95.05%     95.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-47              52      1.04%     96.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-63               5      0.10%     96.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-95               6      0.12%     96.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-111              4      0.08%     96.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-143            12      0.24%     96.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-159            26      0.52%     97.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-175            19      0.38%     97.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-191            10      0.20%     97.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-207            13      0.26%     98.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-223             3      0.06%     98.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-239             4      0.08%     98.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-255             2      0.04%     98.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-271             1      0.02%     98.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-287             2      0.04%     98.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-303             5      0.10%     98.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::304-319             5      0.10%     98.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-335            12      0.24%     98.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::336-351            16      0.32%     99.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-367             4      0.08%     99.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::368-383            10      0.20%     99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::384-399             2      0.04%     99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::432-447             1      0.02%     99.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::464-479             4      0.08%     99.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::480-495             2      0.04%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::512-527             2      0.04%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::528-543             2      0.04%     99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::544-559            10      0.20%     99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::560-575             3      0.06%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::576-591             1      0.02%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::672-687             1      0.02%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::688-703             2      0.04%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::704-719             2      0.04%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::720-735             1      0.02%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::736-751             1      0.02%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::816-831             1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::928-943             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            4988                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2137457500                       # Total ticks spent queuing
system.physmem.totMemAccLat                9763982500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2033740000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        5254.99                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  24004.99                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          13.26                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           4.44                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       13.27                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        5.28                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.10                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                     364433                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    110956                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   89.60                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  81.41                       # Row buffer hit rate for writes
system.physmem.avgGap                      3450647.54                       # Average gap between requests
system.physmem.pageHitRate                      87.54                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  253449000                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  138290625                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1581504600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                432429840                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           128188142160                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            66287824245                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1119418910250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1316300550720                       # Total energy per rank (pJ)
system.physmem_0.averagePower              670.688732                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   1862013796212                       # Time in different power states
system.physmem_0.memoryStateTime::REF     65535860000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     35060565038                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  257856480                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  140695500                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1591129800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                450625680                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           128188142160                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            66523575105                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1119212111250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1316364135975                       # Total energy per rank (pJ)
system.physmem_1.averagePower              670.721130                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   1861673236216                       # Time in different power states
system.physmem_1.memoryStateTime::REF     65535860000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     35401125034                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     7492205                       # DTB read hits
system.cpu0.dtb.read_misses                      7443                       # DTB read misses
system.cpu0.dtb.read_acv                          210                       # DTB read access violations
system.cpu0.dtb.read_accesses                  490673                       # DTB read accesses
system.cpu0.dtb.write_hits                    5067323                       # DTB write hits
system.cpu0.dtb.write_misses                      813                       # DTB write misses
system.cpu0.dtb.write_acv                         134                       # DTB write access violations
system.cpu0.dtb.write_accesses                 187452                       # DTB write accesses
system.cpu0.dtb.data_hits                    12559528                       # DTB hits
system.cpu0.dtb.data_misses                      8256                       # DTB misses
system.cpu0.dtb.data_acv                          344                       # DTB access violations
system.cpu0.dtb.data_accesses                  678125                       # DTB accesses
system.cpu0.itb.fetch_hits                    3501951                       # ITB hits
system.cpu0.itb.fetch_misses                     3871                       # ITB misses
system.cpu0.itb.fetch_acv                         184                       # ITB acv
system.cpu0.itb.fetch_accesses                3505822                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                      3923838766                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   47743384                       # Number of instructions committed
system.cpu0.committedOps                     47743384                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             44279734                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                210698                       # Number of float alu accesses
system.cpu0.num_func_calls                    1202353                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      5609016                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    44279734                       # number of integer instructions
system.cpu0.num_fp_insts                       210698                       # number of float instructions
system.cpu0.num_int_register_reads           60867436                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          32999466                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              102334                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             104190                       # number of times the floating registers were written
system.cpu0.num_mem_refs                     12599731                       # number of memory refs
system.cpu0.num_load_insts                    7519361                       # Number of load instructions
system.cpu0.num_store_insts                   5080370                       # Number of store instructions
system.cpu0.num_idle_cycles              3698952400.393103                       # Number of idle cycles
system.cpu0.num_busy_cycles              224886365.606898                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.057313                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.942687                       # Percentage of idle cycles
system.cpu0.Branches                          7198745                       # Number of branches fetched
system.cpu0.op_class::No_OpClass              2727567      5.71%      5.71% # Class of executed instruction
system.cpu0.op_class::IntAlu                 31426598     65.81%     71.52% # Class of executed instruction
system.cpu0.op_class::IntMult                   52886      0.11%     71.63% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     71.63% # Class of executed instruction
system.cpu0.op_class::FloatAdd                  25715      0.05%     71.69% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     71.69% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     71.69% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     71.69% # Class of executed instruction
system.cpu0.op_class::FloatDiv                   1656      0.00%     71.69% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     71.69% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     71.69% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     71.69% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     71.69% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     71.69% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     71.69% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     71.69% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     71.69% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     71.69% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     71.69% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     71.69% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     71.69% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     71.69% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     71.69% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     71.69% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     71.69% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     71.69% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc                 0      0.00%     71.69% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     71.69% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     71.69% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     71.69% # Class of executed instruction
system.cpu0.op_class::MemRead                 7694830     16.11%     87.81% # Class of executed instruction
system.cpu0.op_class::MemWrite                5086464     10.65%     98.46% # Class of executed instruction
system.cpu0.op_class::IprAccess                736268      1.54%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                  47751984                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    6802                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    164994                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   56858     40.19%     40.19% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    131      0.09%     40.28% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1973      1.39%     41.68% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                    421      0.30%     41.97% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                  82092     58.03%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              141475                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    56322     49.08%     49.08% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     131      0.11%     49.20% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1973      1.72%     50.92% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                     421      0.37%     51.28% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   55901     48.72%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               114748                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1900658476000     96.88%     96.88% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               90840500      0.00%     96.88% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              754578500      0.04%     96.92% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30              304090000      0.02%     96.94% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            60111368000      3.06%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1961919353000                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.990573                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.680956                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.811083                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         8      3.60%      3.60% # number of syscalls executed
system.cpu0.kern.syscall::3                        19      8.56%     12.16% # number of syscalls executed
system.cpu0.kern.syscall::4                         4      1.80%     13.96% # number of syscalls executed
system.cpu0.kern.syscall::6                        32     14.41%     28.38% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.45%     28.83% # number of syscalls executed
system.cpu0.kern.syscall::17                        9      4.05%     32.88% # number of syscalls executed
system.cpu0.kern.syscall::19                       10      4.50%     37.39% # number of syscalls executed
system.cpu0.kern.syscall::20                        6      2.70%     40.09% # number of syscalls executed
system.cpu0.kern.syscall::23                        1      0.45%     40.54% # number of syscalls executed
system.cpu0.kern.syscall::24                        3      1.35%     41.89% # number of syscalls executed
system.cpu0.kern.syscall::33                        7      3.15%     45.05% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.90%     45.95% # number of syscalls executed
system.cpu0.kern.syscall::45                       36     16.22%     62.16% # number of syscalls executed
system.cpu0.kern.syscall::47                        3      1.35%     63.51% # number of syscalls executed
system.cpu0.kern.syscall::48                       10      4.50%     68.02% # number of syscalls executed
system.cpu0.kern.syscall::54                       10      4.50%     72.52% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.45%     72.97% # number of syscalls executed
system.cpu0.kern.syscall::59                        6      2.70%     75.68% # number of syscalls executed
system.cpu0.kern.syscall::71                       23     10.36%     86.04% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.35%     87.39% # number of syscalls executed
system.cpu0.kern.syscall::74                        6      2.70%     90.09% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.45%     90.54% # number of syscalls executed
system.cpu0.kern.syscall::90                        3      1.35%     91.89% # number of syscalls executed
system.cpu0.kern.syscall::92                        9      4.05%     95.95% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.90%     96.85% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.90%     97.75% # number of syscalls executed
system.cpu0.kern.syscall::132                       1      0.45%     98.20% # number of syscalls executed
system.cpu0.kern.syscall::144                       2      0.90%     99.10% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.90%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   222                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                  503      0.34%      0.34% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.34% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.34% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.34% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3067      2.05%      2.39% # number of callpals executed
system.cpu0.kern.callpal::tbi                      51      0.03%      2.42% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.42% # number of callpals executed
system.cpu0.kern.callpal::swpipl               134616     89.86%     92.28% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6699      4.47%     96.75% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.75% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     3      0.00%     96.76% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     9      0.01%     96.76% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     96.76% # number of callpals executed
system.cpu0.kern.callpal::rti                    4333      2.89%     99.65% # number of callpals executed
system.cpu0.kern.callpal::callsys                 381      0.25%     99.91% # number of callpals executed
system.cpu0.kern.callpal::imb                     136      0.09%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                149812                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             6888                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1282                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1282                      
system.cpu0.kern.mode_good::user                 1282                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch_good::kernel     0.186121                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.313831                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1958151397500     99.82%     99.82% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          3535867500      0.18%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3068                       # number of times the context was actually changed
system.cpu0.dcache.tags.replacements          1180939                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          505.262035                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           11368359                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          1181356                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs             9.623144                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        112435250                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.262035                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.986840                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.986840                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          417                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          372                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3           45                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.814453                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         51471280                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        51471280                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      6411907                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        6411907                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      4659091                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       4659091                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       140391                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       140391                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       148074                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       148074                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     11070998                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        11070998                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     11070998                       # number of overall hits
system.cpu0.dcache.overall_hits::total       11070998                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       938638                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       938638                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       251661                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       251661                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13662                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        13662                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         5430                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         5430                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1190299                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1190299                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1190299                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1190299                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  29060390999                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  29060390999                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  10906402435                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  10906402435                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    150333500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    150333500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     48525392                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     48525392                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  39966793434                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  39966793434                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  39966793434                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  39966793434                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      7350545                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      7350545                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      4910752                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      4910752                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       154053                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       154053                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       153504                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       153504                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     12261297                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     12261297                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     12261297                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     12261297                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.127696                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.127696                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.051247                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.051247                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.088684                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.088684                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.035374                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.035374                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.097078                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.097078                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.097078                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.097078                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30960.168882                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 30960.168882                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43337.674232                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 43337.674232                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11003.769580                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11003.769580                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  8936.536280                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  8936.536280                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33577.104101                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 33577.104101                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33577.104101                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 33577.104101                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       679102                       # number of writebacks
system.cpu0.dcache.writebacks::total           679102                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       938638                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       938638                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       251661                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       251661                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        13662                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        13662                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         5430                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         5430                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      1190299                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      1190299                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      1190299                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      1190299                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data         7110                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total         7110                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        10834                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        10834                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        17944                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        17944                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  27526583001                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  27526583001                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  10476952065                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  10476952065                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    129828500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    129828500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     40378608                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     40378608                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  38003535066                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  38003535066                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  38003535066                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  38003535066                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1474416000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1474416000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2293892500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2293892500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3768308500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3768308500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.127696                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.127696                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.051247                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.051247                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.088684                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.088684                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.035374                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.035374                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.097078                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.097078                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.097078                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.097078                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29326.090571                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29326.090571                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41631.210497                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41631.210497                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  9502.891231                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  9502.891231                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  7436.207735                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  7436.207735                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31927.721578                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31927.721578                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31927.721578                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31927.721578                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 207372.151899                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 207372.151899                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 211730.893483                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 211730.893483                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 210003.817432                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 210003.817432                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements           698758                       # number of replacements
system.cpu0.icache.tags.tagsinuse          508.155937                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           47052596                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           699270                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            67.288166                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      42435665250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   508.155937                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.992492                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.992492                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          356                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3          156                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         48451372                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        48451372                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     47052596                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       47052596                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     47052596                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        47052596                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     47052596                       # number of overall hits
system.cpu0.icache.overall_hits::total       47052596                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       699388                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       699388                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       699388                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        699388                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       699388                       # number of overall misses
system.cpu0.icache.overall_misses::total       699388                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10012837997                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  10012837997                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  10012837997                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  10012837997                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  10012837997                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  10012837997                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     47751984                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     47751984                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     47751984                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     47751984                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     47751984                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     47751984                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014646                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.014646                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014646                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.014646                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014646                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.014646                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14316.571055                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14316.571055                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14316.571055                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14316.571055                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14316.571055                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14316.571055                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       699388                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       699388                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       699388                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       699388                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       699388                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       699388                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   8958710003                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   8958710003                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   8958710003                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   8958710003                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   8958710003                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   8958710003                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014646                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014646                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014646                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.014646                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014646                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.014646                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12809.356184                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12809.356184                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12809.356184                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12809.356184                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12809.356184                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12809.356184                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     2419579                       # DTB read hits
system.cpu1.dtb.read_misses                      2992                       # DTB read misses
system.cpu1.dtb.read_acv                            0                       # DTB read access violations
system.cpu1.dtb.read_accesses                  239363                       # DTB read accesses
system.cpu1.dtb.write_hits                    1757217                       # DTB write hits
system.cpu1.dtb.write_misses                      341                       # DTB write misses
system.cpu1.dtb.write_acv                          29                       # DTB write access violations
system.cpu1.dtb.write_accesses                 105247                       # DTB write accesses
system.cpu1.dtb.data_hits                     4176796                       # DTB hits
system.cpu1.dtb.data_misses                      3333                       # DTB misses
system.cpu1.dtb.data_acv                           29                       # DTB access violations
system.cpu1.dtb.data_accesses                  344610                       # DTB accesses
system.cpu1.itb.fetch_hits                    1964101                       # ITB hits
system.cpu1.itb.fetch_misses                     1216                       # ITB misses
system.cpu1.itb.fetch_acv                           0                       # ITB acv
system.cpu1.itb.fetch_accesses                1965317                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                      3925225373                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   13155254                       # Number of instructions committed
system.cpu1.committedOps                     13155254                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             12132982                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                173111                       # Number of float alu accesses
system.cpu1.num_func_calls                     411301                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      1304865                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    12132982                       # number of integer instructions
system.cpu1.num_fp_insts                       173111                       # number of float instructions
system.cpu1.num_int_register_reads           16703630                       # number of times the integer registers were read
system.cpu1.num_int_register_writes           8903954                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads               90570                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes              92446                       # number of times the floating registers were written
system.cpu1.num_mem_refs                      4200357                       # number of memory refs
system.cpu1.num_load_insts                    2433886                       # Number of load instructions
system.cpu1.num_store_insts                   1766471                       # Number of store instructions
system.cpu1.num_idle_cycles              3876126901.998025                       # Number of idle cycles
system.cpu1.num_busy_cycles              49098471.001975                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.012508                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.987492                       # Percentage of idle cycles
system.cpu1.Branches                          1871330                       # Number of branches fetched
system.cpu1.op_class::No_OpClass               704516      5.35%      5.35% # Class of executed instruction
system.cpu1.op_class::IntAlu                  7779367     59.12%     64.47% # Class of executed instruction
system.cpu1.op_class::IntMult                   21509      0.16%     64.64% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     64.64% # Class of executed instruction
system.cpu1.op_class::FloatAdd                  14171      0.11%     64.75% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     64.75% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     64.75% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     64.75% # Class of executed instruction
system.cpu1.op_class::FloatDiv                   1986      0.02%     64.76% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     64.76% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     64.76% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     64.76% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     64.76% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     64.76% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     64.76% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     64.76% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     64.76% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     64.76% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     64.76% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     64.76% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     64.76% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     64.76% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     64.76% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     64.76% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     64.76% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     64.76% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc                 0      0.00%     64.76% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     64.76% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     64.76% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     64.76% # Class of executed instruction
system.cpu1.op_class::MemRead                 2505658     19.04%     83.80% # Class of executed instruction
system.cpu1.op_class::MemWrite                1767460     13.43%     97.23% # Class of executed instruction
system.cpu1.op_class::IprAccess                363949      2.77%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  13158616                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2740                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                     78523                       # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0                   26526     38.34%     38.34% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1967      2.84%     41.19% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                    503      0.73%     41.91% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  40183     58.09%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               69179                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                    25685     48.16%     48.16% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1967      3.69%     51.84% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                     503      0.94%     52.79% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                   25182     47.21%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                53337                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1909492808500     97.29%     97.29% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              698045000      0.04%     97.33% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30              344048000      0.02%     97.35% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            52077063000      2.65%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1962611964500                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.968295                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.626683                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total             0.771000                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3                        11     10.58%     10.58% # number of syscalls executed
system.cpu1.kern.syscall::6                        10      9.62%     20.19% # number of syscalls executed
system.cpu1.kern.syscall::15                        1      0.96%     21.15% # number of syscalls executed
system.cpu1.kern.syscall::17                        6      5.77%     26.92% # number of syscalls executed
system.cpu1.kern.syscall::23                        3      2.88%     29.81% # number of syscalls executed
system.cpu1.kern.syscall::24                        3      2.88%     32.69% # number of syscalls executed
system.cpu1.kern.syscall::33                        4      3.85%     36.54% # number of syscalls executed
system.cpu1.kern.syscall::45                       18     17.31%     53.85% # number of syscalls executed
system.cpu1.kern.syscall::47                        3      2.88%     56.73% # number of syscalls executed
system.cpu1.kern.syscall::59                        1      0.96%     57.69% # number of syscalls executed
system.cpu1.kern.syscall::71                       31     29.81%     87.50% # number of syscalls executed
system.cpu1.kern.syscall::74                       10      9.62%     97.12% # number of syscalls executed
system.cpu1.kern.syscall::132                       3      2.88%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                   104                       # number of syscalls executed
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                  421      0.59%      0.59% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.59% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.59% # number of callpals executed
system.cpu1.kern.callpal::swpctx                 1997      2.79%      3.39% # number of callpals executed
system.cpu1.kern.callpal::tbi                       3      0.00%      3.39% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.01%      3.40% # number of callpals executed
system.cpu1.kern.callpal::swpipl                62934     88.05%     91.45% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2145      3.00%     94.46% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.46% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     4      0.01%     94.46% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.00%     94.47% # number of callpals executed
system.cpu1.kern.callpal::rti                    3774      5.28%     99.75% # number of callpals executed
system.cpu1.kern.callpal::callsys                 136      0.19%     99.94% # number of callpals executed
system.cpu1.kern.callpal::imb                      44      0.06%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 71473                       # number of callpals executed
system.cpu1.kern.mode_switch::kernel             2064                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                463                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2877                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                890                      
system.cpu1.kern.mode_good::user                  463                      
system.cpu1.kern.mode_good::idle                  427                      
system.cpu1.kern.mode_switch_good::kernel     0.431202                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.148418                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     0.329386                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel       17700699500      0.90%      0.90% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user          1706728000      0.09%      0.99% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1943204535000     99.01%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                    1998                       # number of times the context was actually changed
system.cpu1.dcache.tags.replacements           166165                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          485.164459                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            4008469                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           166677                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            24.049323                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle      79256927000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   485.164459                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.947587                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.947587                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0          193                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          254                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           65                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         16941101                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        16941101                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      2255044                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        2255044                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      1640007                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       1640007                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        48683                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        48683                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        50718                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        50718                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      3895051                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         3895051                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      3895051                       # number of overall hits
system.cpu1.dcache.overall_hits::total        3895051                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       118164                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       118164                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data        62534                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total        62534                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         8914                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         8914                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data         5850                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total         5850                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       180698                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        180698                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       180698                       # number of overall misses
system.cpu1.dcache.overall_misses::total       180698                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1427964750                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   1427964750                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   1264688999                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   1264688999                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     81193500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total     81193500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     50099897                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     50099897                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   2692653749                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   2692653749                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   2692653749                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   2692653749                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      2373208                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      2373208                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      1702541                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      1702541                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        57597                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        57597                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        56568                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        56568                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      4075749                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      4075749                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      4075749                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      4075749                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.049791                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.049791                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.036730                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.036730                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.154765                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.154765                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.103415                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.103415                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.044335                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.044335                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.044335                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.044335                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12084.600640                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12084.600640                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20224.022116                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 20224.022116                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9108.537133                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9108.537133                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  8564.084957                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  8564.084957                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14901.403164                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 14901.403164                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14901.403164                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 14901.403164                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       114146                       # number of writebacks
system.cpu1.dcache.writebacks::total           114146                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       118164                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       118164                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        62534                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        62534                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         8914                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         8914                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         5850                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total         5850                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       180698                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       180698                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       180698                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       180698                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data           89                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total           89                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         3218                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         3218                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         3307                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total         3307                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1250643250                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1250643250                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1167915001                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1167915001                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     67822500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     67822500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     41323103                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     41323103                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   2418558251                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   2418558251                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   2418558251                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   2418558251                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     18866000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     18866000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    716370000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    716370000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    735236000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    735236000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.049791                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.049791                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036730                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.036730                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.154765                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.154765                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.103415                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.103415                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.044335                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.044335                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.044335                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.044335                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10583.961697                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10583.961697                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18676.480011                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18676.480011                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7608.537133                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7608.537133                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  7063.778291                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  7063.778291                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13384.532485                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13384.532485                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13384.532485                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13384.532485                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 211977.528090                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 211977.528090                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 222613.424487                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 222613.424487                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 222327.184760                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 222327.184760                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements           315648                       # number of replacements
system.cpu1.icache.tags.tagsinuse          445.931523                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           12842415                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           316160                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            40.619987                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     1961765828000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   445.931523                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.870960                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.870960                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1            3                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          444                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3           13                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         13474819                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        13474819                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst     12842415                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       12842415                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     12842415                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        12842415                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     12842415                       # number of overall hits
system.cpu1.icache.overall_hits::total       12842415                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       316202                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       316202                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       316202                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        316202                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       316202                       # number of overall misses
system.cpu1.icache.overall_misses::total       316202                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4145253739                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   4145253739                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   4145253739                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   4145253739                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   4145253739                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   4145253739                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     13158617                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     13158617                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     13158617                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     13158617                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     13158617                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     13158617                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024030                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.024030                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024030                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.024030                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024030                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.024030                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13109.511448                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13109.511448                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13109.511448                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13109.511448                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13109.511448                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13109.511448                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       316202                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       316202                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       316202                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       316202                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       316202                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       316202                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3670775261                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   3670775261                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3670775261                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   3670775261                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3670775261                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   3670775261                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.024030                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.024030                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.024030                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.024030                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.024030                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.024030                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11608.956493                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11608.956493                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11608.956493                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11608.956493                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11608.956493                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11608.956493                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.iobus.trans_dist::ReadReq                 7373                       # Transaction distribution
system.iobus.trans_dist::ReadResp                7373                       # Transaction distribution
system.iobus.trans_dist::WriteReq               55604                       # Transaction distribution
system.iobus.trans_dist::WriteResp              14052                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        13892                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          480                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18148                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2474                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        42502                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83452                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        83452                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  125954                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        55568                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1920                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9074                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9876                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total        81834                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661616                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total      2661616                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2743450                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             13247000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               359000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            13505000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy             2453000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy               76000                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer29.occupancy           242106937                       # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            28450000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            42027500                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                41694                       # number of replacements
system.iocache.tags.tagsinuse                0.567924                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41710                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1756483552000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     0.567924                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.035495                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.035495                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               375534                       # Number of tag accesses
system.iocache.tags.data_accesses              375534                       # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide          174                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::tsunami.ide        41552                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total        41552                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::tsunami.ide          174                       # number of demand (read+write) misses
system.iocache.demand_misses::total               174                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide          174                       # number of overall misses
system.iocache.overall_misses::total              174                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21822883                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21822883                       # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide   8775454554                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total   8775454554                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide     21822883                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     21822883                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide     21822883                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     21822883                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          174                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide          174                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             174                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide          174                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            174                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125418.867816                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 125418.867816                       # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211192.109983                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 211192.109983                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 125418.867816                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 125418.867816                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 125418.867816                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 125418.867816                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         72753                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 9972                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     7.295728                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41520                       # number of writebacks
system.iocache.writebacks::total                41520                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          174                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          174                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        41552                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        41552                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide          174                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          174                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide          174                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          174                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12615883                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     12615883                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide   6614750554                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   6614750554                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide     12615883                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     12615883                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide     12615883                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     12615883                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72505.074713                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 72505.074713                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159192.109983                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159192.109983                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72505.074713                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 72505.074713                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72505.074713                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 72505.074713                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   341367                       # number of replacements
system.l2c.tags.tagsinuse                65207.739779                       # Cycle average of tags in use
system.l2c.tags.total_refs                    2440642                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   406370                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     6.005960                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               9165125750                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   55183.814884                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4854.166492                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     5017.337774                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      113.675354                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data       38.745274                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.842038                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.074069                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.076558                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.001735                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.000591                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.994991                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024        65003                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          185                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1         1104                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         5014                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         6093                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        52607                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.991867                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 25960355                       # Number of tag accesses
system.l2c.tags.data_accesses                25960355                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.inst             686297                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             664438                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             315744                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             108706                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1775185                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          793248                       # number of Writeback hits
system.l2c.Writeback_hits::total               793248                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data             183                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             524                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 707                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            36                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            24                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                60                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           126541                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            47234                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               173775                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst              686297                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              790979                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              315744                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              155940                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1948960                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst             686297                       # number of overall hits
system.l2c.overall_hits::cpu0.data             790979                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             315744                       # number of overall hits
system.l2c.overall_hits::cpu1.data             155940                       # number of overall hits
system.l2c.overall_hits::total                1948960                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst            13070                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           271636                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst              457                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data              234                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               285397                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          2949                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1736                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              4685                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          892                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          897                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1789                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         115627                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           6589                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             122216                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst             13070                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            387263                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst               457                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              6823                       # number of demand (read+write) misses
system.l2c.demand_misses::total                407613                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst            13070                       # number of overall misses
system.l2c.overall_misses::cpu0.data           387263                       # number of overall misses
system.l2c.overall_misses::cpu1.inst              457                       # number of overall misses
system.l2c.overall_misses::cpu1.data             6823                       # number of overall misses
system.l2c.overall_misses::total               407613                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst   1052716500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data  19700886500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst     37366250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data     18492250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    20809461500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      1635455                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     13268077                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     14903532                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1334957                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       185994                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      1520951                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   8793301011                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    540094736                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   9333395747                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1052716500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  28494187511                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst     37366250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    558586986                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     30142857247                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1052716500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  28494187511                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst     37366250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    558586986                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    30142857247                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst         699367                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         936074                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         316201                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         108940                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2060582                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       793248                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           793248                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         3132                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         2260                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            5392                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          928                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          921                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1849                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       242168                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        53823                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           295991                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst          699367                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1178242                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          316201                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          162763                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2356573                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         699367                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1178242                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         316201                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         162763                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2356573                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.018688                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.290186                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.001445                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.002148                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.138503                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.941571                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.768142                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.868880                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.961207                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.973941                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.967550                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.477466                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.122420                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.412904                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.018688                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.328679                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.001445                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.041920                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.172969                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.018688                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.328679                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.001445                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.041920                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.172969                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80544.491201                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 72526.787686                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81764.223195                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 79026.709402                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 72914.086343                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   554.579518                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  7642.901498                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  3181.116756                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1496.588565                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   207.351171                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total   850.168250                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76048.855466                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81969.151009                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 76368.034848                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 80544.491201                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 73578.388617                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 81764.223195                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 81868.237725                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 73949.695537                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 80544.491201                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 73578.388617                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 81764.223195                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 81868.237725                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 73949.695537                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               78830                       # number of writebacks
system.l2c.writebacks::total                    78830                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             3                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             8                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                11                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              8                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 11                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             8                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                11                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst        13067                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data       271636                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst          449                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data          234                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          285386                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         2949                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1736                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         4685                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          892                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          897                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1789                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       115627                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         6589                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        122216                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        13067                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       387263                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst          449                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         6823                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           407602                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        13067                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       387263                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst          449                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         6823                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          407602                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.data         7110                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data           89                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total         7199                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        10834                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         3218                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        14052                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        17944                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data         3307                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        21251                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    888765750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data  16305067500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     31138500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data     15561750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  17240533500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     51864446                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     30663235                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     82527681                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     15769892                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     15706897                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     31476789                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   7347146989                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    457723764                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   7804870753                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    888765750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  23652214489                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst     31138500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    473285514                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  25045404253                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    888765750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  23652214489                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst     31138500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    473285514                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  25045404253                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1374876000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     17620000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   1392496000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2153050500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    674536000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   2827586500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3527926500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    692156000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   4220082500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.018684                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.290186                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.001420                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.002148                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.138498                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.941571                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.768142                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.868880                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.961207                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.973941                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.967550                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.477466                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.122420                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.412904                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.018684                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.328679                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.001420                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.041920                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.172964                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.018684                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.328679                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.001420                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.041920                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.172964                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68016.051886                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60025.429251                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69350.779510                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66503.205128                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 60411.279811                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17587.129875                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17663.153802                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17615.300107                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17679.251121                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17510.476031                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17594.627725                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 63541.793777                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69467.865230                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 63861.284554                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68016.051886                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61075.327333                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69350.779510                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69366.189946                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 61445.734449                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68016.051886                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61075.327333                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69350.779510                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69366.189946                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 61445.734449                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193372.151899                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 197977.528090                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 193429.087373                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 198730.893483                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 209613.424487                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 201223.064332                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 196607.584708                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 209300.272150                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 198582.772575                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              292759                       # Transaction distribution
system.membus.trans_dist::ReadResp             292759                       # Transaction distribution
system.membus.trans_dist::WriteReq              14052                       # Transaction distribution
system.membus.trans_dist::WriteResp             14052                       # Transaction distribution
system.membus.trans_dist::Writeback            120350                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            16060                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          11220                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            6977                       # Transaction distribution
system.membus.trans_dist::ReadExReq            122543                       # Transaction distribution
system.membus.trans_dist::ReadExResp           121713                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        42502                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       927849                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       970351                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124813                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       124813                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1095164                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        81834                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31082624                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     31164458                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      5317568                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      5317568                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                36482026                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                            21558                       # Total snoops (count)
system.membus.snoop_fanout::samples            618592                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  618592    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              618592                       # Request fanout histogram
system.membus.reqLayer0.occupancy            40208000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy          1232118814                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer1.occupancy         2189522277                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy           42501500                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.trans_dist::ReadReq            2102341                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2102326                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             14052                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            14052                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           793248                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq        41590                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           16264                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         11280                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          27544                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           297931                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          297931                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1398755                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3106837                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       632403                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       482171                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               5620166                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     44759488                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    118936680                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     20236864                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     17747522                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              201680554                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                           98552                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          3276706                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            3.012746                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.112175                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                3234942     98.73%     98.73% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                  41764      1.27%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              3                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              4                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            3276706                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         2417745499                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           238500                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        1051604997                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1901998326                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         474390739                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         282399146                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped

---------- End Simulation Statistics   ----------