path: root/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.961827                       # Number of seconds simulated
sim_ticks                                1961826628500                       # Number of ticks simulated
final_tick                               1961826628500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1248737                       # Simulator instruction rate (inst/s)
host_op_rate                                  1248737                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            40231703865                       # Simulator tick rate (ticks/s)
host_mem_usage                                 312404                       # Number of bytes of host memory used
host_seconds                                    48.76                       # Real time elapsed on the host
sim_insts                                    60892387                       # Number of instructions simulated
sim_ops                                      60892387                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.inst           833152                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         24900864                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst            31872                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           336832                       # Number of bytes read from this memory
system.physmem.bytes_read::total             26103680                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       833152                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst        31872                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          865024                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      5078656                       # Number of bytes written to this memory
system.physmem.bytes_written::tsunami.ide      2659328                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7737984                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst             13018                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            389076                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst               498                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              5263                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                407870                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           79354                       # Number of write requests responded to by this memory
system.physmem.num_writes::tsunami.ide          41552                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               120906                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              424682                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            12692693                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide               489                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               16246                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              171693                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                13305804                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         424682                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          16246                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             440928                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2588738                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::tsunami.ide          1355537                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3944275                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2588738                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             424682                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           12692693                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1356026                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              16246                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             171693                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               17250079                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        407870                       # Number of read requests accepted
system.physmem.writeReqs                       120906                       # Number of write requests accepted
system.physmem.readBursts                      407870                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     120906                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 26092032                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     11648                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7736064                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  26103680                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7737984                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      182                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           6995                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               25277                       # Per bank write bursts
system.physmem.perBankRdBursts::1               25718                       # Per bank write bursts
system.physmem.perBankRdBursts::2               25598                       # Per bank write bursts
system.physmem.perBankRdBursts::3               25075                       # Per bank write bursts
system.physmem.perBankRdBursts::4               25186                       # Per bank write bursts
system.physmem.perBankRdBursts::5               25258                       # Per bank write bursts
system.physmem.perBankRdBursts::6               25824                       # Per bank write bursts
system.physmem.perBankRdBursts::7               25548                       # Per bank write bursts
system.physmem.perBankRdBursts::8               25573                       # Per bank write bursts
system.physmem.perBankRdBursts::9               25196                       # Per bank write bursts
system.physmem.perBankRdBursts::10              25177                       # Per bank write bursts
system.physmem.perBankRdBursts::11              25610                       # Per bank write bursts
system.physmem.perBankRdBursts::12              25669                       # Per bank write bursts
system.physmem.perBankRdBursts::13              25717                       # Per bank write bursts
system.physmem.perBankRdBursts::14              26016                       # Per bank write bursts
system.physmem.perBankRdBursts::15              25246                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7929                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7788                       # Per bank write bursts
system.physmem.perBankWrBursts::2                7545                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7026                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7134                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7133                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7657                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7252                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7395                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7084                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7119                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7401                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7832                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8315                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8567                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7699                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           8                       # Number of times write queue was full causing retry
system.physmem.totGap                    1961819616500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  407870                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 120906                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    407616                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                        59                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1871                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2613                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5895                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6008                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6212                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6964                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7304                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     8598                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8970                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     8975                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8647                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     8791                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7250                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     6804                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     5901                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     5642                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5617                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5600                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      164                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      148                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      141                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      133                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      144                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      133                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      128                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      143                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      134                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      147                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      159                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      149                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      135                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      128                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       81                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       75                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       67                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       68                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       82                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       71                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       61                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       31                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       17                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       19                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        66427                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      509.252202                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     306.095148                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     413.238328                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          15972     24.04%     24.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        12116     18.24%     42.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5140      7.74%     50.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2994      4.51%     54.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         3304      4.97%     59.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1746      2.63%     62.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1491      2.24%     64.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1317      1.98%     66.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        22347     33.64%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          66427                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5433                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        75.036996                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     2192.886898                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-4095           5428     99.91%     99.91% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-8191            1      0.02%     99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-45055            1      0.02%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-61439            1      0.02%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::73728-77823            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::122880-126975            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5433                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5433                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        22.248482                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       19.059784                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       19.984616                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            4773     87.85%     87.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              17      0.31%     88.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              17      0.31%     88.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             237      4.36%     92.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              33      0.61%     93.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39               9      0.17%     93.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43               6      0.11%     93.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               9      0.17%     93.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              24      0.44%     94.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               1      0.02%     94.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67              10      0.18%     94.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               6      0.11%     94.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               3      0.06%     94.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               4      0.07%     94.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              32      0.59%     95.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87              11      0.20%     95.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               3      0.06%     95.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               9      0.17%     95.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99             180      3.31%     99.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             4      0.07%     99.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             1      0.02%     99.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             3      0.06%     99.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             1      0.02%     99.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             4      0.07%     99.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             4      0.07%     99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             5      0.09%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             7      0.13%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147            13      0.24%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             2      0.04%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.02%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             1      0.02%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             1      0.02%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-227             2      0.04%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5433                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2198653000                       # Total ticks spent queuing
system.physmem.totMemAccLat                9842803000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2038440000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        5392.98                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  24142.98                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          13.30                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.94                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       13.31                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.94                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.13                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.10                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        26.12                       # Average write queue length when enqueuing
system.physmem.readRowHits                     365377                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     96760                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   89.62                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  80.03                       # Row buffer hit rate for writes
system.physmem.avgGap                      3710114.71                       # Average gap between requests
system.physmem.pageHitRate                      87.43                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     1840052567250                       # Time in different power states
system.physmem.memoryStateTime::REF       65509600000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       56261656500                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                 248270400                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                 253917720                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                 135465000                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                 138546375                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0               1587175200                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1               1592791200                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0               385326720                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1               397949760                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0          128136777600                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1          128136777600                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0           65365947855                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1           65768853780                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          1119755735250                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          1119402309000                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            1315614698025                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            1315691145435                       # Total energy per rank (pJ)
system.physmem.averagePower::0             670.607978                       # Core power per rank (mW)
system.physmem.averagePower::1             670.646945                       # Core power per rank (mW)
system.membus.trans_dist::ReadReq              292757                       # Transaction distribution
system.membus.trans_dist::ReadResp             292757                       # Transaction distribution
system.membus.trans_dist::WriteReq              14067                       # Transaction distribution
system.membus.trans_dist::WriteResp             14067                       # Transaction distribution
system.membus.trans_dist::Writeback             79354                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            16159                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          11272                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            6995                       # Transaction distribution
system.membus.trans_dist::ReadExReq            123294                       # Transaction distribution
system.membus.trans_dist::ReadExResp           122471                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        42532                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       930313                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       972845                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83293                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        83293                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1056138                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        81954                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31181376                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     31263330                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2660288                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2660288                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                33923618                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                            21418                       # Total snoops (count)
system.membus.snoop_fanout::samples            557197                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  557197    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              557197                       # Request fanout histogram
system.membus.reqLayer0.occupancy            40794500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy          1536995500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer1.occupancy         3833296255                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy           43122000                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                   342092                       # number of replacements
system.l2c.tags.tagsinuse                65220.775537                       # Cycle average of tags in use
system.l2c.tags.total_refs                    2444844                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   407280                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     6.002858                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               8652068750                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   55275.158075                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4808.073812                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     4934.415131                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      159.916198                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data       43.212322                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.843432                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.073365                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.075293                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.002440                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.000659                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.995190                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024        65188                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          115                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          763                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         5265                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         7161                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        51884                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.994690                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 25951455                       # Number of tag accesses
system.l2c.tags.data_accesses                25951455                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.inst             690677                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             668171                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             311497                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             104258                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1774603                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          792816                       # number of Writeback hits
system.l2c.Writeback_hits::total               792816                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data             182                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             541                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 723                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            41                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            23                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                64                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           130531                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            42264                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               172795                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst              690677                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              798702                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              311497                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              146522                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1947398                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst             690677                       # number of overall hits
system.l2c.overall_hits::cpu0.data             798702                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             311497                       # number of overall hits
system.l2c.overall_hits::cpu1.data             146522                       # number of overall hits
system.l2c.overall_hits::total                1947398                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst            13021                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           271630                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst              506                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data              238                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               285395                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          2954                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1743                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              4697                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          889                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          909                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1798                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         117934                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           5037                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             122971                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst             13021                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            389564                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst               506                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              5275                       # number of demand (read+write) misses
system.l2c.demand_misses::total                408366                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst            13021                       # number of overall misses
system.l2c.overall_misses::cpu0.data           389564                       # number of overall misses
system.l2c.overall_misses::cpu1.inst              506                       # number of overall misses
system.l2c.overall_misses::cpu1.data             5275                       # number of overall misses
system.l2c.overall_misses::total               408366                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst    953089000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data  17671814750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst     36961500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data     17116250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    18678981500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      1049955                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      9987069                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     11037024                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       859463                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       161993                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      1021456                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   8143976512                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    374794238                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   8518770750                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst    953089000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  25815791262                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst     36961500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    391910488                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     27197752250                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst    953089000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  25815791262                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst     36961500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    391910488                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    27197752250                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst         703698                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         939801                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         312003                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         104496                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2059998                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       792816                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           792816                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         3136                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         2284                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            5420                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          930                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          932                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1862                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       248465                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        47301                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           295766                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst          703698                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1188266                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          312003                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          151797                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2355764                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         703698                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1188266                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         312003                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         151797                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2355764                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.018504                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.289029                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.001622                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.002278                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.138541                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.941964                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.763135                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.866605                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.955914                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.975322                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.965628                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.474650                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.106488                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.415771                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.018504                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.327842                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.001622                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.034750                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.173348                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.018504                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.327842                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.001622                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.034750                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.173348                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73196.298287                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 65058.405736                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73046.442688                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 71917.016807                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 65449.575150                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   355.435003                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5729.815835                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  2349.802853                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data   966.775028                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   178.210121                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total   568.106785                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69055.374294                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 74408.226722                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 69274.631824                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 73196.298287                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 66268.421266                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 73046.442688                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 74295.827109                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 66601.412091                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 73196.298287                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 66268.421266                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 73046.442688                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 74295.827109                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 66601.412091                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               79354                       # number of writebacks
system.l2c.writebacks::total                    79354                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             3                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             8                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                11                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              8                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 11                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             8                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                11                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst        13018                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data       271630                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst          498                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data          238                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          285384                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         2954                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1743                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         4697                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          889                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          909                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1798                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       117934                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         5037                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        122971                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        13018                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       389564                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst          498                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         5275                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           408355                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        13018                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       389564                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst          498                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         5275                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          408355                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    787294250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data  14275629250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     30082250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data     14147750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  15107153500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     29547954                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     17431743                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     46979697                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      8890889                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      9090909                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     17981798                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   6662795488                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    311210762                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   6974006250                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    787294250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  20938424738                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst     30082250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    325358512                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  22081159750                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    787294250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  20938424738                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst     30082250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    325358512                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  22081159750                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1373183500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     17608500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   1390792000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2147807000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    674603500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   2822410500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3520990500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    692212000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   4213202500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.018499                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.289029                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.001596                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.002278                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.138536                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.941964                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.763135                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.866605                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.955914                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.975322                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.965628                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.474650                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.106488                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.415771                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.018499                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.327842                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.001596                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.034750                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.173343                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.018499                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.327842                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.001596                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.034750                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.173343                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60477.358273                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52555.421897                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60406.124498                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 59444.327731                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 52936.231534                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10002.692620                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.064509                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56495.967982                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61784.943816                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 56712.609070                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60477.358273                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53748.356465                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60406.124498                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61679.338768                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 54073.440389                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60477.358273                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53748.356465                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60406.124498                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61679.338768                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 54073.440389                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.tags.replacements                41694                       # number of replacements
system.iocache.tags.tagsinuse                0.569739                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41710                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1755504878000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     0.569739                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.035609                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.035609                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               375534                       # Number of tag accesses
system.iocache.tags.data_accesses              375534                       # Number of data accesses
system.iocache.WriteInvalidateReq_hits::tsunami.ide        41552                       # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total        41552                       # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::tsunami.ide          174                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
system.iocache.demand_misses::tsunami.ide          174                       # number of demand (read+write) misses
system.iocache.demand_misses::total               174                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide          174                       # number of overall misses
system.iocache.overall_misses::total              174                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21248383                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21248383                       # number of ReadReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide     21248383                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     21248383                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide     21248383                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     21248383                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          174                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide          174                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             174                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide          174                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            174                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122117.143678                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 122117.143678                       # average ReadReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 122117.143678                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 122117.143678                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 122117.143678                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 122117.143678                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                      41552                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_misses::tsunami.ide          174                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          174                       # number of ReadReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide          174                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          174                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide          174                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          174                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12199383                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     12199383                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide   2501404806                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2501404806                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide     12199383                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     12199383                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide     12199383                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     12199383                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70111.396552                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70111.396552                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide          inf                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70111.396552                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70111.396552                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70111.396552                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 70111.396552                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     7562596                       # DTB read hits
system.cpu0.dtb.read_misses                      7765                       # DTB read misses
system.cpu0.dtb.read_acv                          210                       # DTB read access violations
system.cpu0.dtb.read_accesses                  524069                       # DTB read accesses
system.cpu0.dtb.write_hits                    5147185                       # DTB write hits
system.cpu0.dtb.write_misses                      910                       # DTB write misses
system.cpu0.dtb.write_acv                         133                       # DTB write access violations
system.cpu0.dtb.write_accesses                 202595                       # DTB write accesses
system.cpu0.dtb.data_hits                    12709781                       # DTB hits
system.cpu0.dtb.data_misses                      8675                       # DTB misses
system.cpu0.dtb.data_acv                          343                       # DTB access violations
system.cpu0.dtb.data_accesses                  726664                       # DTB accesses
system.cpu0.itb.fetch_hits                    3660706                       # ITB hits
system.cpu0.itb.fetch_misses                     3984                       # ITB misses
system.cpu0.itb.fetch_acv                         184                       # ITB acv
system.cpu0.itb.fetch_accesses                3664690                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                      3923653257                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   48127777                       # Number of instructions committed
system.cpu0.committedOps                     48127777                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             44643925                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                213512                       # Number of float alu accesses
system.cpu0.num_func_calls                    1209739                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      5647172                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    44643925                       # number of integer instructions
system.cpu0.num_fp_insts                       213512                       # number of float instructions
system.cpu0.num_int_register_reads           61387452                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          33242964                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              104337                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             106136                       # number of times the floating registers were written
system.cpu0.num_mem_refs                     12750882                       # number of memory refs
system.cpu0.num_load_insts                    7590433                       # Number of load instructions
system.cpu0.num_store_insts                   5160449                       # Number of store instructions
system.cpu0.num_idle_cycles              3699495012.998114                       # Number of idle cycles
system.cpu0.num_busy_cycles              224158244.001886                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.057130                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.942870                       # Percentage of idle cycles
system.cpu0.Branches                          7246936                       # Number of branches fetched
system.cpu0.op_class::No_OpClass              2741568      5.70%      5.70% # Class of executed instruction
system.cpu0.op_class::IntAlu                 31634980     65.72%     71.41% # Class of executed instruction
system.cpu0.op_class::IntMult                   52525      0.11%     71.52% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     71.52% # Class of executed instruction
system.cpu0.op_class::FloatAdd                  26830      0.06%     71.58% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     71.58% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     71.58% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     71.58% # Class of executed instruction
system.cpu0.op_class::FloatDiv                   1883      0.00%     71.58% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     71.58% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     71.58% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     71.58% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     71.58% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     71.58% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     71.58% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     71.58% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     71.58% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     71.58% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     71.58% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     71.58% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     71.58% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     71.58% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     71.58% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     71.58% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     71.58% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     71.58% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc                 0      0.00%     71.58% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     71.58% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     71.58% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     71.58% # Class of executed instruction
system.cpu0.op_class::MemRead                 7767201     16.14%     87.72% # Class of executed instruction
system.cpu0.op_class::MemWrite                5166567     10.73%     98.45% # Class of executed instruction
system.cpu0.op_class::IprAccess                745241      1.55%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                  48136795                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    6805                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    166328                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   57239     40.25%     40.25% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    131      0.09%     40.34% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1975      1.39%     41.73% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                    424      0.30%     42.03% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                  82449     57.97%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              142218                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    56706     49.09%     49.09% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     131      0.11%     49.20% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1975      1.71%     50.91% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                     424      0.37%     51.28% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   56283     48.72%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               115519                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1902225794500     96.96%     96.96% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               94977500      0.00%     96.97% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              767421000      0.04%     97.01% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30              314336500      0.02%     97.02% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            58423341500      2.98%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1961825871000                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.990688                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.682640                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.812267                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         8      3.42%      3.42% # number of syscalls executed
system.cpu0.kern.syscall::3                        20      8.55%     11.97% # number of syscalls executed
system.cpu0.kern.syscall::4                         4      1.71%     13.68% # number of syscalls executed
system.cpu0.kern.syscall::6                        33     14.10%     27.78% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.43%     28.21% # number of syscalls executed
system.cpu0.kern.syscall::17                       10      4.27%     32.48% # number of syscalls executed
system.cpu0.kern.syscall::19                       10      4.27%     36.75% # number of syscalls executed
system.cpu0.kern.syscall::20                        6      2.56%     39.32% # number of syscalls executed
system.cpu0.kern.syscall::23                        1      0.43%     39.74% # number of syscalls executed
system.cpu0.kern.syscall::24                        3      1.28%     41.03% # number of syscalls executed
system.cpu0.kern.syscall::33                        8      3.42%     44.44% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.85%     45.30% # number of syscalls executed
system.cpu0.kern.syscall::45                       39     16.67%     61.97% # number of syscalls executed
system.cpu0.kern.syscall::47                        3      1.28%     63.25% # number of syscalls executed
system.cpu0.kern.syscall::48                       10      4.27%     67.52% # number of syscalls executed
system.cpu0.kern.syscall::54                       10      4.27%     71.79% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.43%     72.22% # number of syscalls executed
system.cpu0.kern.syscall::59                        6      2.56%     74.79% # number of syscalls executed
system.cpu0.kern.syscall::71                       27     11.54%     86.32% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.28%     87.61% # number of syscalls executed
system.cpu0.kern.syscall::74                        7      2.99%     90.60% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.43%     91.03% # number of syscalls executed
system.cpu0.kern.syscall::90                        3      1.28%     92.31% # number of syscalls executed
system.cpu0.kern.syscall::92                        9      3.85%     96.15% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.85%     97.01% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.85%     97.86% # number of syscalls executed
system.cpu0.kern.syscall::132                       1      0.43%     98.29% # number of syscalls executed
system.cpu0.kern.syscall::144                       2      0.85%     99.15% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.85%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   234                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                  506      0.34%      0.34% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.34% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.34% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.34% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3105      2.06%      2.40% # number of callpals executed
system.cpu0.kern.callpal::tbi                      51      0.03%      2.43% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.44% # number of callpals executed
system.cpu0.kern.callpal::swpipl               135265     89.81%     92.25% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6701      4.45%     96.70% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.70% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     4      0.00%     96.70% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     9      0.01%     96.71% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     96.71% # number of callpals executed
system.cpu0.kern.callpal::rti                    4423      2.94%     99.65% # number of callpals executed
system.cpu0.kern.callpal::callsys                 394      0.26%     99.91% # number of callpals executed
system.cpu0.kern.callpal::imb                     139      0.09%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                150611                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             7020                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1371                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1370                      
system.cpu0.kern.mode_good::user                 1371                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch_good::kernel     0.195157                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.326660                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1958053140500     99.81%     99.81% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          3772726000      0.19%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3106                       # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq            2102030                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2102015                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             14067                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            14067                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           792816                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq        41560                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           16382                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         11336                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          27718                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           297616                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          297616                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1407417                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3134555                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       624007                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       452565                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               5618544                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     45036672                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    120042720                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     19968192                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     16553666                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              201601250                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                           98838                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          3254541                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            3.012823                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.112512                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                3212807     98.72%     98.72% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                  41734      1.28%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              3                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              4                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            3254541                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         4795402363                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           715500                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        3169257997                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        5536514081                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.3                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy        1404115991                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         776560164                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                 7373                       # Transaction distribution
system.iobus.trans_dist::ReadResp                7373                       # Transaction distribution
system.iobus.trans_dist::WriteReq               55619                       # Transaction distribution
system.iobus.trans_dist::WriteResp              55619                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        13922                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          480                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18148                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2474                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        42532                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83452                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        83452                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  125984                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        55688                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1920                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9074                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9876                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total        81954                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661616                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total      2661616                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2743570                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             13277000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               359000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            13505000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy             2453000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy               76000                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer29.occupancy           374410189                       # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            28465000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            42017000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.cpu0.icache.tags.replacements           703089                       # number of replacements
system.cpu0.icache.tags.tagsinuse          508.385515                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           47433077                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           703601                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            67.414738                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      40276505250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   508.385515                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.992940                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.992940                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          444                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3           13                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         48840515                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        48840515                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     47433077                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       47433077                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     47433077                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        47433077                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     47433077                       # number of overall hits
system.cpu0.icache.overall_hits::total       47433077                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       703719                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       703719                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       703719                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        703719                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       703719                       # number of overall misses
system.cpu0.icache.overall_misses::total       703719                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10017635497                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  10017635497                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  10017635497                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  10017635497                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  10017635497                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  10017635497                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     48136796                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     48136796                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     48136796                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     48136796                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     48136796                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     48136796                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014619                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.014619                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014619                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.014619                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014619                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.014619                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14235.277855                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14235.277855                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14235.277855                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14235.277855                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14235.277855                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14235.277855                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       703719                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       703719                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       703719                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       703719                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       703719                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       703719                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   8605152503                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   8605152503                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   8605152503                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   8605152503                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   8605152503                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   8605152503                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014619                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014619                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014619                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.014619                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014619                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.014619                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12228.108809                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12228.108809                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12228.108809                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12228.108809                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12228.108809                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12228.108809                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements          1191194                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          505.224955                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           11513307                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          1191706                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs             9.661197                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        108210250                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.224955                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.986767                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.986767                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          123                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          320                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         52084143                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        52084143                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      6477469                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        6477469                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      4731394                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       4731394                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       141563                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       141563                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       149256                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       149256                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     11208863                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        11208863                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     11208863                       # number of overall hits
system.cpu0.dcache.overall_hits::total       11208863                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       942620                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       942620                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       258040                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       258040                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13696                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        13696                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         5452                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         5452                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1200660                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1200660                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1200660                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1200660                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  27232981250                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  27232981250                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  10355566942                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  10355566942                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    149859500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    149859500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     42011389                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     42011389                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  37588548192                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  37588548192                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  37588548192                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  37588548192                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      7420089                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      7420089                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      4989434                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      4989434                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       155259                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       155259                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       154708                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       154708                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     12409523                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     12409523                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     12409523                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     12409523                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.127036                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.127036                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.051717                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.051717                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.088214                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.088214                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.035241                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.035241                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.096753                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.096753                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.096753                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.096753                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28890.731419                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 28890.731419                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40131.634406                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 40131.634406                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10941.844334                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10941.844334                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7705.683969                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7705.683969                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31306.571546                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 31306.571546                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31306.571546                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 31306.571546                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       686359                       # number of writebacks
system.cpu0.dcache.writebacks::total           686359                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       942620                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       942620                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       258040                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       258040                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        13696                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        13696                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         5452                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         5452                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      1200660                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      1200660                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      1200660                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      1200660                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  25222171750                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  25222171750                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   9786377058                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   9786377058                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    122453500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    122453500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     31105611                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     31105611                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  35008548808                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  35008548808                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  35008548808                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  35008548808                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1465625500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1465625500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2277904000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2277904000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3743529500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3743529500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.127036                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.127036                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.051717                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.051717                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.088214                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.088214                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.035241                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.035241                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.096753                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.096753                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.096753                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.096753                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26757.518141                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26757.518141                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37925.814052                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37925.814052                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  8940.822138                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8940.822138                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  5705.357850                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  5705.357850                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29157.753909                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29157.753909                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29157.753909                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29157.753909                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     2348280                       # DTB read hits
system.cpu1.dtb.read_misses                      2620                       # DTB read misses
system.cpu1.dtb.read_acv                            0                       # DTB read access violations
system.cpu1.dtb.read_accesses                  205337                       # DTB read accesses
system.cpu1.dtb.write_hits                    1676993                       # DTB write hits
system.cpu1.dtb.write_misses                      235                       # DTB write misses
system.cpu1.dtb.write_acv                          24                       # DTB write access violations
system.cpu1.dtb.write_accesses                  89739                       # DTB write accesses
system.cpu1.dtb.data_hits                     4025273                       # DTB hits
system.cpu1.dtb.data_misses                      2855                       # DTB misses
system.cpu1.dtb.data_acv                           24                       # DTB access violations
system.cpu1.dtb.data_accesses                  295076                       # DTB accesses
system.cpu1.itb.fetch_hits                    1801078                       # ITB hits
system.cpu1.itb.fetch_misses                     1064                       # ITB misses
system.cpu1.itb.fetch_acv                           0                       # ITB acv
system.cpu1.itb.fetch_accesses                1802142                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                      3921880878                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   12764610                       # Number of instructions committed
system.cpu1.committedOps                     12764610                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             11762987                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                170364                       # Number of float alu accesses
system.cpu1.num_func_calls                     404048                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      1265459                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    11762987                       # number of integer instructions
system.cpu1.num_fp_insts                       170364                       # number of float instructions
system.cpu1.num_int_register_reads           16177090                       # number of times the integer registers were read
system.cpu1.num_int_register_writes           8656212                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads               88600                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes              90534                       # number of times the floating registers were written
system.cpu1.num_mem_refs                      4047820                       # number of memory refs
system.cpu1.num_load_insts                    2361802                       # Number of load instructions
system.cpu1.num_store_insts                   1686018                       # Number of store instructions
system.cpu1.num_idle_cycles              3873240792.459649                       # Number of idle cycles
system.cpu1.num_busy_cycles              48640085.540351                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.012402                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.987598                       # Percentage of idle cycles
system.cpu1.Branches                          1821460                       # Number of branches fetched
system.cpu1.op_class::No_OpClass               690637      5.41%      5.41% # Class of executed instruction
system.cpu1.op_class::IntAlu                  7566798     59.27%     64.68% # Class of executed instruction
system.cpu1.op_class::IntMult                   21839      0.17%     64.85% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     64.85% # Class of executed instruction
system.cpu1.op_class::FloatAdd                  13058      0.10%     64.95% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     64.95% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     64.95% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     64.95% # Class of executed instruction
system.cpu1.op_class::FloatDiv                   1759      0.01%     64.96% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     64.96% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     64.96% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     64.96% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     64.96% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     64.96% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     64.96% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     64.96% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     64.96% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     64.96% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     64.96% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     64.96% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     64.96% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     64.96% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     64.96% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     64.96% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     64.96% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     64.96% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc                 0      0.00%     64.96% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     64.96% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     64.96% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     64.96% # Class of executed instruction
system.cpu1.op_class::MemRead                 2432293     19.05%     84.01% # Class of executed instruction
system.cpu1.op_class::MemWrite                1686990     13.21%     97.23% # Class of executed instruction
system.cpu1.op_class::IprAccess                354115      2.77%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  12767489                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2740                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                     77083                       # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0                   26133     38.19%     38.19% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1969      2.88%     41.07% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                    506      0.74%     41.81% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  39822     58.19%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               68430                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                    25289     48.13%     48.13% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1969      3.75%     51.87% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                     506      0.96%     52.84% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                   24783     47.16%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                52547                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1909614154000     97.38%     97.38% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              700846000      0.04%     97.42% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30              353816000      0.02%     97.44% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            50271593000      2.56%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1960940409000                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.967704                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.622344                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total             0.767894                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3                        10     10.87%     10.87% # number of syscalls executed
system.cpu1.kern.syscall::6                         9      9.78%     20.65% # number of syscalls executed
system.cpu1.kern.syscall::15                        1      1.09%     21.74% # number of syscalls executed
system.cpu1.kern.syscall::17                        5      5.43%     27.17% # number of syscalls executed
system.cpu1.kern.syscall::23                        3      3.26%     30.43% # number of syscalls executed
system.cpu1.kern.syscall::24                        3      3.26%     33.70% # number of syscalls executed
system.cpu1.kern.syscall::33                        3      3.26%     36.96% # number of syscalls executed
system.cpu1.kern.syscall::45                       15     16.30%     53.26% # number of syscalls executed
system.cpu1.kern.syscall::47                        3      3.26%     56.52% # number of syscalls executed
system.cpu1.kern.syscall::59                        1      1.09%     57.61% # number of syscalls executed
system.cpu1.kern.syscall::71                       27     29.35%     86.96% # number of syscalls executed
system.cpu1.kern.syscall::74                        9      9.78%     96.74% # number of syscalls executed
system.cpu1.kern.syscall::132                       3      3.26%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                    92                       # number of syscalls executed
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                  424      0.60%      0.60% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.60% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.60% # number of callpals executed
system.cpu1.kern.callpal::swpctx                 1955      2.77%      3.37% # number of callpals executed
system.cpu1.kern.callpal::tbi                       3      0.00%      3.38% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.01%      3.39% # number of callpals executed
system.cpu1.kern.callpal::swpipl                62269     88.12%     91.51% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2146      3.04%     94.54% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.54% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     3      0.00%     94.55% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.00%     94.55% # number of callpals executed
system.cpu1.kern.callpal::rti                    3685      5.21%     99.77% # number of callpals executed
system.cpu1.kern.callpal::callsys                 121      0.17%     99.94% # number of callpals executed
system.cpu1.kern.callpal::imb                      42      0.06%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 70663                       # number of callpals executed
system.cpu1.kern.mode_switch::kernel             1918                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                367                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2888                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                797                      
system.cpu1.kern.mode_good::user                  367                      
system.cpu1.kern.mode_good::idle                  430                      
system.cpu1.kern.mode_switch_good::kernel     0.415537                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.148892                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     0.308138                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel       17565031500      0.90%      0.90% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user          1483893000      0.08%      0.97% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1941003590000     99.03%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                    1956                       # number of times the context was actually changed
system.cpu1.icache.tags.replacements           311453                       # number of replacements
system.cpu1.icache.tags.tagsinuse          446.345950                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           12455485                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           311964                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            39.926033                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     1960014862500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   446.345950                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.871769                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.871769                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2           71                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3          440                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         13079493                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        13079493                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst     12455485                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       12455485                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     12455485                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        12455485                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     12455485                       # number of overall hits
system.cpu1.icache.overall_hits::total       12455485                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       312004                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       312004                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       312004                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        312004                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       312004                       # number of overall misses
system.cpu1.icache.overall_misses::total       312004                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4105450991                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   4105450991                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   4105450991                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   4105450991                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   4105450991                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   4105450991                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     12767489                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     12767489                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     12767489                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     12767489                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     12767489                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     12767489                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024437                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.024437                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024437                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.024437                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024437                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.024437                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13158.328070                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13158.328070                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13158.328070                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13158.328070                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13158.328070                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13158.328070                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       312004                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       312004                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       312004                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       312004                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       312004                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       312004                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3481247009                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   3481247009                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3481247009                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   3481247009                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3481247009                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   3481247009                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.024437                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.024437                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.024437                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.024437                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.024437                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.024437                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11157.699930                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11157.699930                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11157.699930                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11157.699930                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11157.699930                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11157.699930                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements           155174                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          486.308424                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            3855056                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           155503                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            24.790879                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     1048852145500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   486.308424                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.949821                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.949821                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          329                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           32                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3          297                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.642578                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         16322131                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        16322131                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      2189503                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        2189503                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      1567525                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       1567525                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        46972                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        46972                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        49481                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        49481                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      3757028                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         3757028                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      3757028                       # number of overall hits
system.cpu1.dcache.overall_hits::total        3757028                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       113756                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       113756                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data        55958                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total        55958                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         8862                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         8862                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data         5884                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total         5884                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       169714                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        169714                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       169714                       # number of overall misses
system.cpu1.dcache.overall_misses::total       169714                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1372027750                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   1372027750                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   1020320505                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   1020320505                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     80442000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total     80442000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     43305909                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     43305909                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   2392348255                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   2392348255                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   2392348255                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   2392348255                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      2303259                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      2303259                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      1623483                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      1623483                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        55834                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        55834                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        55365                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        55365                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      3926742                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      3926742                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      3926742                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      3926742                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.049389                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.049389                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.034468                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.034468                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.158720                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.158720                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.106277                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.106277                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.043220                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.043220                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.043220                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.043220                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12061.146225                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12061.146225                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18233.684281                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 18233.684281                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9077.183480                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9077.183480                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7359.943746                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7359.943746                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14096.351833                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 14096.351833                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14096.351833                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 14096.351833                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       106457                       # number of writebacks
system.cpu1.dcache.writebacks::total           106457                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       113756                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       113756                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        55958                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        55958                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         8862                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         8862                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         5884                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total         5884                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       169714                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       169714                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       169714                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       169714                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1144439250                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1144439250                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data    906162495                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total    906162495                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     62718000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     62718000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     31536091                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     31536091                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   2050601745                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   2050601745                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   2050601745                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   2050601745                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     18765500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     18765500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    713325000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    713325000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    732090500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    732090500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.049389                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.049389                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.034468                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.034468                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.158720                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.158720                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.106277                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.106277                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.043220                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.043220                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.043220                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.043220                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10060.473733                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10060.473733                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16193.618339                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16193.618339                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7077.183480                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7077.183480                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5359.634772                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5359.634772                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12082.690556                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12082.690556                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12082.690556                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12082.690556                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------