path: root/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.982593                       # Number of seconds simulated
sim_ticks                                1982593132000                       # Number of ticks simulated
final_tick                               1982593132000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1109655                       # Simulator instruction rate (inst/s)
host_op_rate                                  1109654                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            36063876778                       # Simulator tick rate (ticks/s)
host_mem_usage                                 333984                       # Number of bytes of host memory used
host_seconds                                    54.97                       # Real time elapsed on the host
sim_insts                                    61002651                       # Number of instructions simulated
sim_ops                                      61002651                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.inst           800256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         24686464                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst            59392                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           523264                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             26070336                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       800256                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst        59392                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          859648                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7739904                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7739904                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst             12504                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            385726                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst               928                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              8176                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                407349                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          120936                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               120936                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              403641                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            12451604                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               29957                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              263929                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide               484                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                13149615                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         403641                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          29957                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             433598                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3903930                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3903930                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3903930                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             403641                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           12451604                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              29957                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             263929                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide              484                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               17053544                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        407349                       # Number of read requests accepted
system.physmem.writeReqs                       120936                       # Number of write requests accepted
system.physmem.readBursts                      407349                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     120936                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 26062656                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7680                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7738112                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  26070336                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7739904                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      120                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               25226                       # Per bank write bursts
system.physmem.perBankRdBursts::1               25379                       # Per bank write bursts
system.physmem.perBankRdBursts::2               25428                       # Per bank write bursts
system.physmem.perBankRdBursts::3               24855                       # Per bank write bursts
system.physmem.perBankRdBursts::4               25157                       # Per bank write bursts
system.physmem.perBankRdBursts::5               25423                       # Per bank write bursts
system.physmem.perBankRdBursts::6               25496                       # Per bank write bursts
system.physmem.perBankRdBursts::7               25345                       # Per bank write bursts
system.physmem.perBankRdBursts::8               25239                       # Per bank write bursts
system.physmem.perBankRdBursts::9               25589                       # Per bank write bursts
system.physmem.perBankRdBursts::10              25733                       # Per bank write bursts
system.physmem.perBankRdBursts::11              25919                       # Per bank write bursts
system.physmem.perBankRdBursts::12              25947                       # Per bank write bursts
system.physmem.perBankRdBursts::13              25572                       # Per bank write bursts
system.physmem.perBankRdBursts::14              25277                       # Per bank write bursts
system.physmem.perBankRdBursts::15              25644                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7850                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7778                       # Per bank write bursts
system.physmem.perBankWrBursts::2                7471                       # Per bank write bursts
system.physmem.perBankWrBursts::3                6886                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7104                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7345                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7430                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7151                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7161                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7315                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7729                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8152                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8256                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7924                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7541                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7815                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          11                       # Number of times write queue was full causing retry
system.physmem.totGap                    1982585764500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  407349                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 120936                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    407149                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                        67                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1879                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3334                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     7458                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6021                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     7046                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6129                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5977                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6491                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7102                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6544                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8528                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     8912                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7538                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8021                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     7097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7359                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6085                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5703                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      205                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      125                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      115                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       87                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      151                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                       93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      117                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      145                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      145                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      174                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      210                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      225                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      127                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      133                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      125                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       80                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       71                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       69                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       66                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       31                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       30                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        67582                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      500.144536                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     302.732498                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     404.890859                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          16271     24.08%     24.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        12393     18.34%     42.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5170      7.65%     50.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3294      4.87%     54.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2518      3.73%     58.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         4277      6.33%     64.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1487      2.20%     67.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         2102      3.11%     70.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        20070     29.70%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          67582                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5413                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        75.229078                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     2867.379606                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191           5410     99.94%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5413                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5413                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        22.336597                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       19.167195                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       20.176387                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23            4808     88.82%     88.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31              29      0.54%     89.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39              21      0.39%     89.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47              46      0.85%     90.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55             212      3.92%     94.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63              15      0.28%     94.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71              14      0.26%     95.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79              26      0.48%     95.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87             189      3.49%     99.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95               5      0.09%     99.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103              5      0.09%     99.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111             4      0.07%     99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135             5      0.09%     99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143             2      0.04%     99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151             4      0.07%     99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159             1      0.02%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167             1      0.02%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175             8      0.15%     99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183             1      0.02%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191             2      0.04%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199             3      0.06%     99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215             8      0.15%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231             2      0.04%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263             2      0.04%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5413                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2790032750                       # Total ticks spent queuing
system.physmem.totMemAccLat               10425576500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2036145000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        6851.26                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  25601.26                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          13.15                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.90                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       13.15                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.90                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.13                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.10                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.37                       # Average write queue length when enqueuing
system.physmem.readRowHits                     363813                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     96742                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   89.34                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  79.99                       # Row buffer hit rate for writes
system.physmem.avgGap                      3752871.58                       # Average gap between requests
system.physmem.pageHitRate                      87.20                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  244006560                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  133138500                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1578010200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                382417200                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           129493107120                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            72939489120                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1125571835250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1330342003950                       # Total energy per rank (pJ)
system.physmem_0.averagePower              671.012251                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   1872206783000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     66203020000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     44179949500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  266913360                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  145637250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1598376000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                401066640                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           129493107120                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            73838725110                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1124783023500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1330526848980                       # Total energy per rank (pJ)
system.physmem_1.averagePower              671.105490                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   1870895185000                       # Time in different power states
system.physmem_1.memoryStateTime::REF     66203020000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     45491533750                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     7416541                       # DTB read hits
system.cpu0.dtb.read_misses                      7442                       # DTB read misses
system.cpu0.dtb.read_acv                          210                       # DTB read access violations
system.cpu0.dtb.read_accesses                  490672                       # DTB read accesses
system.cpu0.dtb.write_hits                    5004457                       # DTB write hits
system.cpu0.dtb.write_misses                      812                       # DTB write misses
system.cpu0.dtb.write_acv                         134                       # DTB write access violations
system.cpu0.dtb.write_accesses                 187451                       # DTB write accesses
system.cpu0.dtb.data_hits                    12420998                       # DTB hits
system.cpu0.dtb.data_misses                      8254                       # DTB misses
system.cpu0.dtb.data_acv                          344                       # DTB access violations
system.cpu0.dtb.data_accesses                  678123                       # DTB accesses
system.cpu0.itb.fetch_hits                    3482402                       # ITB hits
system.cpu0.itb.fetch_misses                     3871                       # ITB misses
system.cpu0.itb.fetch_acv                         184                       # ITB acv
system.cpu0.itb.fetch_accesses                3486273                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                      3964851877                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    6803                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    162801                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   55926     40.12%     40.12% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    133      0.10%     40.21% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1977      1.42%     41.63% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                    435      0.31%     41.94% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                  80941     58.06%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              139412                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    55417     49.07%     49.07% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     133      0.12%     49.18% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1977      1.75%     50.93% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                     435      0.39%     51.32% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   54983     48.68%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               112945                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1904793300500     96.08%     96.08% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               93813000      0.00%     96.09% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              790638500      0.04%     96.13% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30              326474000      0.02%     96.15% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            76421682500      3.85%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1982425908500                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.990899                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.679297                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.810153                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         8      3.60%      3.60% # number of syscalls executed
system.cpu0.kern.syscall::3                        19      8.56%     12.16% # number of syscalls executed
system.cpu0.kern.syscall::4                         4      1.80%     13.96% # number of syscalls executed
system.cpu0.kern.syscall::6                        32     14.41%     28.38% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.45%     28.83% # number of syscalls executed
system.cpu0.kern.syscall::17                        9      4.05%     32.88% # number of syscalls executed
system.cpu0.kern.syscall::19                       10      4.50%     37.39% # number of syscalls executed
system.cpu0.kern.syscall::20                        6      2.70%     40.09% # number of syscalls executed
system.cpu0.kern.syscall::23                        1      0.45%     40.54% # number of syscalls executed
system.cpu0.kern.syscall::24                        3      1.35%     41.89% # number of syscalls executed
system.cpu0.kern.syscall::33                        7      3.15%     45.05% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.90%     45.95% # number of syscalls executed
system.cpu0.kern.syscall::45                       36     16.22%     62.16% # number of syscalls executed
system.cpu0.kern.syscall::47                        3      1.35%     63.51% # number of syscalls executed
system.cpu0.kern.syscall::48                       10      4.50%     68.02% # number of syscalls executed
system.cpu0.kern.syscall::54                       10      4.50%     72.52% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.45%     72.97% # number of syscalls executed
system.cpu0.kern.syscall::59                        6      2.70%     75.68% # number of syscalls executed
system.cpu0.kern.syscall::71                       23     10.36%     86.04% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.35%     87.39% # number of syscalls executed
system.cpu0.kern.syscall::74                        6      2.70%     90.09% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.45%     90.54% # number of syscalls executed
system.cpu0.kern.syscall::90                        3      1.35%     91.89% # number of syscalls executed
system.cpu0.kern.syscall::92                        9      4.05%     95.95% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.90%     96.85% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.90%     97.75% # number of syscalls executed
system.cpu0.kern.syscall::132                       1      0.45%     98.20% # number of syscalls executed
system.cpu0.kern.syscall::144                       2      0.90%     99.10% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.90%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   222                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                  524      0.36%      0.36% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.36% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.36% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.36% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3024      2.05%      2.41% # number of callpals executed
system.cpu0.kern.callpal::tbi                      51      0.03%      2.44% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.45% # number of callpals executed
system.cpu0.kern.callpal::swpipl               132542     89.80%     92.24% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6593      4.47%     96.71% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.71% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     3      0.00%     96.71% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     9      0.01%     96.72% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     96.72% # number of callpals executed
system.cpu0.kern.callpal::rti                    4325      2.93%     99.65% # number of callpals executed
system.cpu0.kern.callpal::callsys                 381      0.26%     99.91% # number of callpals executed
system.cpu0.kern.callpal::imb                     136      0.09%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                147602                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             6863                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1282                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1282                      
system.cpu0.kern.mode_good::user                 1282                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch_good::kernel     0.186799                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.314794                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1977682087000     99.80%     99.80% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          3901070000      0.20%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3025                       # number of times the context was actually changed
system.cpu0.committedInsts                   47316172                       # Number of instructions committed
system.cpu0.committedOps                     47316172                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             43886449                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                206939                       # Number of float alu accesses
system.cpu0.num_func_calls                    1185652                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      5565345                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    43886449                       # number of integer instructions
system.cpu0.num_fp_insts                       206939                       # number of float instructions
system.cpu0.num_int_register_reads           60334275                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          32718467                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              100516                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             102286                       # number of times the floating registers were written
system.cpu0.num_mem_refs                     12460893                       # number of memory refs
system.cpu0.num_load_insts                    7443480                       # Number of load instructions
system.cpu0.num_store_insts                   5017413                       # Number of store instructions
system.cpu0.num_idle_cycles              3699956428.707181                       # Number of idle cycles
system.cpu0.num_busy_cycles              264895448.292820                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.066811                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.933189                       # Percentage of idle cycles
system.cpu0.Branches                          7133641                       # Number of branches fetched
system.cpu0.op_class::No_OpClass              2703037      5.71%      5.71% # Class of executed instruction
system.cpu0.op_class::IntAlu                 31175022     65.87%     71.59% # Class of executed instruction
system.cpu0.op_class::IntMult                   51696      0.11%     71.70% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     71.70% # Class of executed instruction
system.cpu0.op_class::FloatAdd                  25566      0.05%     71.75% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     71.75% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     71.75% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     71.75% # Class of executed instruction
system.cpu0.op_class::FloatDiv                   1656      0.00%     71.75% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     71.75% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     71.75% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     71.75% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     71.75% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     71.75% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     71.75% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     71.75% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     71.75% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     71.75% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     71.75% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     71.75% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     71.75% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     71.75% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     71.75% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     71.75% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     71.75% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     71.75% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc                 0      0.00%     71.75% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     71.75% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     71.75% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     71.75% # Class of executed instruction
system.cpu0.op_class::MemRead                 7616572     16.09%     87.85% # Class of executed instruction
system.cpu0.op_class::MemWrite                5023515     10.61%     98.46% # Class of executed instruction
system.cpu0.op_class::IprAccess                727706      1.54%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                  47324770                       # Class of executed instruction
system.cpu0.dcache.tags.replacements          1172753                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          505.332741                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           11237004                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          1173173                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs             9.578301                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        144706500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.332741                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.986978                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.986978                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          420                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           48                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3          372                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.820312                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         50908772                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        50908772                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      6342827                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        6342827                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      4601104                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       4601104                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       138127                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       138127                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       145435                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       145435                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     10943931                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        10943931                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     10943931                       # number of overall hits
system.cpu0.dcache.overall_hits::total       10943931                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       934208                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       934208                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       249079                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       249079                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13580                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        13580                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         5739                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         5739                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1183287                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1183287                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1183287                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1183287                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  42886334500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  42886334500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  16793569500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  16793569500                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    151760500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    151760500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     94775500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     94775500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  59679904000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  59679904000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  59679904000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  59679904000                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      7277035                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      7277035                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      4850183                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      4850183                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       151707                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       151707                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       151174                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       151174                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     12127218                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     12127218                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     12127218                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     12127218                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.128378                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.128378                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.051355                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.051355                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.089515                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.089515                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.037963                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.037963                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.097573                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.097573                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.097573                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.097573                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 45906.623043                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 45906.623043                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67422.663091                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 67422.663091                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11175.294551                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11175.294551                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16514.288204                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16514.288204                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50435.696496                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 50435.696496                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50435.696496                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 50435.696496                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       672821                       # number of writebacks
system.cpu0.dcache.writebacks::total           672821                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       934208                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       934208                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       249079                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       249079                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        13580                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        13580                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         5739                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         5739                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      1183287                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      1183287                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      1183287                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      1183287                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data         7086                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total         7086                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        10784                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        10784                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        17870                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        17870                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  41952126500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  41952126500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  16544490500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  16544490500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    138180500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    138180500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     89036500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     89036500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  58496617000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  58496617000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  58496617000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  58496617000                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1567540500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1567540500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2452068500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2452068500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   4019609000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4019609000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.128378                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.128378                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.051355                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.051355                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.089515                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.089515                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.037963                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.037963                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.097573                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.097573                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.097573                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.097573                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 44906.623043                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 44906.623043                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 66422.663091                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 66422.663091                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10175.294551                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10175.294551                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15514.288204                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15514.288204                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49435.696496                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 49435.696496                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49435.696496                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49435.696496                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221216.553768                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221216.553768                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227380.239243                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227380.239243                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224936.149972                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224936.149972                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements           686592                       # number of replacements
system.cpu0.icache.tags.tagsinuse          506.490691                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           46637544                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           687104                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            67.875524                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      58998281500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   506.490691                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.989240                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.989240                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           95                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3          417                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         48011996                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        48011996                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     46637544                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       46637544                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     46637544                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        46637544                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     46637544                       # number of overall hits
system.cpu0.icache.overall_hits::total       46637544                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       687226                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       687226                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       687226                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        687226                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       687226                       # number of overall misses
system.cpu0.icache.overall_misses::total       687226                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10626395500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  10626395500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  10626395500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  10626395500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  10626395500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  10626395500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     47324770                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     47324770                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     47324770                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     47324770                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     47324770                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     47324770                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014521                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.014521                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014521                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.014521                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014521                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.014521                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15462.737877                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 15462.737877                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15462.737877                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 15462.737877                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15462.737877                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 15462.737877                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks       686592                       # number of writebacks
system.cpu0.icache.writebacks::total           686592                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       687226                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       687226                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       687226                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       687226                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       687226                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       687226                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   9939169500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   9939169500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   9939169500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   9939169500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   9939169500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   9939169500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014521                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014521                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014521                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.014521                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014521                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.014521                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14462.737877                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14462.737877                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14462.737877                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 14462.737877                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14462.737877                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 14462.737877                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     2511145                       # DTB read hits
system.cpu1.dtb.read_misses                      2993                       # DTB read misses
system.cpu1.dtb.read_acv                            0                       # DTB read access violations
system.cpu1.dtb.read_accesses                  239364                       # DTB read accesses
system.cpu1.dtb.write_hits                    1829996                       # DTB write hits
system.cpu1.dtb.write_misses                      342                       # DTB write misses
system.cpu1.dtb.write_acv                          29                       # DTB write access violations
system.cpu1.dtb.write_accesses                 105248                       # DTB write accesses
system.cpu1.dtb.data_hits                     4341141                       # DTB hits
system.cpu1.dtb.data_misses                      3335                       # DTB misses
system.cpu1.dtb.data_acv                           29                       # DTB access violations
system.cpu1.dtb.data_accesses                  344612                       # DTB accesses
system.cpu1.itb.fetch_hits                    1990273                       # ITB hits
system.cpu1.itb.fetch_misses                     1216                       # ITB misses
system.cpu1.itb.fetch_acv                           0                       # ITB acv
system.cpu1.itb.fetch_accesses                1991489                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                      3965186264                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2869                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                     81047                       # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0                   27546     38.52%     38.52% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1971      2.76%     41.28% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                    524      0.73%     42.01% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  41461     57.99%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               71502                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                    26678     48.22%     48.22% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1971      3.56%     51.78% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                     524      0.95%     52.73% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                   26154     47.27%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                55327                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1912240588500     96.45%     96.45% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              731240000      0.04%     96.49% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30              374509500      0.02%     96.51% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            69246057000      3.49%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1982592395000                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.968489                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.630810                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total             0.773783                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3                        11     10.58%     10.58% # number of syscalls executed
system.cpu1.kern.syscall::6                        10      9.62%     20.19% # number of syscalls executed
system.cpu1.kern.syscall::15                        1      0.96%     21.15% # number of syscalls executed
system.cpu1.kern.syscall::17                        6      5.77%     26.92% # number of syscalls executed
system.cpu1.kern.syscall::23                        3      2.88%     29.81% # number of syscalls executed
system.cpu1.kern.syscall::24                        3      2.88%     32.69% # number of syscalls executed
system.cpu1.kern.syscall::33                        4      3.85%     36.54% # number of syscalls executed
system.cpu1.kern.syscall::45                       18     17.31%     53.85% # number of syscalls executed
system.cpu1.kern.syscall::47                        3      2.88%     56.73% # number of syscalls executed
system.cpu1.kern.syscall::59                        1      0.96%     57.69% # number of syscalls executed
system.cpu1.kern.syscall::71                       31     29.81%     87.50% # number of syscalls executed
system.cpu1.kern.syscall::74                       10      9.62%     97.12% # number of syscalls executed
system.cpu1.kern.syscall::132                       3      2.88%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                   104                       # number of syscalls executed
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                  435      0.59%      0.59% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.59% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.59% # number of callpals executed
system.cpu1.kern.callpal::swpctx                 2066      2.79%      3.39% # number of callpals executed
system.cpu1.kern.callpal::tbi                       3      0.00%      3.39% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.01%      3.40% # number of callpals executed
system.cpu1.kern.callpal::swpipl                65180     88.12%     91.52% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2261      3.06%     94.57% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.57% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     4      0.01%     94.58% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.00%     94.58% # number of callpals executed
system.cpu1.kern.callpal::rti                    3826      5.17%     99.76% # number of callpals executed
system.cpu1.kern.callpal::callsys                 136      0.18%     99.94% # number of callpals executed
system.cpu1.kern.callpal::imb                      44      0.06%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 73970                       # number of callpals executed
system.cpu1.kern.mode_switch::kernel             2115                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                464                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2921                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                912                      
system.cpu1.kern.mode_good::user                  464                      
system.cpu1.kern.mode_good::idle                  448                      
system.cpu1.kern.mode_switch_good::kernel     0.431206                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.153372                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     0.331636                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel       19470103000      0.98%      0.98% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user          1729907500      0.09%      1.07% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1961392382500     98.93%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                    2067                       # number of times the context was actually changed
system.cpu1.committedInsts                   13686479                       # Number of instructions committed
system.cpu1.committedOps                     13686479                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             12624111                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                178612                       # Number of float alu accesses
system.cpu1.num_func_calls                     430158                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      1359705                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    12624111                       # number of integer instructions
system.cpu1.num_fp_insts                       178612                       # number of float instructions
system.cpu1.num_int_register_reads           17383206                       # number of times the integer registers were read
system.cpu1.num_int_register_writes           9260208                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads               93246                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes              95234                       # number of times the floating registers were written
system.cpu1.num_mem_refs                      4365297                       # number of memory refs
system.cpu1.num_load_insts                    2525800                       # Number of load instructions
system.cpu1.num_store_insts                   1839497                       # Number of store instructions
system.cpu1.num_idle_cycles              3912233484.998027                       # Number of idle cycles
system.cpu1.num_busy_cycles              52952779.001973                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.013354                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.986646                       # Percentage of idle cycles
system.cpu1.Branches                          1950120                       # Number of branches fetched
system.cpu1.op_class::No_OpClass               733810      5.36%      5.36% # Class of executed instruction
system.cpu1.op_class::IntAlu                  8101284     59.18%     64.54% # Class of executed instruction
system.cpu1.op_class::IntMult                   23184      0.17%     64.71% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     64.71% # Class of executed instruction
system.cpu1.op_class::FloatAdd                  14372      0.10%     64.81% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     64.81% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     64.81% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     64.81% # Class of executed instruction
system.cpu1.op_class::FloatDiv                   1986      0.01%     64.83% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     64.83% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     64.83% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     64.83% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     64.83% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     64.83% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     64.83% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     64.83% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     64.83% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     64.83% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     64.83% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     64.83% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     64.83% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     64.83% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     64.83% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     64.83% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     64.83% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     64.83% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc                 0      0.00%     64.83% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     64.83% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     64.83% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     64.83% # Class of executed instruction
system.cpu1.op_class::MemRead                 2600475     19.00%     83.82% # Class of executed instruction
system.cpu1.op_class::MemWrite                1840521     13.44%     97.27% # Class of executed instruction
system.cpu1.op_class::IprAccess                374211      2.73%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  13689843                       # Class of executed instruction
system.cpu1.dcache.tags.replacements           173686                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          481.983606                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            4164884                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           174198                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            23.908908                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle      90321767000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   481.983606                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.941374                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.941374                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0          111                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          333                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         17608316                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        17608316                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      2339523                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        2339523                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      1707175                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       1707175                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        50425                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        50425                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        53078                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        53078                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      4046698                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         4046698                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      4046698                       # number of overall hits
system.cpu1.dcache.overall_hits::total        4046698                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       123485                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       123485                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data        65589                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total        65589                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         9256                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         9256                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data         6109                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total         6109                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       189074                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        189074                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       189074                       # number of overall misses
system.cpu1.dcache.overall_misses::total       189074                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1555964500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   1555964500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   1870805000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   1870805000                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     85075000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total     85075000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     96955500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     96955500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   3426769500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   3426769500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   3426769500                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   3426769500                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      2463008                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      2463008                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      1772764                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      1772764                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        59681                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        59681                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        59187                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        59187                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      4235772                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      4235772                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      4235772                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      4235772                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.050136                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.050136                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.036998                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.036998                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.155091                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.155091                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.103215                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.103215                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.044637                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.044637                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.044637                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.044637                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12600.433251                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12600.433251                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28523.151748                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 28523.151748                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9191.335350                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9191.335350                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15870.928139                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15870.928139                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18123.959402                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 18123.959402                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18123.959402                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 18123.959402                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       119736                       # number of writebacks
system.cpu1.dcache.writebacks::total           119736                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       123485                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       123485                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        65589                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        65589                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         9256                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         9256                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         6109                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total         6109                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       189074                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       189074                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       189074                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       189074                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data          118                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total          118                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         3348                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         3348                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         3466                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total         3466                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1432479500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1432479500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1805216000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1805216000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     75819000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     75819000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     90846500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     90846500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   3237695500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   3237695500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   3237695500                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   3237695500                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     25051000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     25051000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    789482000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    789482000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    814533000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    814533000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.050136                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.050136                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036998                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.036998                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.155091                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.155091                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.103215                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.103215                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.044637                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.044637                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.044637                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.044637                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11600.433251                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11600.433251                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27523.151748                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27523.151748                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8191.335350                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8191.335350                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14870.928139                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14870.928139                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17123.959402                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17123.959402                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17123.959402                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17123.959402                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 212296.610169                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 212296.610169                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 235807.048984                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 235807.048984                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 235006.635892                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 235006.635892                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements           331505                       # number of replacements
system.cpu1.icache.tags.tagsinuse          442.932847                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           13357787                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           332017                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            40.232238                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     1975288394500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   442.932847                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.865103                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.865103                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          405                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3           32                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         14021901                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        14021901                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst     13357787                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       13357787                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     13357787                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        13357787                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     13357787                       # number of overall hits
system.cpu1.icache.overall_hits::total       13357787                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       332057                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       332057                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       332057                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        332057                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       332057                       # number of overall misses
system.cpu1.icache.overall_misses::total       332057                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4541544500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   4541544500                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   4541544500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   4541544500                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   4541544500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   4541544500                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     13689844                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     13689844                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     13689844                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     13689844                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     13689844                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     13689844                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024256                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.024256                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024256                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.024256                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024256                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.024256                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13677.002744                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13677.002744                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13677.002744                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13677.002744                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13677.002744                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13677.002744                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.writebacks::writebacks       331505                       # number of writebacks
system.cpu1.icache.writebacks::total           331505                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       332057                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       332057                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       332057                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       332057                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       332057                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       332057                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4209487500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   4209487500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4209487500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   4209487500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4209487500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   4209487500                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.024256                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.024256                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.024256                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.024256                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.024256                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.024256                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12677.002744                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12677.002744                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12677.002744                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 12677.002744                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12677.002744                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 12677.002744                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.iobus.trans_dist::ReadReq                 7379                       # Transaction distribution
system.iobus.trans_dist::ReadResp                7379                       # Transaction distribution
system.iobus.trans_dist::WriteReq               55684                       # Transaction distribution
system.iobus.trans_dist::WriteResp              55684                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        14066                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1006                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18148                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2476                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6674                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        42672                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83454                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        83454                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  126126                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        56264                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2717                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9074                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9884                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4194                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total        82507                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661624                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total      2661624                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2744131                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             15127500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               758000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 9500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                10000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy              175000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            15843000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy             2460000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             6055000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy               83000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           215669663                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            28540000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            41950000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                41695                       # number of replacements
system.iocache.tags.tagsinuse                0.566874                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41711                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1775103309000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     0.566874                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.035430                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.035430                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               375543                       # Number of tag accesses
system.iocache.tags.data_accesses              375543                       # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide          175                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              175                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
system.iocache.demand_misses::tsunami.ide          175                       # number of demand (read+write) misses
system.iocache.demand_misses::total               175                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide          175                       # number of overall misses
system.iocache.overall_misses::total              175                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21956883                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21956883                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::tsunami.ide   5245212780                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   5245212780                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide     21956883                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     21956883                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide     21956883                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     21956883                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          175                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            175                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide          175                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             175                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide          175                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            175                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125467.902857                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 125467.902857                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126232.498556                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 126232.498556                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 125467.902857                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 125467.902857                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 125467.902857                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 125467.902857                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41520                       # number of writebacks
system.iocache.writebacks::total                41520                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          175                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          175                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide          175                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          175                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide          175                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          175                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13206883                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     13206883                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3165805993                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   3165805993                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide     13206883                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     13206883                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide     13206883                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     13206883                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75467.902857                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 75467.902857                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76189.016004                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76189.016004                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75467.902857                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 75467.902857                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75467.902857                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 75467.902857                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   342144                       # number of replacements
system.l2c.tags.tagsinuse                65164.214079                       # Cycle average of tags in use
system.l2c.tags.total_refs                    3686310                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   407150                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     9.053936                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle              12928623000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   54851.914684                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4798.806705                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     5354.570072                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      119.591740                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data       39.330879                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.836974                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.073224                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.081704                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.001825                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.000600                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.994327                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024        65006                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          517                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         5381                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         6294                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        52712                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.991913                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 35907872                       # Number of tag accesses
system.l2c.tags.data_accesses                35907872                       # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks       792557                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          792557                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks       746952                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total          746952                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data             186                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             548                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 734                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            40                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            23                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                63                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           124117                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            48557                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               172674                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst        674696                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst        331117                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total           1005813                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       659477                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       113729                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           773206                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.inst              674696                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              783594                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              331117                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              162286                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1951693                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst             674696                       # number of overall hits
system.l2c.overall_hits::cpu0.data             783594                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             331117                       # number of overall hits
system.l2c.overall_hits::cpu1.data             162286                       # number of overall hits
system.l2c.overall_hits::total                1951693                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data          2972                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1811                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              4783                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          926                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          930                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1856                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         114977                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           7877                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             122854                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst        12504                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst          939                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           13443                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       271537                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data          337                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         271874                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.inst             12504                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            386514                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst               939                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              8214                       # number of demand (read+write) misses
system.l2c.demand_misses::total                408171                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst            12504                       # number of overall misses
system.l2c.overall_misses::cpu0.data           386514                       # number of overall misses
system.l2c.overall_misses::cpu1.inst              939                       # number of overall misses
system.l2c.overall_misses::cpu1.data             8214                       # number of overall misses
system.l2c.overall_misses::total               408171                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data      3619500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     35439500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     39059000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      3369500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       943000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      4312500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  14618391000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   1036807500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  15655198500                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst   1642625500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst    124569500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   1767195000                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  33669095000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data     43269000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  33712364000                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1642625500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  48287486000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    124569500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   1080076500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     51134757500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1642625500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  48287486000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    124569500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   1080076500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    51134757500                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks       792557                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       792557                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks       746952                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total       746952                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         3158                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         2359                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            5517                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          966                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          953                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1919                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       239094                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        56434                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           295528                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst       687200                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst       332056                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total       1019256                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       931014                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       114066                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      1045080                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst          687200                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1170108                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          332056                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          170500                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2359864                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         687200                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1170108                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         332056                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         170500                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2359864                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.941102                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.767698                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.866957                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.958592                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.975866                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.967170                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.480886                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.139579                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.415710                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.018196                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.002828                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.013189                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.291657                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.002954                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.260147                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.018196                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.330323                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.002828                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.048176                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.172964                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.018196                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.330323                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.002828                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.048176                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.172964                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1217.866756                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 19569.022639                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  8166.213673                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  3638.768898                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1013.978495                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  2323.545259                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 127141.871853                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131624.666751                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 127429.294121                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 131368.002239                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 132661.874334                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 131458.379826                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 123994.501670                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 128394.658754                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 123999.955862                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 131368.002239                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 124930.755419                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 132661.874334                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 131492.147553                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 125277.781861                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 131368.002239                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 124930.755419                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 132661.874334                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 131492.147553                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 125277.781861                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               79416                       # number of writebacks
system.l2c.writebacks::total                    79416                       # number of writebacks
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst           11                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total           11                       # number of ReadCleanReq MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             11                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 11                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            11                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                11                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks           10                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total           10                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         2972                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1811                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         4783                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          926                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          930                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1856                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       114977                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         7877                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        122854                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        12504                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst          928                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        13432                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       271537                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data          337                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       271874                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        12504                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       386514                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst          928                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         8214                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           408160                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        12504                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       386514                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst          928                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         8214                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          408160                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.data         7086                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data          118                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total         7204                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        10784                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         3348                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        14132                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        17870                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data         3466                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        21336                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    204336000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    124703500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    329039500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     63412000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     64097500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total    127509500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  13468621000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    958037500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  14426658500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   1517585500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    113934001                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   1631519501                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  30953725000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data     39899000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  30993624000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   1517585500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  44422346000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    113934001                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    997936500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  47051802001                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   1517585500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  44422346000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    113934001                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    997936500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  47051802001                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1478927500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     23575500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   1502503000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2327963000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    750967000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   3078930000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3806890500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    774542500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   4581433000                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.941102                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.767698                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.866957                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.958592                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.975866                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.967170                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.480886                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.139579                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.415710                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.018196                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.002795                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.013178                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.291657                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.002954                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.260147                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.018196                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.330323                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.002795                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.048176                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.172959                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.018196                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.330323                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.002795                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.048176                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.172959                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68753.701211                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68858.917725                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68793.539619                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68479.481641                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68922.043011                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68701.239224                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 117141.871853                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121624.666751                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 117429.294121                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121368.002239                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122773.707974                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121465.120682                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113994.501670                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 118394.658754                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113999.955862                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121368.002239                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114930.755419                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122773.707974                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121492.147553                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 115277.837125                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121368.002239                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114930.755419                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122773.707974                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121492.147553                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 115277.837125                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208711.191081                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 199792.372881                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208565.102721                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215871.939911                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 224303.166069                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 217869.374469                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213032.484611                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 223468.695903                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 214727.830896                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq                7204                       # Transaction distribution
system.membus.trans_dist::ReadResp             292685                       # Transaction distribution
system.membus.trans_dist::WriteReq              14132                       # Transaction distribution
system.membus.trans_dist::WriteResp             14132                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       120936                       # Transaction distribution
system.membus.trans_dist::CleanEvict           262098                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            16894                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          11785                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               3                       # Transaction distribution
system.membus.trans_dist::ReadExReq            123162                       # Transaction distribution
system.membus.trans_dist::ReadExResp           122291                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        285481                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        42672                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1185820                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      1228492                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83437                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        83437                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1311929                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        82507                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31152000                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     31234507                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2658240                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2658240                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                33892747                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                            22774                       # Total snoops (count)
system.membus.snoop_fanout::samples            883255                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  883255    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              883255                       # Request fanout histogram
system.membus.reqLayer0.occupancy            40521000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy          1327609723                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer1.occupancy         2178253250                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy             898617                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoop_filter.tot_requests      4790864                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      2395593                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests       361656                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops           1242                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops         1182                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops           60                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq               7204                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2107176                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             14132                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            14132                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       913504                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean      1018097                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          816785                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           17065                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         11848                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          28913                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           297603                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          297603                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq       1019283                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      1080704                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2061018                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3585479                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       995618                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       558881                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               7200996                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     87922688                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    118013949                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     42467904                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     18601358                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              267005899                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          484765                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          2873241                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.136986                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.344076                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                2479885     86.31%     86.31% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 393120     13.68%     99.99% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                    234      0.01%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                      2      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            2873241                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         4223821996                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           297883                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        1031213250                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1802267282                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         499176813                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         293823888                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped

---------- End Simulation Statistics   ----------