path: root/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.961837                       # Number of seconds simulated
sim_ticks                                1961837389000                       # Number of ticks simulated
final_tick                               1961837389000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1325125                       # Simulator instruction rate (inst/s)
host_op_rate                                  1325124                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            42668778131                       # Simulator tick rate (ticks/s)
host_mem_usage                                 308960                       # Number of bytes of host memory used
host_seconds                                    45.98                       # Real time elapsed on the host
sim_insts                                    60926932                       # Number of instructions simulated
sim_ops                                      60926932                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst           833280                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         24887104                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2650880                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst            31680                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           338432                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28741376                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       833280                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst        31680                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          864960                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7742464                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7742464                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst             13020                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            388861                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41420                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst               495                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              5288                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                449084                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          120976                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               120976                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              424745                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            12685610                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1351223                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               16148                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              172508                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                14650234                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         424745                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          16148                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             440893                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3946537                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3946537                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3946537                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             424745                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           12685610                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1351223                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              16148                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             172508                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               18596771                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        449084                       # Number of read requests accepted
system.physmem.writeReqs                       120976                       # Number of write requests accepted
system.physmem.readBursts                      449084                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     120976                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 28737920                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      3456                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7741568                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  28741376                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7742464                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                       54                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           7077                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               28167                       # Per bank write bursts
system.physmem.perBankRdBursts::1               28458                       # Per bank write bursts
system.physmem.perBankRdBursts::2               28055                       # Per bank write bursts
system.physmem.perBankRdBursts::3               27665                       # Per bank write bursts
system.physmem.perBankRdBursts::4               27762                       # Per bank write bursts
system.physmem.perBankRdBursts::5               27792                       # Per bank write bursts
system.physmem.perBankRdBursts::6               28261                       # Per bank write bursts
system.physmem.perBankRdBursts::7               27879                       # Per bank write bursts
system.physmem.perBankRdBursts::8               28077                       # Per bank write bursts
system.physmem.perBankRdBursts::9               27735                       # Per bank write bursts
system.physmem.perBankRdBursts::10              27671                       # Per bank write bursts
system.physmem.perBankRdBursts::11              28135                       # Per bank write bursts
system.physmem.perBankRdBursts::12              28173                       # Per bank write bursts
system.physmem.perBankRdBursts::13              28505                       # Per bank write bursts
system.physmem.perBankRdBursts::14              28655                       # Per bank write bursts
system.physmem.perBankRdBursts::15              28040                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7931                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7869                       # Per bank write bursts
system.physmem.perBankWrBursts::2                7539                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7157                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7275                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7313                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7748                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7258                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7316                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7114                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7078                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7523                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7676                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8141                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8336                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7688                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          12                       # Number of times write queue was full causing retry
system.physmem.totGap                    1961830378000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  449084                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 120976                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    409885                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     10531                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      5358                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      2695                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      2315                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      2316                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      1356                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1333                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      1333                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1442                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1324                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1276                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1111                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      977                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      963                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      963                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      961                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      960                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      963                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      961                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      4884                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      4909                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      4919                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      5610                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      6333                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      5684                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      5697                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      5791                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      5851                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      5165                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     5161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     5152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     5968                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     6087                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     6069                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     6113                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     6155                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5017                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4975                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4958                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4963                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     4927                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                      216                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                      187                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                       45                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                       25                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                       22                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                       24                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        49252                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      740.628604                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     223.502021                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev    1737.958624                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-67          17638     35.81%     35.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-131         7255     14.73%     50.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-195         4934     10.02%     60.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-259         2938      5.97%     66.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-323         1843      3.74%     70.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-387         1471      2.99%     73.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-451         1137      2.31%     75.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-515          871      1.77%     77.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-579          749      1.52%     78.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-643          678      1.38%     80.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-707          696      1.41%     81.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-771          441      0.90%     82.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-835          346      0.70%     83.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-899          295      0.60%     83.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-963          325      0.66%     84.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1027          366      0.74%     85.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1091          215      0.44%     85.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1155          196      0.40%     86.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1219          200      0.41%     86.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1283          126      0.26%     86.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1347          182      0.37%     87.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1411          862      1.75%     88.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1475          228      0.46%     89.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1539          113      0.23%     89.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1603          126      0.26%     89.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1667          100      0.20%     90.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1731           86      0.17%     90.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1795           47      0.10%     90.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1859           73      0.15%     90.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1923           75      0.15%     90.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1987           79      0.16%     90.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2051           32      0.06%     90.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2115           84      0.17%     90.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2179           62      0.13%     91.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2243           61      0.12%     91.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2307           26      0.05%     91.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2371           60      0.12%     91.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2435           59      0.12%     91.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2499           68      0.14%     91.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2563           29      0.06%     91.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2627           67      0.14%     91.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2691           63      0.13%     91.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2755           57      0.12%     92.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2819           25      0.05%     92.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2883           61      0.12%     92.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2947           59      0.12%     92.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3011           69      0.14%     92.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3075           25      0.05%     92.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3139           65      0.13%     92.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3203           58      0.12%     92.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3267           65      0.13%     92.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3331           25      0.05%     93.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3395           59      0.12%     93.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3459           53      0.11%     93.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3523           71      0.14%     93.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3587           22      0.04%     93.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3651           70      0.14%     93.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3715           53      0.11%     93.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3779           60      0.12%     93.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3843           27      0.05%     93.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3907           61      0.12%     93.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3971           53      0.11%     94.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4035           63      0.13%     94.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4099           34      0.07%     94.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4163           63      0.13%     94.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4227           57      0.12%     94.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4291           62      0.13%     94.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4355           28      0.06%     94.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4419           58      0.12%     94.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4483           54      0.11%     94.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4547           66      0.13%     95.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4611          361      0.73%     95.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4675           57      0.12%     95.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4739           23      0.05%     95.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4803           53      0.11%     96.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4867           23      0.05%     96.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4931           58      0.12%     96.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4995           23      0.05%     96.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5059           51      0.10%     96.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5123           22      0.04%     96.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5187           54      0.11%     96.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5251           39      0.08%     96.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5315           55      0.11%     96.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5379           21      0.04%     96.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5443           55      0.11%     96.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5507           27      0.05%     96.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5571           50      0.10%     97.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5635           22      0.04%     97.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5699           54      0.11%     97.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5763           25      0.05%     97.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5827           53      0.11%     97.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5891           22      0.04%     97.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5955           52      0.11%     97.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6019           23      0.05%     97.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6083           54      0.11%     97.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6147           23      0.05%     97.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6211           52      0.11%     97.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6275           23      0.05%     97.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6339           54      0.11%     97.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6403           23      0.05%     98.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6467           53      0.11%     98.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6531           23      0.05%     98.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6595           55      0.11%     98.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6659           26      0.05%     98.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6723           57      0.12%     98.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6787          421      0.85%     99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6851            1      0.00%     99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7043            1      0.00%     99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7171           12      0.02%     99.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7235            1      0.00%     99.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7363            2      0.00%     99.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7427            1      0.00%     99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7491            1      0.00%     99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7555            1      0.00%     99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7619            1      0.00%     99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7683            2      0.00%     99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7811            2      0.00%     99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7875            1      0.00%     99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7939            1      0.00%     99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8131            2      0.00%     99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8195            6      0.01%     99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8256-8259            1      0.00%     99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8451            1      0.00%     99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8576-8579            1      0.00%     99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8704-8707            2      0.00%     99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8768-8771            1      0.00%     99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8832-8835            1      0.00%     99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8896-8899            1      0.00%     99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-8963            1      0.00%     99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9024-9027            2      0.00%     99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9152-9155            1      0.00%     99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9219            4      0.01%     99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9344-9347            1      0.00%     99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9472-9475            1      0.00%     99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9536-9539            1      0.00%     99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9664-9667            2      0.00%     99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9792-9795            2      0.00%     99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9856-9859            1      0.00%     99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10176-10179            2      0.00%     99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10304-10307            1      0.00%     99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10368-10371            1      0.00%     99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10432-10435            1      0.00%     99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10880-10883            1      0.00%     99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10944-10947            4      0.01%     99.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11072-11075            2      0.00%     99.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11264-11267            1      0.00%     99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11648-11651            1      0.00%     99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11712-11715            2      0.00%     99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11776-11779            2      0.00%     99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11840-11843            1      0.00%     99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11968-11971            1      0.00%     99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12032-12035            2      0.00%     99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12096-12099            1      0.00%     99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12291            3      0.01%     99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12544-12547            1      0.00%     99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12608-12611            1      0.00%     99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12672-12675            2      0.00%     99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13059            3      0.01%     99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13315            1      0.00%     99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13568-13571            1      0.00%     99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13696-13699            4      0.01%     99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14208-14211            4      0.01%     99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14339            1      0.00%     99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14656-14659            2      0.00%     99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14784-14787            1      0.00%     99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14848-14851            1      0.00%     99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14912-14915            1      0.00%     99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14976-14979            2      0.00%     99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15168-15171            2      0.00%     99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15232-15235            1      0.00%     99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15296-15299            2      0.00%     99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15363           40      0.08%     99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15424-15427            2      0.00%     99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15488-15491            1      0.00%     99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15744-15747            1      0.00%     99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15936-15939            1      0.00%     99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16192-16195            1      0.00%     99.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16387          179      0.36%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          49252                       # Bytes accessed per row activation
system.physmem.totQLat                     6314810500                       # Total ticks spent queuing
system.physmem.totMemAccLat               14686644250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2245150000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                  6126683750                       # Total ticks spent accessing banks
system.physmem.avgQLat                       14063.23                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                    13644.26                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  32707.49                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          14.65                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.95                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       14.65                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.95                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         0.01                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        11.09                       # Average write queue length when enqueuing
system.physmem.readRowHits                     424855                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     95885                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   94.62                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  79.26                       # Row buffer hit rate for writes
system.physmem.avgGap                      3441445.42                       # Average gap between requests
system.physmem.pageHitRate                      91.36                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent               0.53                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                     18657286                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              292799                       # Transaction distribution
system.membus.trans_dist::ReadResp             292799                       # Transaction distribution
system.membus.trans_dist::WriteReq              14111                       # Transaction distribution
system.membus.trans_dist::WriteResp             14111                       # Transaction distribution
system.membus.trans_dist::Writeback            120976                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            16467                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          11554                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            7080                       # Transaction distribution
system.membus.trans_dist::ReadExReq            164905                       # Transaction distribution
system.membus.trans_dist::ReadExResp           164053                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        42620                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       930997                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       973617                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124666                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       124666                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1098283                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave        82306                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     31175680                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total     31257986                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5308160                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total      5308160                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            36566146                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               36566146                       # Total data (bytes)
system.membus.snoop_data_through_bus            36416                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy            43190000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy          1566162500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer1.occupancy         3824002662                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy          376301000                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.l2c.tags.replacements                   342163                       # number of replacements
system.l2c.tags.tagsinuse                65223.750612                       # Cycle average of tags in use
system.l2c.tags.total_refs                    2442870                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   407350                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     5.996980                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               8613125750                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   55316.946263                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4805.666179                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     4897.139369                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      159.783438                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data       44.215363                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.844070                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.073329                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.074724                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.002438                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.000675                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.995235                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst             684304                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             664415                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             317640                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             107160                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1773519                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          792069                       # number of Writeback hits
system.l2c.Writeback_hits::total               792069                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data             188                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             543                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 731                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            37                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            22                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                59                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           129070                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            43262                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               172332                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst              684304                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              793485                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              317640                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              150422                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1945851                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst             684304                       # number of overall hits
system.l2c.overall_hits::cpu0.data             793485                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             317640                       # number of overall hits
system.l2c.overall_hits::cpu1.data             150422                       # number of overall hits
system.l2c.overall_hits::total                1945851                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst            13023                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           271669                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst              503                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data              242                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               285437                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          2958                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1767                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              4725                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          919                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          927                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1846                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         117954                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           5056                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             123010                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst             13023                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            389623                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst               503                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              5298                       # number of demand (read+write) misses
system.l2c.demand_misses::total                408447                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst            13023                       # number of overall misses
system.l2c.overall_misses::cpu0.data           389623                       # number of overall misses
system.l2c.overall_misses::cpu1.inst              503                       # number of overall misses
system.l2c.overall_misses::cpu1.data             5298                       # number of overall misses
system.l2c.overall_misses::total               408447                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst    996362741                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data  17553106248                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst     38541500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data     19247750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    18607258239                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      1197458                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     10193060                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     11390518                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       953959                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       139494                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      1093453                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   8253462501                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    385340740                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   8638803241                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst    996362741                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  25806568749                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst     38541500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    404588490                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     27246061480                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst    996362741                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  25806568749                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst     38541500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    404588490                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    27246061480                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst         697327                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         936084                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         318143                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         107402                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2058956                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       792069                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           792069                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         3146                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         2310                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            5456                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          956                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          949                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1905                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       247024                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        48318                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           295342                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst          697327                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1183108                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          318143                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          155720                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2354298                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         697327                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1183108                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         318143                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         155720                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2354298                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.018676                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.290219                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.001581                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.002253                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.138632                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.940242                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.764935                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.866019                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.961297                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.976818                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.969029                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.477500                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.104640                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.416500                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.018676                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.329322                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.001581                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.034023                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.173490                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.018676                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.329322                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.001581                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.034023                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.173490                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76507.927590                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 64612.106085                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76623.260437                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 79536.157025                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 65188.669440                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   404.820149                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5768.568195                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  2410.691640                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1038.040261                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   150.478964                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total   592.336403                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69971.874638                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76214.545095                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 70228.463060                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 76507.927590                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 66234.715992                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 76623.260437                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 76366.268403                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 66706.479617                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 76507.927590                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 66234.715992                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 76623.260437                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 76366.268403                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 66706.479617                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               79456                       # number of writebacks
system.l2c.writebacks::total                    79456                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             3                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             8                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                11                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              8                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 11                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             8                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                11                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst        13020                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data       271669                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst          495                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data          242                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          285426                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         2958                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1767                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         4725                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          919                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          927                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1846                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       117954                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         5056                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        123010                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        13020                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       389623                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst          495                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         5298                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           408436                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        13020                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       389623                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst          495                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         5298                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          408436                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    832352009                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data  14156448252                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     31778000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data     16225250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  15036803511                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     29732955                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     17692267                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     47425222                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      9190919                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      9270927                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     18461846                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   6776581499                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    321158260                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   7097739759                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    832352009                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  20933029751                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst     31778000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    337383510                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  22134543270                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    832352009                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  20933029751                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst     31778000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    337383510                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  22134543270                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1373137500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     17612000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   1390749500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2154547500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    679451000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   2833998500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3527685000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    697063000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   4224748000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.018671                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.290219                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.001556                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.002253                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.138627                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.940242                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.764935                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.866019                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.961297                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.976818                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.969029                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.477500                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.104640                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.416500                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.018671                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.329322                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.001556                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.034023                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.173485                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.018671                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.329322                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.001556                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.034023                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.173485                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63928.725730                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52109.177904                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64197.979798                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67046.487603                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 52681.968395                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10051.708925                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10012.601585                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10037.084021                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57451.052944                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63520.225475                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 57700.510194                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63928.725730                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53726.370751                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64197.979798                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63681.296716                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 54193.418969                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63928.725730                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53726.370751                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64197.979798                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63681.296716                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 54193.418969                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.tags.replacements                41694                       # number of replacements
system.iocache.tags.tagsinuse                0.571330                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41710                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1754532770000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     0.571330                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.035708                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.035708                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide          174                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41726                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41726                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41726                       # number of overall misses
system.iocache.overall_misses::total            41726                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21248383                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21248383                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide  12952701816                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  12952701816                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide  12973950199                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  12973950199                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide  12973950199                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  12973950199                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          174                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41726                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41726                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41726                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41726                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122117.143678                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 122117.143678                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 311722.704467                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 311722.704467                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 310932.037555                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 310932.037555                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 310932.037555                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 310932.037555                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        405757                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                29467                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    13.769878                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41520                       # number of writebacks
system.iocache.writebacks::total                41520                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          174                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          174                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41726                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41726                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41726                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41726                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12199383                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     12199383                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  10790464816                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total  10790464816                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide  10802664199                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total  10802664199                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide  10802664199                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total  10802664199                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70111.396552                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70111.396552                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 259685.810936                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 259685.810936                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 258895.273906                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 258895.273906                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 258895.273906                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 258895.273906                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     7530179                       # DTB read hits
system.cpu0.dtb.read_misses                      7765                       # DTB read misses
system.cpu0.dtb.read_acv                          210                       # DTB read access violations
system.cpu0.dtb.read_accesses                  524069                       # DTB read accesses
system.cpu0.dtb.write_hits                    5118893                       # DTB write hits
system.cpu0.dtb.write_misses                      910                       # DTB write misses
system.cpu0.dtb.write_acv                         133                       # DTB write access violations
system.cpu0.dtb.write_accesses                 202595                       # DTB write accesses
system.cpu0.dtb.data_hits                    12649072                       # DTB hits
system.cpu0.dtb.data_misses                      8675                       # DTB misses
system.cpu0.dtb.data_acv                          343                       # DTB access violations
system.cpu0.dtb.data_accesses                  726664                       # DTB accesses
system.cpu0.itb.fetch_hits                    3650586                       # ITB hits
system.cpu0.itb.fetch_misses                     3984                       # ITB misses
system.cpu0.itb.fetch_acv                         184                       # ITB acv
system.cpu0.itb.fetch_accesses                3654570                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                      3923674778                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   47959136                       # Number of instructions committed
system.cpu0.committedOps                     47959136                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             44491652                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                211334                       # Number of float alu accesses
system.cpu0.num_func_calls                    1203195                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      5632072                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    44491652                       # number of integer instructions
system.cpu0.num_fp_insts                       211334                       # number of float instructions
system.cpu0.num_int_register_reads           61191395                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          33136181                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              103249                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             105046                       # number of times the floating registers were written
system.cpu0.num_mem_refs                     12690027                       # number of memory refs
system.cpu0.num_load_insts                    7557911                       # Number of load instructions
system.cpu0.num_store_insts                   5132116                       # Number of store instructions
system.cpu0.num_idle_cycles              3700191977.998114                       # Number of idle cycles
system.cpu0.num_busy_cycles              223482800.001886                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.056958                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.943042                       # Percentage of idle cycles
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    6812                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    165228                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   56779     40.23%     40.23% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    131      0.09%     40.33% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1974      1.40%     41.72% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                    435      0.31%     42.03% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                  81809     57.97%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              141128                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    56269     49.08%     49.08% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     131      0.11%     49.20% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1974      1.72%     50.92% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                     435      0.38%     51.30% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   55834     48.70%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               114643                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1902446374500     96.97%     96.97% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               95095000      0.00%     96.98% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              766988500      0.04%     97.02% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30              322426000      0.02%     97.03% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            58205747500      2.97%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1961836631500                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.991018                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.682492                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.812333                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         8      3.42%      3.42% # number of syscalls executed
system.cpu0.kern.syscall::3                        20      8.55%     11.97% # number of syscalls executed
system.cpu0.kern.syscall::4                         4      1.71%     13.68% # number of syscalls executed
system.cpu0.kern.syscall::6                        33     14.10%     27.78% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.43%     28.21% # number of syscalls executed
system.cpu0.kern.syscall::17                       10      4.27%     32.48% # number of syscalls executed
system.cpu0.kern.syscall::19                       10      4.27%     36.75% # number of syscalls executed
system.cpu0.kern.syscall::20                        6      2.56%     39.32% # number of syscalls executed
system.cpu0.kern.syscall::23                        1      0.43%     39.74% # number of syscalls executed
system.cpu0.kern.syscall::24                        3      1.28%     41.03% # number of syscalls executed
system.cpu0.kern.syscall::33                        8      3.42%     44.44% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.85%     45.30% # number of syscalls executed
system.cpu0.kern.syscall::45                       39     16.67%     61.97% # number of syscalls executed
system.cpu0.kern.syscall::47                        3      1.28%     63.25% # number of syscalls executed
system.cpu0.kern.syscall::48                       10      4.27%     67.52% # number of syscalls executed
system.cpu0.kern.syscall::54                       10      4.27%     71.79% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.43%     72.22% # number of syscalls executed
system.cpu0.kern.syscall::59                        6      2.56%     74.79% # number of syscalls executed
system.cpu0.kern.syscall::71                       27     11.54%     86.32% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.28%     87.61% # number of syscalls executed
system.cpu0.kern.syscall::74                        7      2.99%     90.60% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.43%     91.03% # number of syscalls executed
system.cpu0.kern.syscall::90                        3      1.28%     92.31% # number of syscalls executed
system.cpu0.kern.syscall::92                        9      3.85%     96.15% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.85%     97.01% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.85%     97.86% # number of syscalls executed
system.cpu0.kern.syscall::132                       1      0.43%     98.29% # number of syscalls executed
system.cpu0.kern.syscall::144                       2      0.85%     99.15% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.85%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   234                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                  517      0.35%      0.35% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.35% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.35% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.35% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3084      2.06%      2.41% # number of callpals executed
system.cpu0.kern.callpal::tbi                      51      0.03%      2.45% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.45% # number of callpals executed
system.cpu0.kern.callpal::swpipl               134176     89.75%     92.20% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6701      4.48%     96.68% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.68% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     4      0.00%     96.69% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     9      0.01%     96.69% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     96.69% # number of callpals executed
system.cpu0.kern.callpal::rti                    4411      2.95%     99.64% # number of callpals executed
system.cpu0.kern.callpal::callsys                 394      0.26%     99.91% # number of callpals executed
system.cpu0.kern.callpal::imb                     139      0.09%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                149500                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             7010                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1373                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1372                      
system.cpu0.kern.mode_good::user                 1373                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch_good::kernel     0.195720                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.327448                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1958037655500     99.81%     99.81% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          3798971500      0.19%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3085                       # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.toL2Bus.throughput                   103908079                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq            2101783                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2101768                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             14111                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            14111                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           792069                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           16689                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         11613                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          28302                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           338794                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          297244                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1394675                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3121086                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       636287                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       464415                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               5616463                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     44628928                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    119461456                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     20361152                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     17008562                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total          201460098                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus             201449794                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus         2400960                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy         4792055385                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           724500                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        3140628756                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        5519397625                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.3                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy        1431747492                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         796288703                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.iobus.throughput                       1398649                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq                 7373                       # Transaction distribution
system.iobus.trans_dist::ReadResp                7373                       # Transaction distribution
system.iobus.trans_dist::WriteReq               55663                       # Transaction distribution
system.iobus.trans_dist::WriteResp              55663                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        14010                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          480                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18148                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2474                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        42620                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83452                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        83452                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  126072                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        56040                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio         1920                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio         9074                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9876                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total        82306                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661616                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      2661616                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total              2743922                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                 2743922                       # Total data (bytes)
system.iobus.reqLayer0.occupancy             13365000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               359000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            13505000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy             2453000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy               76000                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer29.occupancy           377760199                       # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            28509000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            42664000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.cpu0.icache.tags.replacements           696718                       # number of replacements
system.cpu0.icache.tags.tagsinuse          508.401211                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           47270807                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           697230                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            67.798011                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      40083254250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   508.401211                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.992971                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.992971                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst     47270807                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       47270807                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     47270807                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        47270807                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     47270807                       # number of overall hits
system.cpu0.icache.overall_hits::total       47270807                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       697348                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       697348                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       697348                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        697348                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       697348                       # number of overall misses
system.cpu0.icache.overall_misses::total       697348                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   9977651756                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   9977651756                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   9977651756                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   9977651756                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   9977651756                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   9977651756                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     47968155                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     47968155                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     47968155                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     47968155                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     47968155                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     47968155                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014538                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.014538                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014538                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.014538                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014538                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.014538                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14307.995084                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14307.995084                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14307.995084                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14307.995084                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14307.995084                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14307.995084                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       697348                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       697348                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       697348                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       697348                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       697348                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       697348                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   8577830244                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   8577830244                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   8577830244                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   8577830244                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   8577830244                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   8577830244                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014538                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014538                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014538                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.014538                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014538                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.014538                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12300.645078                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12300.645078                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12300.645078                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12300.645078                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12300.645078                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12300.645078                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements          1186136                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          505.274988                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           11457169                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          1186648                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs             9.655070                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        107469250                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.274988                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.986865                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.986865                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      6449366                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        6449366                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      4705451                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       4705451                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       140478                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       140478                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       147984                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       147984                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     11154817                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        11154817                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     11154817                       # number of overall hits
system.cpu0.dcache.overall_hits::total       11154817                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       939343                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       939343                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       256772                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       256772                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13639                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        13639                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         5591                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         5591                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1196115                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1196115                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1196115                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1196115                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  27074316502                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  27074316502                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  10448735954                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  10448735954                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    148878750                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    148878750                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     43336419                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     43336419                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  37523052456                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  37523052456                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  37523052456                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  37523052456                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      7388709                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      7388709                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      4962223                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      4962223                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       154117                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       154117                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       153575                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       153575                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     12350932                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     12350932                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     12350932                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     12350932                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.127132                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.127132                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.051745                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.051745                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.088498                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.088498                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.036406                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.036406                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.096844                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.096844                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.096844                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.096844                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28822.609528                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 28822.609528                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40692.661014                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 40692.661014                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10915.664638                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10915.664638                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7751.103380                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7751.103380                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31370.773258                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 31370.773258                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31370.773258                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 31370.773258                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       682430                       # number of writebacks
system.cpu0.dcache.writebacks::total           682430                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       939343                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       939343                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       256772                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       256772                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        13639                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        13639                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         5590                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         5590                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      1196115                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      1196115                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      1196115                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      1196115                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  25063726498                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  25063726498                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   9880374046                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   9880374046                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    121588250                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    121588250                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     32154581                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     32154581                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  34944100544                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  34944100544                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  34944100544                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  34944100544                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1465575000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1465575000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2284904500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2284904500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3750479500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3750479500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.127132                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.127132                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.051745                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.051745                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.088498                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.088498                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.036399                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.036399                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.096844                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.096844                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.096844                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.096844                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26682.187974                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26682.187974                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38479.172363                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38479.172363                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  8914.748149                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8914.748149                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  5752.161181                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  5752.161181                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29214.666269                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29214.666269                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29214.666269                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29214.666269                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     2385380                       # DTB read hits
system.cpu1.dtb.read_misses                      2620                       # DTB read misses
system.cpu1.dtb.read_acv                            0                       # DTB read access violations
system.cpu1.dtb.read_accesses                  205337                       # DTB read accesses
system.cpu1.dtb.write_hits                    1707840                       # DTB write hits
system.cpu1.dtb.write_misses                      235                       # DTB write misses
system.cpu1.dtb.write_acv                          24                       # DTB write access violations
system.cpu1.dtb.write_accesses                  89739                       # DTB write accesses
system.cpu1.dtb.data_hits                     4093220                       # DTB hits
system.cpu1.dtb.data_misses                      2855                       # DTB misses
system.cpu1.dtb.data_acv                           24                       # DTB access violations
system.cpu1.dtb.data_accesses                  295076                       # DTB accesses
system.cpu1.itb.fetch_hits                    1814538                       # ITB hits
system.cpu1.itb.fetch_misses                     1064                       # ITB misses
system.cpu1.itb.fetch_acv                           0                       # ITB acv
system.cpu1.itb.fetch_accesses                1815602                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                      3921880904                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   12967796                       # Number of instructions committed
system.cpu1.committedOps                     12967796                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             11946960                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                174217                       # Number of float alu accesses
system.cpu1.num_func_calls                     410982                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      1284197                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    11946960                       # number of integer instructions
system.cpu1.num_fp_insts                       174217                       # number of float instructions
system.cpu1.num_int_register_reads           16422187                       # number of times the integer registers were read
system.cpu1.num_int_register_writes           8787604                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads               90513                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes              92474                       # number of times the floating registers were written
system.cpu1.num_mem_refs                      4116157                       # number of memory refs
system.cpu1.num_load_insts                    2399132                       # Number of load instructions
system.cpu1.num_store_insts                   1717025                       # Number of store instructions
system.cpu1.num_idle_cycles              3872385828.119347                       # Number of idle cycles
system.cpu1.num_busy_cycles              49495075.880653                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.012620                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.987380                       # Percentage of idle cycles
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2742                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                     78306                       # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0                   26634     38.27%     38.27% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1969      2.83%     41.10% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                    517      0.74%     41.84% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  40476     58.16%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               69596                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                    25767     48.16%     48.16% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1969      3.68%     51.84% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                     517      0.97%     52.81% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                   25250     47.19%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                53503                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1909643308000     97.38%     97.38% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              700945000      0.04%     97.42% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30              361639500      0.02%     97.44% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            50234529500      2.56%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1960940422000                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.967448                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.623826                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total             0.768765                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3                        10     10.87%     10.87% # number of syscalls executed
system.cpu1.kern.syscall::6                         9      9.78%     20.65% # number of syscalls executed
system.cpu1.kern.syscall::15                        1      1.09%     21.74% # number of syscalls executed
system.cpu1.kern.syscall::17                        5      5.43%     27.17% # number of syscalls executed
system.cpu1.kern.syscall::23                        3      3.26%     30.43% # number of syscalls executed
system.cpu1.kern.syscall::24                        3      3.26%     33.70% # number of syscalls executed
system.cpu1.kern.syscall::33                        3      3.26%     36.96% # number of syscalls executed
system.cpu1.kern.syscall::45                       15     16.30%     53.26% # number of syscalls executed
system.cpu1.kern.syscall::47                        3      3.26%     56.52% # number of syscalls executed
system.cpu1.kern.syscall::59                        1      1.09%     57.61% # number of syscalls executed
system.cpu1.kern.syscall::71                       27     29.35%     86.96% # number of syscalls executed
system.cpu1.kern.syscall::74                        9      9.78%     96.74% # number of syscalls executed
system.cpu1.kern.syscall::132                       3      3.26%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                    92                       # number of syscalls executed
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                  435      0.61%      0.61% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.61% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.61% # number of callpals executed
system.cpu1.kern.callpal::swpctx                 2001      2.78%      3.39% # number of callpals executed
system.cpu1.kern.callpal::tbi                       3      0.00%      3.40% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.01%      3.41% # number of callpals executed
system.cpu1.kern.callpal::swpipl                63390     88.19%     91.60% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2146      2.99%     94.59% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.59% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     3      0.00%     94.59% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.00%     94.60% # number of callpals executed
system.cpu1.kern.callpal::rti                    3719      5.17%     99.77% # number of callpals executed
system.cpu1.kern.callpal::callsys                 121      0.17%     99.94% # number of callpals executed
system.cpu1.kern.callpal::imb                      42      0.06%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 71875                       # number of callpals executed
system.cpu1.kern.mode_switch::kernel             1956                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                368                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2907                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                809                      
system.cpu1.kern.mode_good::user                  368                      
system.cpu1.kern.mode_good::idle                  441                      
system.cpu1.kern.mode_switch_good::kernel     0.413599                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.151703                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     0.309310                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel       17986321500      0.92%      0.92% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user          1483696000      0.08%      0.99% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1940592550000     99.01%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                    2002                       # number of times the context was actually changed
system.cpu1.icache.tags.replacements           317593                       # number of replacements
system.cpu1.icache.tags.tagsinuse          446.454785                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           12652531                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           318104                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            39.774825                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     1959964216000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   446.454785                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.871982                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.871982                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst     12652531                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       12652531                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     12652531                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        12652531                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     12652531                       # number of overall hits
system.cpu1.icache.overall_hits::total       12652531                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       318144                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       318144                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       318144                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        318144                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       318144                       # number of overall misses
system.cpu1.icache.overall_misses::total       318144                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4187615492                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   4187615492                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   4187615492                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   4187615492                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   4187615492                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   4187615492                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     12970675                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     12970675                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     12970675                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     12970675                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     12970675                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     12970675                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024528                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.024528                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024528                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.024528                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024528                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.024528                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13162.641735                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13162.641735                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13162.641735                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13162.641735                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13162.641735                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13162.641735                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       318144                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       318144                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       318144                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       318144                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       318144                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       318144                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3551128508                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   3551128508                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3551128508                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   3551128508                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3551128508                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   3551128508                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.024528                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.024528                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.024528                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.024528                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.024528                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.024528                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11162.016282                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11162.016282                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11162.016282                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11162.016282                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11162.016282                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11162.016282                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements           159205                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          486.204508                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            3919863                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           159531                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            24.571168                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     1048842695500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   486.204508                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.949618                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.949618                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data      2222453                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        2222453                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      1596000                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       1596000                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        48034                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        48034                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        50617                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        50617                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      3818453                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         3818453                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      3818453                       # number of overall hits
system.cpu1.dcache.overall_hits::total        3818453                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       116850                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       116850                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data        57159                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total        57159                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         9086                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         9086                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data         6023                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total         6023                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       174009                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        174009                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       174009                       # number of overall misses
system.cpu1.dcache.overall_misses::total       174009                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1411488249                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   1411488249                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   1045308027                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   1045308027                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     82519500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total     82519500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     44276427                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     44276427                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   2456796276                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   2456796276                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   2456796276                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   2456796276                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      2339303                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      2339303                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      1653159                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      1653159                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        57120                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        57120                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        56640                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        56640                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      3992462                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      3992462                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      3992462                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      3992462                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.049951                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.049951                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.034576                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.034576                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.159069                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.159069                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.106338                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.106338                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.043584                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.043584                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.043584                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.043584                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12079.488652                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12079.488652                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18287.724190                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 18287.724190                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9082.049307                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9082.049307                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7351.224805                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7351.224805                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14118.788545                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 14118.788545                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14118.788545                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 14118.788545                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       109639                       # number of writebacks
system.cpu1.dcache.writebacks::total           109639                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       116850                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       116850                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        57159                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        57159                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         9086                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         9086                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         6023                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total         6023                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       174009                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       174009                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       174009                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       174009                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1177711751                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1177711751                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data    928682973                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total    928682973                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     64347500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     64347500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     32228573                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     32228573                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   2106394724                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   2106394724                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   2106394724                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   2106394724                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     18769000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     18769000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    718428000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    718428000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    737197000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    737197000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.049951                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.049951                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.034576                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.034576                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.159069                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.159069                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.106338                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.106338                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.043584                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.043584                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.043584                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.043584                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10078.833984                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10078.833984                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16247.362148                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16247.362148                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7082.049307                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7082.049307                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5350.916985                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5350.916985                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12105.090679                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12105.090679                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12105.090679                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12105.090679                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------