path: root/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.962822                       # Number of seconds simulated
sim_ticks                                1962822184500                       # Number of ticks simulated
final_tick                               1962822184500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 916137                       # Simulator instruction rate (inst/s)
host_op_rate                                   916137                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            30287148246                       # Simulator tick rate (ticks/s)
host_mem_usage                                 346744                       # Number of bytes of host memory used
host_seconds                                    64.81                       # Real time elapsed on the host
sim_insts                                    59372170                       # Number of instructions simulated
sim_ops                                      59372170                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.inst           724800                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         24150336                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2649344                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           138496                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          1080640                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28743616                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       724800                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       138496                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          863296                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7747520                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7747520                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst             11325                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            377349                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41396                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              2164                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             16885                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                449119                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          121055                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               121055                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              369264                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            12303884                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1349763                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               70560                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              550554                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                14644024                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         369264                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          70560                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             439824                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3947133                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3947133                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3947133                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             369264                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           12303884                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1349763                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              70560                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             550554                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               18591157                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        449119                       # Number of read requests accepted
system.physmem.writeReqs                       121055                       # Number of write requests accepted
system.physmem.readBursts                      449119                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     121055                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 28736320                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7296                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7746176                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  28743616                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7747520                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      114                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           3360                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               28065                       # Per bank write bursts
system.physmem.perBankRdBursts::1               28141                       # Per bank write bursts
system.physmem.perBankRdBursts::2               27986                       # Per bank write bursts
system.physmem.perBankRdBursts::3               28553                       # Per bank write bursts
system.physmem.perBankRdBursts::4               28160                       # Per bank write bursts
system.physmem.perBankRdBursts::5               27775                       # Per bank write bursts
system.physmem.perBankRdBursts::6               27616                       # Per bank write bursts
system.physmem.perBankRdBursts::7               27528                       # Per bank write bursts
system.physmem.perBankRdBursts::8               27559                       # Per bank write bursts
system.physmem.perBankRdBursts::9               27974                       # Per bank write bursts
system.physmem.perBankRdBursts::10              27981                       # Per bank write bursts
system.physmem.perBankRdBursts::11              28021                       # Per bank write bursts
system.physmem.perBankRdBursts::12              28612                       # Per bank write bursts
system.physmem.perBankRdBursts::13              28738                       # Per bank write bursts
system.physmem.perBankRdBursts::14              28459                       # Per bank write bursts
system.physmem.perBankRdBursts::15              27837                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7862                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7636                       # Per bank write bursts
system.physmem.perBankWrBursts::2                7481                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8065                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7619                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7244                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7159                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6941                       # Per bank write bursts
system.physmem.perBankWrBursts::8                6882                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7297                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7427                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7400                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8124                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8265                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8168                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7464                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           8                       # Number of times write queue was full causing retry
system.physmem.totGap                    1962815073500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  449119                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 121055                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    407912                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      1721                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      2712                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      1276                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      1995                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      4350                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      3947                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      3971                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      2533                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      2190                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     2125                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     2091                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1633                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1613                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     1890                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     1879                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                     2087                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                     1205                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      975                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      896                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1425                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1547                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4875                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4920                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4927                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4931                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     4933                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5043                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5216                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     5300                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5467                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5674                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5678                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     5762                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     5841                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     5977                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5938                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6015                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      879                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      905                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      923                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      879                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      937                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      961                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1045                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      965                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     1159                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     1188                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     1167                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     1240                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     1400                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     1637                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     1890                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     2102                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                     1946                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                     1888                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                     1710                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                     1689                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                     1830                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                     1638                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      806                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      341                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      205                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       40                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       32                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       20                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       14                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        68642                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      531.489409                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     323.678439                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     416.279001                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          15609     22.74%     22.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        11929     17.38%     40.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5150      7.50%     47.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3087      4.50%     52.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         3390      4.94%     57.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1779      2.59%     59.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1473      2.15%     61.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1315      1.92%     63.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        24910     36.29%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          68642                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          7087                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        63.355581                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     1920.089024                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-4095           7082     99.93%     99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-8191            1      0.01%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-45055            1      0.01%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-61439            1      0.01%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::73728-77823            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::122880-126975            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            7087                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          7087                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.078312                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.846071                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        3.814192                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               5314     74.98%     74.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                115      1.62%     76.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18               1264     17.84%     94.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                 37      0.52%     94.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                 12      0.17%     95.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 12      0.17%     95.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 26      0.37%     95.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 96      1.35%     97.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 18      0.25%     97.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                 39      0.55%     97.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                 16      0.23%     98.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                 10      0.14%     98.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                 12      0.17%     98.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29                  8      0.11%     98.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30                  4      0.06%     98.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31                 15      0.21%     98.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32                  3      0.04%     98.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34                  4      0.06%     98.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::35                  2      0.03%     98.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36                  1      0.01%     98.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::37                  3      0.04%     98.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::38                  2      0.03%     98.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::39                 10      0.14%     99.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40                  6      0.08%     99.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::41                  6      0.08%     99.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42                  2      0.03%     99.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::43                  2      0.03%     99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44                  2      0.03%     99.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::45                  4      0.06%     99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::46                  1      0.01%     99.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::47                 10      0.14%     99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48                  2      0.03%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::50                  2      0.03%     99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::55                  1      0.01%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56                  9      0.13%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::57                 14      0.20%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::58                  3      0.04%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            7087                       # Writes before turning the bus around for reads
system.physmem.totQLat                     7297703000                       # Total ticks spent queuing
system.physmem.totMemAccLat               15716546750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2245025000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       16253.06                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  35003.06                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          14.64                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.95                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       14.64                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.95                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.12                       # Average write queue length when enqueuing
system.physmem.readRowHits                     403892                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     97505                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   89.95                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  80.55                       # Row buffer hit rate for writes
system.physmem.avgGap                      3442484.35                       # Average gap between requests
system.physmem.pageHitRate                      87.96                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     1840580762750                       # Time in different power states
system.physmem.memoryStateTime::REF       65542880000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       56696821000                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.membus.throughput                     18645480                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              292657                       # Transaction distribution
system.membus.trans_dist::ReadResp             292657                       # Transaction distribution
system.membus.trans_dist::WriteReq              12414                       # Transaction distribution
system.membus.trans_dist::WriteResp             12414                       # Transaction distribution
system.membus.trans_dist::Writeback            121055                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4555                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq           1018                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            3360                       # Transaction distribution
system.membus.trans_dist::ReadExReq            164356                       # Transaction distribution
system.membus.trans_dist::ReadExResp           164254                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        39228                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       904273                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       943501                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124647                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       124647                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1068148                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave        68738                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     31184320                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total     31253058                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5306816                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total      5306816                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            36559874                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               36559874                       # Total data (bytes)
system.membus.snoop_data_through_bus            37888                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy            39221000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy          1574833000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer1.occupancy         3826410374                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy          376647250                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                   342221                       # number of replacements
system.l2c.tags.tagsinuse                65256.412579                       # Cycle average of tags in use
system.l2c.tags.total_refs                    2544259                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   407367                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     6.245619                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               8652281750                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   55518.574788                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3744.543964                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     4299.514442                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     1171.756098                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      522.023286                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.847146                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.057137                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.065605                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.017880                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.007965                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.995734                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024        65146                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          752                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         5288                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         7256                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        51736                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.994049                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 26948745                       # Number of tag accesses
system.l2c.tags.data_accesses                26948745                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.inst             527962                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             377923                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             461443                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             449896                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1817224                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          850135                       # number of Writeback hits
system.l2c.Writeback_hits::total               850135                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data             136                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              70                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 206                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            24                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            20                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                44                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           113466                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            85009                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               198475                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst              527962                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              491389                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              461443                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              534905                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2015699                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst             527962                       # number of overall hits
system.l2c.overall_hits::cpu0.data             491389                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             461443                       # number of overall hits
system.l2c.overall_hits::cpu1.data             534905                       # number of overall hits
system.l2c.overall_hits::total                2015699                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst            11328                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           270740                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             2172                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             1052                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               285292                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          2603                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           468                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              3071                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data           62                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data           80                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total             142                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         107000                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          15849                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             122849                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst             11328                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            377740                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              2172                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             16901                       # number of demand (read+write) misses
system.l2c.demand_misses::total                408141                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst            11328                       # number of overall misses
system.l2c.overall_misses::cpu0.data           377740                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             2172                       # number of overall misses
system.l2c.overall_misses::cpu1.data            16901                       # number of overall misses
system.l2c.overall_misses::total               408141                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst    833297996                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data  17596590486                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    160787750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data     79756250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    18670432482                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data       706471                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       350485                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      1056956                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       162493                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data        92496                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       254989                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   7343044869                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   1158336734                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   8501381603                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst    833297996                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  24939635355                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    160787750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   1238092984                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     27171814085                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst    833297996                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  24939635355                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    160787750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   1238092984                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    27171814085                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst         539290                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         648663                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         463615                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         450948                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2102516                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       850135                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           850135                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         2739                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          538                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            3277                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data           86                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          100                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total           186                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       220466                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       100858                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           321324                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst          539290                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          869129                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          463615                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          551806                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2423840                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         539290                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         869129                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         463615                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         551806                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2423840                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.021005                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.417382                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.004685                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.002333                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.135691                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.950347                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.869888                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.937138                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.720930                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.800000                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.763441                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.485336                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.157142                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.382321                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.021005                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.434619                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.004685                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.030629                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.168386                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.021005                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.434619                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.004685                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.030629                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.168386                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73560.910664                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 64994.424488                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74027.509208                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 75813.925856                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 65443.238794                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   271.406454                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   748.899573                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   344.173233                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  2620.854839                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1156.200000                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  1795.697183                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 68626.587561                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73085.793047                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 69201.878754                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 73560.910664                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 66023.284150                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 74027.509208                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 73255.605230                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 66574.576151                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 73560.910664                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 66023.284150                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 74027.509208                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 73255.605230                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 66574.576151                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               79532                       # number of writebacks
system.l2c.writebacks::total                    79532                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             3                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             8                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                11                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              8                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 11                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             8                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                11                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst        11325                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data       270740                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         2164                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         1052                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          285281                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         2603                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          468                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         3071                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           62                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           80                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total          142                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       107000                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        15849                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        122849                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        11325                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       377740                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         2164                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        16901                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           408130                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        11325                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       377740                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         2164                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        16901                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          408130                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    689008754                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data  14211795014                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    132703500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data     66581750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  15100089018                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     26041101                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      4800968                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     30842069                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       620062                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       800080                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total      1420142                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   5999010131                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    959576266                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   6958586397                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    689008754                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  20210805145                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    132703500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   1026158016                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  22058675415                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    689008754                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  20210805145                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    132703500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   1026158016                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  22058675415                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data    941946500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    449028500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   1390975000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1618779500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    858260500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   2477040000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2560726000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1307289000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   3868015000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.021000                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.417382                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.004668                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.002333                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.135686                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.950347                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.869888                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.937138                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.720930                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.763441                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.485336                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.157142                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.382321                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.021000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.434619                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.004668                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.030629                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.168382                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.021000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.434619                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.004668                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.030629                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.168382                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60839.625077                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52492.409744                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61323.243993                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63290.636882                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 52930.580789                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.264695                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10258.478632                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10043.005210                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56065.515243                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60544.909206                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 56643.410992                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60839.625077                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53504.540544                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61323.243993                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60715.816579                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 54048.159692                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60839.625077                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53504.540544                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61323.243993                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60715.816579                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 54048.159692                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.tags.replacements                41699                       # number of replacements
system.iocache.tags.tagsinuse                0.570023                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41715                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1756486423000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     0.570023                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.035626                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.035626                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               375552                       # Number of tag accesses
system.iocache.tags.data_accesses              375552                       # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide          176                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              176                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41728                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41728                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41728                       # number of overall misses
system.iocache.overall_misses::total            41728                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21474883                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21474883                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide  12370994210                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  12370994210                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide  12392469093                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  12392469093                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide  12392469093                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  12392469093                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          176                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            176                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41728                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41728                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41728                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41728                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122016.380682                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 122016.380682                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 297723.195273                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 297723.195273                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 296982.100580                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 296982.100580                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 296982.100580                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 296982.100580                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        362942                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                28216                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    12.862986                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41523                       # number of writebacks
system.iocache.writebacks::total                41523                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          176                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          176                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41728                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41728                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41728                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41728                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12321883                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     12321883                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  10208100710                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total  10208100710                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide  10220422593                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total  10220422593                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide  10220422593                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total  10220422593                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70010.698864                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70010.698864                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 245670.502262                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 245670.502262                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 244929.605852                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 244929.605852                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 244929.605852                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 244929.605852                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     6067358                       # DTB read hits
system.cpu0.dtb.read_misses                      7765                       # DTB read misses
system.cpu0.dtb.read_acv                          210                       # DTB read access violations
system.cpu0.dtb.read_accesses                  524069                       # DTB read accesses
system.cpu0.dtb.write_hits                    4265662                       # DTB write hits
system.cpu0.dtb.write_misses                      910                       # DTB write misses
system.cpu0.dtb.write_acv                         133                       # DTB write access violations
system.cpu0.dtb.write_accesses                 202595                       # DTB write accesses
system.cpu0.dtb.data_hits                    10333020                       # DTB hits
system.cpu0.dtb.data_misses                      8675                       # DTB misses
system.cpu0.dtb.data_acv                          343                       # DTB access violations
system.cpu0.dtb.data_accesses                  726664                       # DTB accesses
system.cpu0.itb.fetch_hits                    3354842                       # ITB hits
system.cpu0.itb.fetch_misses                     3984                       # ITB misses
system.cpu0.itb.fetch_acv                         184                       # ITB acv
system.cpu0.itb.fetch_accesses                3358826                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                      3925644369                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   38276564                       # Number of instructions committed
system.cpu0.committedOps                     38276564                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             35596868                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                153627                       # Number of float alu accesses
system.cpu0.num_func_calls                     936507                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      4464991                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    35596868                       # number of integer instructions
system.cpu0.num_fp_insts                       153627                       # number of float instructions
system.cpu0.num_int_register_reads           48919002                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          26532177                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads               75066                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes              75978                       # number of times the floating registers were written
system.cpu0.num_mem_refs                     10366198                       # number of memory refs
system.cpu0.num_load_insts                    6090760                       # Number of load instructions
system.cpu0.num_store_insts                   4275438                       # Number of store instructions
system.cpu0.num_idle_cycles              3742234246.498094                       # Number of idle cycles
system.cpu0.num_busy_cycles              183410122.501907                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.046721                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.953279                       # Percentage of idle cycles
system.cpu0.Branches                          5694814                       # Number of branches fetched
system.cpu0.op_class::No_OpClass              2096369      5.48%      5.48% # Class of executed instruction
system.cpu0.op_class::IntAlu                 24995370     65.29%     70.76% # Class of executed instruction
system.cpu0.op_class::IntMult                   39322      0.10%     70.86% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     70.86% # Class of executed instruction
system.cpu0.op_class::FloatAdd                  12602      0.03%     70.90% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     70.90% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     70.90% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     70.90% # Class of executed instruction
system.cpu0.op_class::FloatDiv                   1883      0.00%     70.90% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     70.90% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     70.90% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     70.90% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     70.90% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     70.90% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     70.90% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     70.90% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     70.90% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     70.90% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     70.90% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     70.90% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     70.90% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     70.90% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     70.90% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     70.90% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     70.90% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     70.90% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc                 0      0.00%     70.90% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     70.90% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     70.90% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     70.90% # Class of executed instruction
system.cpu0.op_class::MemRead                 6233117     16.28%     87.18% # Class of executed instruction
system.cpu0.op_class::MemWrite                4280683     11.18%     98.36% # Class of executed instruction
system.cpu0.op_class::IprAccess                626236      1.64%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                  38285582                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    4866                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    138364                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   44810     38.76%     38.76% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    131      0.11%     38.88% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1975      1.71%     40.58% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                     16      0.01%     40.60% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                  68668     59.40%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              115600                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    44285     48.84%     48.84% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     131      0.14%     48.98% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1975      2.18%     51.16% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                      16      0.02%     51.18% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   44269     48.82%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total                90676                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1909704051500     97.29%     97.29% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               94854000      0.00%     97.30% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              764030500      0.04%     97.34% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30               12585500      0.00%     97.34% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            52245891000      2.66%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1962821412500                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.988284                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.644682                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.784394                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         8      3.42%      3.42% # number of syscalls executed
system.cpu0.kern.syscall::3                        20      8.55%     11.97% # number of syscalls executed
system.cpu0.kern.syscall::4                         4      1.71%     13.68% # number of syscalls executed
system.cpu0.kern.syscall::6                        33     14.10%     27.78% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.43%     28.21% # number of syscalls executed
system.cpu0.kern.syscall::17                       10      4.27%     32.48% # number of syscalls executed
system.cpu0.kern.syscall::19                       10      4.27%     36.75% # number of syscalls executed
system.cpu0.kern.syscall::20                        6      2.56%     39.32% # number of syscalls executed
system.cpu0.kern.syscall::23                        1      0.43%     39.74% # number of syscalls executed
system.cpu0.kern.syscall::24                        3      1.28%     41.03% # number of syscalls executed
system.cpu0.kern.syscall::33                        8      3.42%     44.44% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.85%     45.30% # number of syscalls executed
system.cpu0.kern.syscall::45                       39     16.67%     61.97% # number of syscalls executed
system.cpu0.kern.syscall::47                        3      1.28%     63.25% # number of syscalls executed
system.cpu0.kern.syscall::48                       10      4.27%     67.52% # number of syscalls executed
system.cpu0.kern.syscall::54                       10      4.27%     71.79% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.43%     72.22% # number of syscalls executed
system.cpu0.kern.syscall::59                        6      2.56%     74.79% # number of syscalls executed
system.cpu0.kern.syscall::71                       27     11.54%     86.32% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.28%     87.61% # number of syscalls executed
system.cpu0.kern.syscall::74                        7      2.99%     90.60% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.43%     91.03% # number of syscalls executed
system.cpu0.kern.syscall::90                        3      1.28%     92.31% # number of syscalls executed
system.cpu0.kern.syscall::92                        9      3.85%     96.15% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.85%     97.01% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.85%     97.86% # number of syscalls executed
system.cpu0.kern.syscall::132                       1      0.43%     98.29% # number of syscalls executed
system.cpu0.kern.syscall::144                       2      0.85%     99.15% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.85%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   234                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                   86      0.07%      0.07% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.07% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.07% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.07% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 2218      1.80%      1.88% # number of callpals executed
system.cpu0.kern.callpal::tbi                      51      0.04%      1.92% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.01%      1.92% # number of callpals executed
system.cpu0.kern.callpal::swpipl               109461     88.95%     90.88% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6662      5.41%     96.29% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.29% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     4      0.00%     96.29% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     9      0.01%     96.30% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     96.30% # number of callpals executed
system.cpu0.kern.callpal::rti                    4016      3.26%     99.57% # number of callpals executed
system.cpu0.kern.callpal::callsys                 394      0.32%     99.89% # number of callpals executed
system.cpu0.kern.callpal::imb                     139      0.11%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                123054                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             5726                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1371                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1370                      
system.cpu0.kern.mode_good::user                 1371                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch_good::kernel     0.239260                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.386220                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1959031016000     99.81%     99.81% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          3790392000      0.19%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    2219                       # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.toL2Bus.throughput                   108070579                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq            2148343                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2148328                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             12414                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            12414                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           850135                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            4614                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq          1062                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           5676                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           363639                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          322090                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1078600                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2181406                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       927231                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      1598323                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               5785560                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     34514560                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     81611821                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     29671360                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     63815893                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total          209613634                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus             209603138                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus         2520192                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy         5075991989                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.3                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           738000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2429088500                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        4030648808                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy        2086694241                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy        2646669064                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.1                       # Layer utilization (%)
system.iobus.throughput                       1391043                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq                 7376                       # Transaction distribution
system.iobus.trans_dist::ReadResp                7376                       # Transaction distribution
system.iobus.trans_dist::WriteReq               53966                       # Transaction distribution
system.iobus.trans_dist::WriteResp              53966                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        10614                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          484                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18148                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2474                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        39228                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83456                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        83456                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  122684                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        42456                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio         1936                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio         9074                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9876                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total        68738                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661632                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      2661632                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total              2730370                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                 2730370                       # Total data (bytes)
system.iobus.reqLayer0.occupancy              9969000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               362000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            13505000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy             2453000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy               76000                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer29.occupancy           380139843                       # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            26814000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            43231750                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.cpu0.icache.tags.replacements           538677                       # number of replacements
system.cpu0.icache.tags.tagsinuse          508.393435                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           37746273                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           539189                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            70.005644                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      40276505250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   508.393435                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.992956                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.992956                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          442                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3           17                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         38824893                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        38824893                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     37746273                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       37746273                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     37746273                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        37746273                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     37746273                       # number of overall hits
system.cpu0.icache.overall_hits::total       37746273                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       539310                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       539310                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       539310                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        539310                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       539310                       # number of overall misses
system.cpu0.icache.overall_misses::total       539310                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   7764312000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   7764312000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   7764312000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   7764312000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   7764312000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   7764312000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     38285583                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     38285583                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     38285583                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     38285583                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     38285583                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     38285583                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014087                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.014087                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014087                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.014087                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014087                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.014087                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14396.751405                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14396.751405                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14396.751405                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14396.751405                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14396.751405                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14396.751405                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       539310                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       539310                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       539310                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       539310                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       539310                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       539310                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   6681305000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   6681305000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   6681305000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   6681305000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   6681305000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   6681305000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014087                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014087                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014087                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.014087                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014087                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.014087                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12388.616936                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12388.616936                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12388.616936                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12388.616936                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12388.616936                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12388.616936                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements           871224                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          481.747613                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs            9466123                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           871736                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            10.858933                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        108210250                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   481.747613                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.940913                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.940913                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          322                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         42234072                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        42234072                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      5299987                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        5299987                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3905819                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3905819                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       124795                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       124795                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       131586                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       131586                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data      9205806                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total         9205806                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      9205806                       # number of overall hits
system.cpu0.dcache.overall_hits::total        9205806                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       645326                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       645326                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       224198                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       224198                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         7833                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total         7833                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data          495                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total          495                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       869524                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        869524                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       869524                       # number of overall misses
system.cpu0.dcache.overall_misses::total       869524                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  23374169264                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  23374169264                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   9262123232                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   9262123232                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    102899750                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    102899750                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      3567062                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total      3567062                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  32636292496                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  32636292496                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  32636292496                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  32636292496                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      5945313                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      5945313                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      4130017                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      4130017                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       132628                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       132628                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       132081                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       132081                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     10075330                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     10075330                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     10075330                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     10075330                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.108544                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.108544                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.054285                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.054285                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059060                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059060                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.003748                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.003748                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.086302                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.086302                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.086302                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.086302                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 36220.715211                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 36220.715211                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41312.247353                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 41312.247353                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13136.697306                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13136.697306                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7206.185859                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7206.185859                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37533.515459                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 37533.515459                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37533.515459                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 37533.515459                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       405192                       # number of writebacks
system.cpu0.dcache.writebacks::total           405192                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       645326                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       645326                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       224198                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       224198                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         7833                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         7833                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          495                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total          495                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       869524                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       869524                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       869524                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       869524                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  21958342736                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  21958342736                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   8764766768                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8764766768                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     87220250                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     87220250                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      2576938                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      2576938                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  30723109504                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  30723109504                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  30723109504                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  30723109504                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1004924500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1004924500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1718153000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1718153000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2723077500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2723077500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.108544                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.108544                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.054285                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.054285                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059060                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059060                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.003748                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.003748                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.086302                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.086302                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.086302                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.086302                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34026.744213                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34026.744213                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39093.866886                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39093.866886                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11134.973829                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11134.973829                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  5205.935354                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  5205.935354                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35333.250726                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35333.250726                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35333.250726                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35333.250726                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     3617105                       # DTB read hits
system.cpu1.dtb.read_misses                      2620                       # DTB read misses
system.cpu1.dtb.read_acv                            0                       # DTB read access violations
system.cpu1.dtb.read_accesses                  205337                       # DTB read accesses
system.cpu1.dtb.write_hits                    2433899                       # DTB write hits
system.cpu1.dtb.write_misses                      235                       # DTB write misses
system.cpu1.dtb.write_acv                          24                       # DTB write access violations
system.cpu1.dtb.write_accesses                  89739                       # DTB write accesses
system.cpu1.dtb.data_hits                     6051004                       # DTB hits
system.cpu1.dtb.data_misses                      2855                       # DTB misses
system.cpu1.dtb.data_acv                           24                       # DTB access violations
system.cpu1.dtb.data_accesses                  295076                       # DTB accesses
system.cpu1.itb.fetch_hits                    1988116                       # ITB hits
system.cpu1.itb.fetch_misses                     1064                       # ITB misses
system.cpu1.itb.fetch_acv                           0                       # ITB acv
system.cpu1.itb.fetch_accesses                1989180                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                      3923841481                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   21095606                       # Number of instructions committed
system.cpu1.committedOps                     21095606                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             19410796                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                175175                       # Number of float alu accesses
system.cpu1.num_func_calls                     648522                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      2286515                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    19410796                       # number of integer instructions
system.cpu1.num_fp_insts                       175175                       # number of float instructions
system.cpu1.num_int_register_reads           26519930                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          14289781                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads               90745                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes              92744                       # number of times the floating registers were written
system.cpu1.num_mem_refs                      6073244                       # number of memory refs
system.cpu1.num_load_insts                    3630952                       # Number of load instructions
system.cpu1.num_store_insts                   2442292                       # Number of store instructions
system.cpu1.num_idle_cycles              3837671905.347151                       # Number of idle cycles
system.cpu1.num_busy_cycles              86169575.652849                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.021961                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.978039                       # Percentage of idle cycles
system.cpu1.Branches                          3164985                       # Number of branches fetched
system.cpu1.op_class::No_OpClass              1250072      5.92%      5.92% # Class of executed instruction
system.cpu1.op_class::IntAlu                 13187049     62.50%     68.43% # Class of executed instruction
system.cpu1.op_class::IntMult                   30193      0.14%     68.57% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     68.57% # Class of executed instruction
system.cpu1.op_class::FloatAdd                  13163      0.06%     68.63% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     68.63% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     68.63% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     68.63% # Class of executed instruction
system.cpu1.op_class::FloatDiv                   1759      0.01%     68.64% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     68.64% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     68.64% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     68.64% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     68.64% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     68.64% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     68.64% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     68.64% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     68.64% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     68.64% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     68.64% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     68.64% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     68.64% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     68.64% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     68.64% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     68.64% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     68.64% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     68.64% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc                 0      0.00%     68.64% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     68.64% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     68.64% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     68.64% # Class of executed instruction
system.cpu1.op_class::MemRead                 3726131     17.66%     86.30% # Class of executed instruction
system.cpu1.op_class::MemWrite                2443312     11.58%     97.88% # Class of executed instruction
system.cpu1.op_class::IprAccess                446806      2.12%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  21098485                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    3863                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                    100735                       # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0                   37219     40.29%     40.29% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1970      2.13%     42.42% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                     86      0.09%     42.51% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  53109     57.49%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               92384                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                    36367     48.68%     48.68% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1970      2.64%     51.32% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                      86      0.12%     51.43% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                   36281     48.57%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                74704                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1906656399000     97.18%     97.18% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              706249000      0.04%     97.22% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30               59367000      0.00%     97.22% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            54498695500      2.78%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1961920710500                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.977108                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.683142                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total             0.808625                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3                        10     10.87%     10.87% # number of syscalls executed
system.cpu1.kern.syscall::6                         9      9.78%     20.65% # number of syscalls executed
system.cpu1.kern.syscall::15                        1      1.09%     21.74% # number of syscalls executed
system.cpu1.kern.syscall::17                        5      5.43%     27.17% # number of syscalls executed
system.cpu1.kern.syscall::23                        3      3.26%     30.43% # number of syscalls executed
system.cpu1.kern.syscall::24                        3      3.26%     33.70% # number of syscalls executed
system.cpu1.kern.syscall::33                        3      3.26%     36.96% # number of syscalls executed
system.cpu1.kern.syscall::45                       15     16.30%     53.26% # number of syscalls executed
system.cpu1.kern.syscall::47                        3      3.26%     56.52% # number of syscalls executed
system.cpu1.kern.syscall::59                        1      1.09%     57.61% # number of syscalls executed
system.cpu1.kern.syscall::71                       27     29.35%     86.96% # number of syscalls executed
system.cpu1.kern.syscall::74                        9      9.78%     96.74% # number of syscalls executed
system.cpu1.kern.syscall::132                       3      3.26%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                    92                       # number of syscalls executed
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                   16      0.02%      0.02% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.02% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.02% # number of callpals executed
system.cpu1.kern.callpal::swpctx                 2020      2.13%      2.15% # number of callpals executed
system.cpu1.kern.callpal::tbi                       3      0.00%      2.16% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.01%      2.16% # number of callpals executed
system.cpu1.kern.callpal::swpipl                87061     91.90%     94.06% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2187      2.31%     96.37% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     96.37% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     3      0.00%     96.38% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.00%     96.38% # number of callpals executed
system.cpu1.kern.callpal::rti                    3266      3.45%     99.83% # number of callpals executed
system.cpu1.kern.callpal::callsys                 121      0.13%     99.95% # number of callpals executed
system.cpu1.kern.callpal::imb                      42      0.04%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 94734                       # number of callpals executed
system.cpu1.kern.mode_switch::kernel             2415                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                366                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2037                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                414                      
system.cpu1.kern.mode_good::user                  366                      
system.cpu1.kern.mode_good::idle                   48                      
system.cpu1.kern.mode_switch_good::kernel     0.171429                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.023564                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     0.171856                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel       65780447000      3.35%      3.35% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user          1486717000      0.08%      3.43% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1893764152500     96.57%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                    2021                       # number of times the context was actually changed
system.cpu1.icache.tags.replacements           463064                       # number of replacements
system.cpu1.icache.tags.tagsinuse          500.061225                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           20634869                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           463576                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            44.512376                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      97712638250                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   500.061225                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.976682                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.976682                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          108                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3          404                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         21562101                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        21562101                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst     20634869                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       20634869                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     20634869                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        20634869                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     20634869                       # number of overall hits
system.cpu1.icache.overall_hits::total       20634869                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       463616                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       463616                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       463616                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        463616                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       463616                       # number of overall misses
system.cpu1.icache.overall_misses::total       463616                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   6201828741                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   6201828741                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   6201828741                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   6201828741                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   6201828741                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   6201828741                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     21098485                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     21098485                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     21098485                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     21098485                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     21098485                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     21098485                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.021974                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.021974                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.021974                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.021974                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.021974                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.021974                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13377.080905                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13377.080905                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13377.080905                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13377.080905                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13377.080905                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13377.080905                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       463616                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       463616                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       463616                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       463616                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       463616                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       463616                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5273752259                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   5273752259                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5273752259                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   5273752259                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5273752259                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   5273752259                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.021974                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.021974                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.021974                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.021974                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.021974                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.021974                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11375.259394                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11375.259394                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11375.259394                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11375.259394                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11375.259394                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11375.259394                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements           581734                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          492.027113                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            5462976                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           582077                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs             9.385315                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle      61159690250                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   492.027113                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.960990                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.960990                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          343                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           43                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3          300                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.669922                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         24828652                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        24828652                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      3080166                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        3080166                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      2260006                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       2260006                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        60928                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        60928                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        71558                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        71558                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      5340172                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         5340172                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      5340172                       # number of overall hits
system.cpu1.dcache.overall_hits::total        5340172                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       473210                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       473210                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       102503                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       102503                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11672                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        11672                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data          567                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total          567                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       575713                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        575713                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       575713                       # number of overall misses
system.cpu1.dcache.overall_misses::total       575713                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   5938920500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   5938920500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2340100234                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   2340100234                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    149905750                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    149905750                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      4163080                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total      4163080                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   8279020734                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   8279020734                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   8279020734                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   8279020734                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      3553376                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      3553376                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      2362509                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      2362509                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        72600                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        72600                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        72125                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        72125                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      5915885                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      5915885                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      5915885                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      5915885                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.133172                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.133172                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.043387                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.043387                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.160771                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.160771                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.007861                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.007861                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.097316                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.097316                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.097316                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.097316                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12550.285286                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12550.285286                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22829.578003                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 22829.578003                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12843.193112                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12843.193112                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7342.292769                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7342.292769                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14380.465152                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 14380.465152                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14380.465152                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 14380.465152                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       444943                       # number of writebacks
system.cpu1.dcache.writebacks::total           444943                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       473210                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       473210                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       102503                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       102503                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        11672                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total        11672                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          567                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total          567                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       575713                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       575713                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       575713                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       575713                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   4992146500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   4992146500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2128603766                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2128603766                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    126561250                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total    126561250                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      3028920                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      3028920                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   7120750266                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   7120750266                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   7120750266                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   7120750266                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    479658500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    479658500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    907861000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    907861000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1387519500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1387519500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.133172                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.133172                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.043387                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.043387                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.160771                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.160771                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.007861                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.007861                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.097316                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.097316                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.097316                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.097316                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10549.537203                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10549.537203                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20766.258217                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20766.258217                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10843.150274                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10843.150274                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5342.010582                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5342.010582                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12368.576471                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12368.576471                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12368.576471                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12368.576471                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------