path: root/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.941276                       # Number of seconds simulated
sim_ticks                                1941275996000                       # Number of ticks simulated
final_tick                               1941275996000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1048317                       # Simulator instruction rate (inst/s)
host_op_rate                                  1048317                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            36222399744                       # Simulator tick rate (ticks/s)
host_mem_usage                                 330588                       # Number of bytes of host memory used
host_seconds                                    53.59                       # Real time elapsed on the host
sim_insts                                    56182685                       # Number of instructions simulated
sim_ops                                      56182685                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            844800                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24856512                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             25702272                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       844800                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          844800                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7410752                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7410752                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst              13200                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             388383                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                401598                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          115793                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               115793                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               435178                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             12804213                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide               495                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                13239886                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          435178                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             435178                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3817464                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3817464                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3817464                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              435178                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            12804213                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide              495                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               17057350                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        401598                       # Number of read requests accepted
system.physmem.writeReqs                       115793                       # Number of write requests accepted
system.physmem.readBursts                      401598                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     115793                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 25694784                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7488                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7408704                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  25702272                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7410752                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      117                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               25225                       # Per bank write bursts
system.physmem.perBankRdBursts::1               25628                       # Per bank write bursts
system.physmem.perBankRdBursts::2               25541                       # Per bank write bursts
system.physmem.perBankRdBursts::3               25494                       # Per bank write bursts
system.physmem.perBankRdBursts::4               25069                       # Per bank write bursts
system.physmem.perBankRdBursts::5               24955                       # Per bank write bursts
system.physmem.perBankRdBursts::6               24242                       # Per bank write bursts
system.physmem.perBankRdBursts::7               24604                       # Per bank write bursts
system.physmem.perBankRdBursts::8               25085                       # Per bank write bursts
system.physmem.perBankRdBursts::9               24651                       # Per bank write bursts
system.physmem.perBankRdBursts::10              25269                       # Per bank write bursts
system.physmem.perBankRdBursts::11              24875                       # Per bank write bursts
system.physmem.perBankRdBursts::12              24508                       # Per bank write bursts
system.physmem.perBankRdBursts::13              25360                       # Per bank write bursts
system.physmem.perBankRdBursts::14              25616                       # Per bank write bursts
system.physmem.perBankRdBursts::15              25359                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7625                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7638                       # Per bank write bursts
system.physmem.perBankWrBursts::2                7842                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7532                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7224                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6973                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6356                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6427                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7248                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6409                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7117                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6905                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7093                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7822                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7863                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7687                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           8                       # Number of times write queue was full causing retry
system.physmem.totGap                    1941264122500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  401598                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 115793                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    401467                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1806                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3249                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     7105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5703                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6714                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5907                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5702                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6222                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     6746                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6250                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     8385                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7085                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7386                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     6734                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6941                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5812                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5400                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      238                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      188                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      170                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      137                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      203                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      108                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      138                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      138                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      146                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      179                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      218                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      158                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      212                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      264                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      181                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      256                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      159                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      122                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      116                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      115                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      118                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       31                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       34                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        64912                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      509.974858                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     310.431433                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     406.117715                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          15298     23.57%     23.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        11509     17.73%     41.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         4967      7.65%     48.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3096      4.77%     53.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2467      3.80%     57.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         4201      6.47%     63.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1427      2.20%     66.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         2061      3.18%     69.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        19886     30.64%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          64912                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5093                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        78.826036                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     2956.913485                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191           5090     99.94%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5093                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5093                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        22.729433                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       19.333640                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       21.082746                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23            4499     88.34%     88.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31              29      0.57%     88.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39              20      0.39%     89.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47              41      0.81%     90.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55             209      4.10%     94.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63              11      0.22%     94.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71              11      0.22%     94.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79              30      0.59%     95.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87             184      3.61%     98.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95               6      0.12%     98.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103              5      0.10%     99.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111             4      0.08%     99.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127             1      0.02%     99.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135             8      0.16%     99.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143             5      0.10%     99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151             1      0.02%     99.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167             4      0.08%     99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175             5      0.10%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183             5      0.10%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191             1      0.02%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199             2      0.04%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215             7      0.14%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-247             1      0.02%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263             4      0.08%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5093                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2720413750                       # Total ticks spent queuing
system.physmem.totMemAccLat               10248182500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2007405000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        6775.95                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  25525.95                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          13.24                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.82                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       13.24                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.82                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.13                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.10                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        22.10                       # Average write queue length when enqueuing
system.physmem.readRowHits                     358846                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     93484                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   89.38                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  80.73                       # Row buffer hit rate for writes
system.physmem.avgGap                      3752025.30                       # Average gap between requests
system.physmem.pageHitRate                      87.44                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  240264360                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  131096625                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1565912400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                373358160                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           126794687760                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            71567841690                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1101986721000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1302659881995                       # Total energy per rank (pJ)
system.physmem_0.averagePower              671.032847                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   1832974788000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     64823460000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     43477648250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  250470360                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  136665375                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1565639400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                376773120                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           126794687760                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            72629101890                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1101055791000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1302809128905                       # Total energy per rank (pJ)
system.physmem_1.averagePower              671.109728                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   1831423384000                       # Time in different power states
system.physmem_1.memoryStateTime::REF     64823460000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     45029052250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                      9064642                       # DTB read hits
system.cpu.dtb.read_misses                      10324                       # DTB read misses
system.cpu.dtb.read_acv                           210                       # DTB read access violations
system.cpu.dtb.read_accesses                   728853                       # DTB read accesses
system.cpu.dtb.write_hits                     6356200                       # DTB write hits
system.cpu.dtb.write_misses                      1142                       # DTB write misses
system.cpu.dtb.write_acv                          157                       # DTB write access violations
system.cpu.dtb.write_accesses                  291931                       # DTB write accesses
system.cpu.dtb.data_hits                     15420842                       # DTB hits
system.cpu.dtb.data_misses                      11466                       # DTB misses
system.cpu.dtb.data_acv                           367                       # DTB access violations
system.cpu.dtb.data_accesses                  1020784                       # DTB accesses
system.cpu.itb.fetch_hits                     4975134                       # ITB hits
system.cpu.itb.fetch_misses                      5010                       # ITB misses
system.cpu.itb.fetch_acv                          184                       # ITB acv
system.cpu.itb.fetch_accesses                 4980144                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.numCycles                       3882551992                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     6375                       # number of quiesce instructions executed
system.cpu.kern.inst.hwrei                     212050                       # number of hwrei instructions executed
system.cpu.kern.ipl_count::0                    74912     40.88%     40.88% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21                     131      0.07%     40.96% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22                    1935      1.06%     42.01% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31                  106253     57.99%    100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total               183231                       # number of times we switched to this ipl
system.cpu.kern.ipl_good::0                     73545     49.31%     49.31% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22                     1935      1.30%     50.69% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31                    73545     49.31%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total                149156                       # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0             1860509936500     95.84%     95.84% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21                94066500      0.00%     95.84% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22               770529000      0.04%     95.88% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31             79900730000      4.12%    100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total         1941275262000                       # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0                  0.981752                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31                 0.692169                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total              0.814033                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
system.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
system.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
system.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
system.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
system.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
system.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
system.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
system.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
system.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
system.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
system.cpu.kern.syscall::total                    326                       # number of syscalls executed
system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx                  4176      2.16%      2.17% # number of callpals executed
system.cpu.kern.callpal::tbi                       54      0.03%      2.19% # number of callpals executed
system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
system.cpu.kern.callpal::swpipl                176004     91.22%     93.41% # number of callpals executed
system.cpu.kern.callpal::rdps                    6835      3.54%     96.96% # number of callpals executed
system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
system.cpu.kern.callpal::wrusp                      7      0.00%     96.96% # number of callpals executed
system.cpu.kern.callpal::rdusp                      9      0.00%     96.96% # number of callpals executed
system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::rti                     5160      2.67%     99.64% # number of callpals executed
system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
system.cpu.kern.callpal::total                 192955                       # number of callpals executed
system.cpu.kern.mode_switch::kernel              5908                       # number of protection mode switches
system.cpu.kern.mode_switch::user                1739                       # number of protection mode switches
system.cpu.kern.mode_switch::idle                2094                       # number of protection mode switches
system.cpu.kern.mode_good::kernel                1909                      
system.cpu.kern.mode_good::user                  1739                      
system.cpu.kern.mode_good::idle                   170                      
system.cpu.kern.mode_switch_good::kernel     0.323121                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle       0.081184                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total      0.391952                       # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel        48613441500      2.50%      2.50% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user           5603081000      0.29%      2.79% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle         1887058737500     97.21%    100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed
system.cpu.committedInsts                    56182685                       # Number of instructions committed
system.cpu.committedOps                      56182685                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses              52054580                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                 324393                       # Number of float alu accesses
system.cpu.num_func_calls                     1483390                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts      6468674                       # number of instructions that are conditional controls
system.cpu.num_int_insts                     52054580                       # number of integer instructions
system.cpu.num_fp_insts                        324393                       # number of float instructions
system.cpu.num_int_register_reads            71322431                       # number of times the integer registers were read
system.cpu.num_int_register_writes           38520860                       # number of times the integer registers were written
system.cpu.num_fp_register_reads               163609                       # number of times the floating registers were read
system.cpu.num_fp_register_writes              166486                       # number of times the floating registers were written
system.cpu.num_mem_refs                      15473452                       # number of memory refs
system.cpu.num_load_insts                     9101488                       # Number of load instructions
system.cpu.num_store_insts                    6371964                       # Number of store instructions
system.cpu.num_idle_cycles               3583831790.000154                       # Number of idle cycles
system.cpu.num_busy_cycles               298720201.999846                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.076939                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.923061                       # Percentage of idle cycles
system.cpu.Branches                           8422715                       # Number of branches fetched
system.cpu.op_class::No_OpClass               3200634      5.70%      5.70% # Class of executed instruction
system.cpu.op_class::IntAlu                  36230987     64.47%     70.17% # Class of executed instruction
system.cpu.op_class::IntMult                    61043      0.11%     70.28% # Class of executed instruction
system.cpu.op_class::IntDiv                         0      0.00%     70.28% # Class of executed instruction
system.cpu.op_class::FloatAdd                   38085      0.07%     70.35% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     70.35% # Class of executed instruction
system.cpu.op_class::FloatCvt                       0      0.00%     70.35% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     70.35% # Class of executed instruction
system.cpu.op_class::FloatDiv                    3636      0.01%     70.35% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     70.35% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     70.35% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     70.35% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     70.35% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     70.35% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     70.35% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     70.35% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     70.35% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     70.35% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     70.35% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     70.35% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     70.35% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   0      0.00%     70.35% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     70.35% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                   0      0.00%     70.35% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                   0      0.00%     70.35% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     70.35% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc                  0      0.00%     70.35% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     70.35% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     70.35% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     70.35% # Class of executed instruction
system.cpu.op_class::MemRead                  9328618     16.60%     86.95% # Class of executed instruction
system.cpu.op_class::MemWrite                 6378045     11.35%     98.30% # Class of executed instruction
system.cpu.op_class::IprAccess                 953470      1.70%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                   56194518                       # Class of executed instruction
system.cpu.dcache.tags.replacements           1390402                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.973391                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            14048961                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1390914                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             10.100525                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         145150500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.973391                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999948                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999948                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          63150419                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         63150419                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data      7814383                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total         7814383                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      5852265                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        5852265                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       183036                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       183036                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       199260                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       199260                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      13666648                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         13666648                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     13666648                       # number of overall hits
system.cpu.dcache.overall_hits::total        13666648                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1069359                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1069359                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       304327                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       304327                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        17246                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        17246                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1373686                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1373686                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1373686                       # number of overall misses
system.cpu.dcache.overall_misses::total       1373686                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  44772641000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  44772641000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  17635172000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  17635172000                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    232797500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    232797500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  62407813000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  62407813000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  62407813000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  62407813000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data      8883742                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total      8883742                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      6156592                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6156592                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200282                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       200282                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       199260                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       199260                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     15040334                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     15040334                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     15040334                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     15040334                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120373                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.120373                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049431                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.049431                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086109                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086109                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.091333                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.091333                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.091333                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.091333                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41868.671793                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 41868.671793                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57948.101877                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 57948.101877                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13498.637365                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13498.637365                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45430.915799                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 45430.915799                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 45430.915799                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 45430.915799                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks       834944                       # number of writebacks
system.cpu.dcache.writebacks::total            834944                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1069359                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1069359                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304327                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       304327                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17246                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        17246                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1373686                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1373686                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1373686                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1373686                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9653                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total         9653                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16583                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        16583                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43703282000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  43703282000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17330845000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  17330845000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    215551500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    215551500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  61034127000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  61034127000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  61034127000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  61034127000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1526978500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1526978500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   1526978500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   1526978500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120373                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120373                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049431                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049431                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086109                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086109                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091333                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.091333                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091333                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.091333                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40868.671793                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40868.671793                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56948.101877                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56948.101877                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12498.637365                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12498.637365                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44430.915799                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 44430.915799                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44430.915799                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 44430.915799                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220343.217893                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220343.217893                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92080.956401                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92080.956401                       # average overall mshr uncacheable latency
system.cpu.icache.tags.replacements            928931                       # number of replacements
system.cpu.icache.tags.tagsinuse           506.355616                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            55264917                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            929442                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             59.460318                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       58592056500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   506.355616                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.988976                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.988976                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          438                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          57124121                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         57124121                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     55264917                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        55264917                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      55264917                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         55264917                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     55264917                       # number of overall hits
system.cpu.icache.overall_hits::total        55264917                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       929602                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        929602                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       929602                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         929602                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       929602                       # number of overall misses
system.cpu.icache.overall_misses::total        929602                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  13686117000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  13686117000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  13686117000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  13686117000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  13686117000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  13686117000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     56194519                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     56194519                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     56194519                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     56194519                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     56194519                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     56194519                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016543                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.016543                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.016543                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.016543                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.016543                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.016543                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14722.555459                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14722.555459                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14722.555459                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14722.555459                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14722.555459                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14722.555459                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks       928931                       # number of writebacks
system.cpu.icache.writebacks::total            928931                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       929602                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       929602                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       929602                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       929602                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       929602                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       929602                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12756515000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  12756515000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12756515000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  12756515000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12756515000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  12756515000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016543                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016543                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016543                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.016543                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.016543                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.016543                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13722.555459                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13722.555459                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13722.555459                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13722.555459                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13722.555459                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13722.555459                       # average overall mshr miss latency
system.cpu.l2cache.tags.replacements           336393                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65234.360001                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            3930403                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           401556                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             9.787932                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      10619817000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 55072.820493                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  4686.121272                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  5475.418237                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.840345                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.071505                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.083548                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.995397                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65163                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          178                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          722                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         5220                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3221                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55822                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994308                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         37812972                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        37812972                       # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks       834944                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total       834944                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks       928709                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total       928709                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       187490                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       187490                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       916382                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total       916382                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       814634                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       814634                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst       916382                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1002124                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1918506                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst       916382                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1002124                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1918506                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data           13                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           13                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       116820                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       116820                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        13200                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        13200                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       271971                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       271971                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst        13200                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       388791                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        401991                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        13200                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       388791                       # number of overall misses
system.cpu.l2cache.overall_misses::total       401991                       # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       315000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       315000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  14901349500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  14901349500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1726796000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   1726796000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  33721236500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  33721236500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1726796000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  48622586000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  50349382000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1726796000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  48622586000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  50349382000                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks       834944                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total       834944                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks       928709                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total       928709                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           17                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           17                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       304310                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       304310                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       929582                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total       929582                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1086605                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      1086605                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst       929582                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1390915                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2320497                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       929582                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1390915                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2320497                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.764706                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.764706                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383885                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.383885                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.014200                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.014200                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.250294                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.250294                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014200                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.279522                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.173235                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014200                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.279522                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.173235                       # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 24230.769231                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 24230.769231                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127558.204931                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127558.204931                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130817.878788                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130817.878788                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123988.353538                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123988.353538                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130817.878788                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 125060.986494                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 125250.023010                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130817.878788                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125060.986494                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 125250.023010                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks        74281                       # number of writebacks
system.cpu.l2cache.writebacks::total            74281                       # number of writebacks
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           13                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           13                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       116820                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       116820                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        13200                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        13200                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       271971                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       271971                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        13200                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       388791                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       401991                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        13200                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       388791                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       401991                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9653                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9653                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16583                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16583                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       893500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       893500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  13733149500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  13733149500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1594796000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1594796000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  31001526500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  31001526500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1594796000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  44734676000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  46329472000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1594796000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  44734676000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  46329472000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1440322500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1440322500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   1440322500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   1440322500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.764706                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.764706                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383885                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383885                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.014200                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.014200                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.250294                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.250294                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014200                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.279522                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.173235                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014200                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.279522                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.173235                       # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68730.769231                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68730.769231                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117558.204931                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117558.204931                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120817.878788                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120817.878788                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113988.353538                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113988.353538                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120817.878788                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115060.986494                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115250.023010                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120817.878788                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115060.986494                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115250.023010                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 207838.744589                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 207838.744589                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86855.363927                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 86855.363927                       # average overall mshr uncacheable latency
system.cpu.toL2Bus.snoop_filter.tot_requests      4639867                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      2319499                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1502                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         1136                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1136                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadReq           6930                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2023294                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq          9653                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp         9653                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty       950745                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean       928931                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       817743                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           17                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           17                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       304310                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       304310                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq       929602                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      1086778                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2788115                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4205589                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           6993704                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    118944832                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    142509612                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          261454444                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      419988                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      2756928                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.001015                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.031847                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            2754129     99.90%     99.90% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1               2799      0.10%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        2756928                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     4096926500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       293383                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1394403000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2098137500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
system.iobus.trans_dist::WriteReq               51205                       # Transaction distribution
system.iobus.trans_dist::WriteResp              51205                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5162                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1006                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        33166                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  116616                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20648                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2717                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total        44588                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2706196                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              5340500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               759000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 9500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                10000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy              174000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            15817500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy             1891500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             6038000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy               82500                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           215662167                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            23513000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                41685                       # number of replacements
system.iocache.tags.tagsinuse                1.339384                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1774106669000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     1.339384                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.083712                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.083712                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
system.iocache.tags.data_accesses              375525                       # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
system.iocache.overall_misses::total            41725                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21742883                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21742883                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::tsunami.ide   5244713284                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   5244713284                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide   5266456167                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   5266456167                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide   5266456167                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   5266456167                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125681.404624                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 125681.404624                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126220.477570                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 126220.477570                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 126218.242469                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 126218.242469                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 126218.242469                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 126218.242469                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs            29                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    14.500000                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           41512                       # number of writebacks
system.iocache.writebacks::total                41512                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13092883                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     13092883                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3165314984                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   3165314984                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide   3178407867                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   3178407867                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide   3178407867                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   3178407867                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75681.404624                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 75681.404624                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76177.199268                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76177.199268                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76175.143607                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 76175.143607                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76175.143607                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76175.143607                       # average overall mshr miss latency
system.membus.trans_dist::ReadReq                6930                       # Transaction distribution
system.membus.trans_dist::ReadResp             292274                       # Transaction distribution
system.membus.trans_dist::WriteReq               9653                       # Transaction distribution
system.membus.trans_dist::WriteResp              9653                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       115793                       # Transaction distribution
system.membus.trans_dist::CleanEvict           261560                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              150                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::ReadExReq            116683                       # Transaction distribution
system.membus.trans_dist::ReadExResp           116683                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        285344                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33166                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1139255                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1172421                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83425                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        83425                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1255846                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44588                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30455296                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30499884                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2657728                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2657728                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                33157612                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              431                       # Total snoops (count)
system.membus.snoop_fanout::samples            837673                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  837673    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              837673                       # Request fanout histogram
system.membus.reqLayer0.occupancy            30122500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy          1287200967                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer1.occupancy         2143013000                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy             887117                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped

---------- End Simulation Statistics   ----------