path: root/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.919447                       # Number of seconds simulated
sim_ticks                                1919446558000                       # Number of ticks simulated
final_tick                               1919446558000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 885398                       # Simulator instruction rate (inst/s)
host_op_rate                                   885398                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            30291378157                       # Simulator tick rate (ticks/s)
host_mem_usage                                 344696                       # Number of bytes of host memory used
host_seconds                                    63.37                       # Real time elapsed on the host
sim_insts                                    56104177                       # Number of instructions simulated
sim_ops                                      56104177                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            850752                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24858240                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2652352                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28361344                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       850752                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          850752                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7404032                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7404032                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst              13293                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             388410                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41443                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                443146                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          115688                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               115688                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               443228                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             12950733                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1381832                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                14775792                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          443228                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             443228                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3857379                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3857379                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3857379                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              443228                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            12950733                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1381832                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               18633171                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        443146                       # Number of read requests accepted
system.physmem.writeReqs                       115688                       # Number of write requests accepted
system.physmem.readBursts                      443146                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     115688                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 28353856                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7488                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7402304                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  28361344                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7404032                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      117                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs            130                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               27768                       # Per bank write bursts
system.physmem.perBankRdBursts::1               28019                       # Per bank write bursts
system.physmem.perBankRdBursts::2               28336                       # Per bank write bursts
system.physmem.perBankRdBursts::3               28020                       # Per bank write bursts
system.physmem.perBankRdBursts::4               27518                       # Per bank write bursts
system.physmem.perBankRdBursts::5               27546                       # Per bank write bursts
system.physmem.perBankRdBursts::6               26737                       # Per bank write bursts
system.physmem.perBankRdBursts::7               26852                       # Per bank write bursts
system.physmem.perBankRdBursts::8               27860                       # Per bank write bursts
system.physmem.perBankRdBursts::9               27104                       # Per bank write bursts
system.physmem.perBankRdBursts::10              27841                       # Per bank write bursts
system.physmem.perBankRdBursts::11              27413                       # Per bank write bursts
system.physmem.perBankRdBursts::12              27378                       # Per bank write bursts
system.physmem.perBankRdBursts::13              28201                       # Per bank write bursts
system.physmem.perBankRdBursts::14              28236                       # Per bank write bursts
system.physmem.perBankRdBursts::15              28200                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7550                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7529                       # Per bank write bursts
system.physmem.perBankWrBursts::2                7869                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7540                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7115                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6983                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6321                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6313                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7293                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6538                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7205                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6861                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6964                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7821                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7979                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7780                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          11                       # Number of times write queue was full causing retry
system.physmem.totGap                    1919434637000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  443146                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 115688                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    401962                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      1642                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      2685                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      1248                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      1966                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      4407                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      3974                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      3974                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      2507                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      2187                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     2134                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     2102                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1622                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1616                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     1907                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     1876                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                     2136                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                     1224                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      966                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      883                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       11                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4562                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4579                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4593                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4592                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     4608                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     4699                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     4858                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     4946                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5128                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5346                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5326                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     5448                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     5540                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     5685                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5621                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5715                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      897                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      915                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      934                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      861                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      945                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      959                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1033                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      949                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     1139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     1162                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     1146                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     1232                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     1390                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     1625                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     1897                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     2098                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                     1909                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                     1878                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                     1683                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                     1684                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                     1800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                     1629                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      867                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      418                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      235                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      155                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       41                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       26                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       18                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       18                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        66429                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      538.261302                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     328.855989                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     417.099114                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          14887     22.41%     22.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        11472     17.27%     39.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         4684      7.05%     46.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3132      4.71%     51.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         3072      4.62%     56.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1874      2.82%     58.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1342      2.02%     60.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1444      2.17%     63.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        24522     36.91%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          66429                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6775                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        65.389077                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean       16.529238                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     2564.130292                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191           6772     99.96%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151            1      0.01%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6775                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6775                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.071734                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.848509                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        3.695111                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               5062     74.72%     74.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                127      1.87%     76.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18               1207     17.82%     94.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                 25      0.37%     94.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                 12      0.18%     94.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 16      0.24%     95.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 18      0.27%     95.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 98      1.45%     96.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 22      0.32%     97.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                 41      0.61%     97.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                 20      0.30%     98.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                  8      0.12%     98.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                  7      0.10%     98.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29                  8      0.12%     98.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30                  7      0.10%     98.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31                 15      0.22%     98.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32                  9      0.13%     98.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::33                  1      0.01%     98.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34                  1      0.01%     98.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::35                  1      0.01%     98.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::37                  1      0.01%     98.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::38                  1      0.01%     99.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::39                  4      0.06%     99.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40                  9      0.13%     99.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::41                  8      0.12%     99.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42                  2      0.03%     99.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::43                  2      0.03%     99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44                  2      0.03%     99.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::45                  1      0.01%     99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::46                  1      0.01%     99.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::47                  8      0.12%     99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48                  7      0.10%     99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::49                  1      0.01%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::50                  2      0.03%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::51                  2      0.03%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52                  1      0.01%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::54                  1      0.01%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56                  7      0.10%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::57                  9      0.13%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::59                  1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6775                       # Writes before turning the bus around for reads
system.physmem.totQLat                     7315796250                       # Total ticks spent queuing
system.physmem.totMemAccLat               15622590000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2215145000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       16513.13                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  35263.13                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          14.77                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.86                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       14.78                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.86                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.12                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.40                       # Average write queue length when enqueuing
system.physmem.readRowHits                     398273                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     93988                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   89.90                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  81.24                       # Row buffer hit rate for writes
system.physmem.avgGap                      3434713.42                       # Average gap between requests
system.physmem.pageHitRate                      88.11                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     1800016178000                       # Time in different power states
system.physmem.memoryStateTime::REF       64094420000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       55332653250                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.membus.throughput                     18674823                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              292356                       # Transaction distribution
system.membus.trans_dist::ReadResp             292356                       # Transaction distribution
system.membus.trans_dist::WriteReq               9649                       # Transaction distribution
system.membus.trans_dist::WriteResp              9649                       # Transaction distribution
system.membus.trans_dist::Writeback            115688                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              132                       # Transaction distribution
system.membus.trans_dist::UpgradeResp             132                       # Transaction distribution
system.membus.trans_dist::ReadExReq            158273                       # Transaction distribution
system.membus.trans_dist::ReadExResp           158273                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33158                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       878115                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total       911273                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124680                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       124680                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1035953                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44556                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30456256                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     30500812                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5309120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total      5309120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            35809932                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               35809932                       # Total data (bytes)
system.membus.snoop_data_through_bus            35392                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy            32376000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy          1491996000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer1.occupancy         3751677600                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy          376660500                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.iocache.tags.replacements                41685                       # number of replacements
system.iocache.tags.tagsinuse                1.344872                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1753525004000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     1.344872                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.084054                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.084054                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
system.iocache.tags.data_accesses              375525                       # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
system.iocache.overall_misses::total            41725                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21253133                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21253133                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide  12447285431                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  12447285431                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide  12468538564                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  12468538564                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide  12468538564                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  12468538564                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122850.479769                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 122850.479769                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299559.237365                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 299559.237365                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 298826.568340                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 298826.568340                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 298826.568340                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 298826.568340                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        365803                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                28265                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    12.941907                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41512                       # number of writebacks
system.iocache.writebacks::total                41512                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12255133                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     12255133                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  10284312431                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total  10284312431                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide  10296567564                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total  10296567564                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide  10296567564                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total  10296567564                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70838.919075                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70838.919075                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247504.631089                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 247504.631089                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246772.140539                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 246772.140539                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246772.140539                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 246772.140539                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                      9052923                       # DTB read hits
system.cpu.dtb.read_misses                      10354                       # DTB read misses
system.cpu.dtb.read_acv                           210                       # DTB read access violations
system.cpu.dtb.read_accesses                   728911                       # DTB read accesses
system.cpu.dtb.write_hits                     6349403                       # DTB write hits
system.cpu.dtb.write_misses                      1143                       # DTB write misses
system.cpu.dtb.write_acv                          157                       # DTB write access violations
system.cpu.dtb.write_accesses                  291932                       # DTB write accesses
system.cpu.dtb.data_hits                     15402326                       # DTB hits
system.cpu.dtb.data_misses                      11497                       # DTB misses
system.cpu.dtb.data_acv                           367                       # DTB access violations
system.cpu.dtb.data_accesses                  1020843                       # DTB accesses
system.cpu.itb.fetch_hits                     4974965                       # ITB hits
system.cpu.itb.fetch_misses                      5010                       # ITB misses
system.cpu.itb.fetch_acv                          184                       # ITB acv
system.cpu.itb.fetch_accesses                 4979975                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.numCycles                       3838893116                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                    56104177                       # Number of instructions committed
system.cpu.committedOps                      56104177                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses              51979169                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                 324594                       # Number of float alu accesses
system.cpu.num_func_calls                     1481286                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts      6461218                       # number of instructions that are conditional controls
system.cpu.num_int_insts                     51979169                       # number of integer instructions
system.cpu.num_fp_insts                        324594                       # number of float instructions
system.cpu.num_int_register_reads            71209746                       # number of times the integer registers were read
system.cpu.num_int_register_writes           38460532                       # number of times the integer registers were written
system.cpu.num_fp_register_reads               163708                       # number of times the floating registers were read
system.cpu.num_fp_register_writes              166588                       # number of times the floating registers were written
system.cpu.num_mem_refs                      15454993                       # number of memory refs
system.cpu.num_load_insts                     9089820                       # Number of load instructions
system.cpu.num_store_insts                    6365173                       # Number of store instructions
system.cpu.num_idle_cycles               3587243859.498131                       # Number of idle cycles
system.cpu.num_busy_cycles               251649256.501869                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.065553                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.934447                       # Percentage of idle cycles
system.cpu.Branches                           8413035                       # Number of branches fetched
system.cpu.op_class::No_OpClass               3197761      5.70%      5.70% # Class of executed instruction
system.cpu.op_class::IntAlu                  36186344     64.48%     70.18% # Class of executed instruction
system.cpu.op_class::IntMult                    61011      0.11%     70.29% # Class of executed instruction
system.cpu.op_class::IntDiv                         0      0.00%     70.29% # Class of executed instruction
system.cpu.op_class::FloatAdd                   25613      0.05%     70.34% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::FloatCvt                       0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::FloatDiv                    3636      0.01%     70.34% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                   0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                   0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc                  0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::MemRead                  9316905     16.60%     86.95% # Class of executed instruction
system.cpu.op_class::MemWrite                 6371245     11.35%     98.30% # Class of executed instruction
system.cpu.op_class::IprAccess                 953526      1.70%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                   56116041                       # Class of executed instruction
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     6378                       # number of quiesce instructions executed
system.cpu.kern.inst.hwrei                     212017                       # number of hwrei instructions executed
system.cpu.kern.ipl_count::0                    74895     40.89%     40.89% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21                     131      0.07%     40.96% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22                    1931      1.05%     42.01% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31                  106210     57.99%    100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total               183167                       # number of times we switched to this ipl
system.cpu.kern.ipl_good::0                     73528     49.31%     49.31% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22                     1931      1.29%     50.69% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31                    73528     49.31%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total                149118                       # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0             1857252195000     96.76%     96.76% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21                91387500      0.00%     96.76% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22               737178000      0.04%     96.80% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31             61365063500      3.20%    100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total         1919445824000                       # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0                  0.981748                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31                 0.692289                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total              0.814110                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
system.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
system.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
system.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
system.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
system.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
system.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
system.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
system.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
system.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
system.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
system.cpu.kern.syscall::total                    326                       # number of syscalls executed
system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx                  4179      2.17%      2.17% # number of callpals executed
system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
system.cpu.kern.callpal::swpipl                175948     91.21%     93.41% # number of callpals executed
system.cpu.kern.callpal::rdps                    6832      3.54%     96.96% # number of callpals executed
system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
system.cpu.kern.callpal::wrusp                      7      0.00%     96.96% # number of callpals executed
system.cpu.kern.callpal::rdusp                      9      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::rti                     5156      2.67%     99.64% # number of callpals executed
system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
system.cpu.kern.callpal::total                 192895                       # number of callpals executed
system.cpu.kern.mode_switch::kernel              5904                       # number of protection mode switches
system.cpu.kern.mode_switch::user                1741                       # number of protection mode switches
system.cpu.kern.mode_switch::idle                2097                       # number of protection mode switches
system.cpu.kern.mode_good::kernel                1912                      
system.cpu.kern.mode_good::user                  1741                      
system.cpu.kern.mode_good::idle                   171                      
system.cpu.kern.mode_switch_good::kernel     0.323848                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle       0.081545                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total      0.392527                       # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel        46108525500      2.40%      2.40% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user           5189217000      0.27%      2.67% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle         1868148079500     97.33%    100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context                     4180                       # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.iobus.throughput                       1409867                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
system.iobus.trans_dist::WriteReq               51201                       # Transaction distribution
system.iobus.trans_dist::WriteResp              51201                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5154                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        33158                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  116608                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        20616                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total        44556                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total              2706164                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                 2706164                       # Total data (bytes)
system.iobus.reqLayer0.occupancy              4765000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               353000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            13484000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy             1887000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy               76000                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer29.occupancy           380199064                       # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            23509000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            43233500                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.cpu.icache.tags.replacements            927875                       # number of replacements
system.cpu.icache.tags.tagsinuse           508.303976                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            55187496                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            928386                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             59.444559                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       39855277250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   508.303976                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.992781                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.992781                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          438                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          57044588                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         57044588                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     55187496                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        55187496                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      55187496                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         55187496                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     55187496                       # number of overall hits
system.cpu.icache.overall_hits::total        55187496                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       928546                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        928546                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       928546                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         928546                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       928546                       # number of overall misses
system.cpu.icache.overall_misses::total        928546                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  12910342260                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  12910342260                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  12910342260                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  12910342260                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  12910342260                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  12910342260                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     56116042                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     56116042                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     56116042                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     56116042                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     56116042                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     56116042                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016547                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.016547                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.016547                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.016547                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.016547                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.016547                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13903.826262                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13903.826262                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13903.826262                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13903.826262                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13903.826262                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13903.826262                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       928546                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       928546                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       928546                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       928546                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       928546                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       928546                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11048086740                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  11048086740                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11048086740                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  11048086740                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11048086740                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  11048086740                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016547                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016547                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016547                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.016547                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.016547                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.016547                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11898.265396                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11898.265396                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11898.265396                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11898.265396                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11898.265396                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11898.265396                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           336232                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65296.289611                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            2446119                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           401393                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             6.094075                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle       6784872750                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 55555.447127                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  4766.385283                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  4974.457201                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.847709                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.072729                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.075904                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.996342                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65161                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          177                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1074                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         4875                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3257                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55778                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994278                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         25936539                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        25936539                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst       915233                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       814520                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1729753                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       834591                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       834591                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       187383                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       187383                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst       915233                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1001903                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1917136                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst       915233                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1001903                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1917136                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst        13293                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       271960                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       285253                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data           13                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           13                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       116840                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       116840                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst        13293                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       388800                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        402093                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        13293                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       388800                       # number of overall misses
system.cpu.l2cache.overall_misses::total       402093                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    967190740                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  17699357246                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  18666547986                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       190498                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       190498                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8068029125                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   8068029125                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    967190740                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  25767386371                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  26734577111                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    967190740                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  25767386371                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  26734577111                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst       928526                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1086480                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2015006                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       834591                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       834591                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           17                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           17                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       304223                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       304223                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst       928526                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1390703                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2319229                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       928526                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1390703                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2319229                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014316                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.250313                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.141564                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.764706                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.764706                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.384060                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.384060                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014316                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.279571                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.173374                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014316                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.279571                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.173374                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72759.402693                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65080.737042                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 65438.568520                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14653.692308                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14653.692308                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69051.943898                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69051.943898                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72759.402693                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66274.141901                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 66488.541484                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72759.402693                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66274.141901                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 66488.541484                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        74176                       # number of writebacks
system.cpu.l2cache.writebacks::total            74176                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        13293                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       271960                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       285253                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           13                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           13                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       116840                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       116840                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        13293                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       388800                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       402093                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        13293                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       388800                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       402093                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    800656260                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  14299493254                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  15100149514                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       230011                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       230011                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6607242375                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6607242375                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    800656260                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20906735629                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  21707391889                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    800656260                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20906735629                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  21707391889                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1334145500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1334145500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1895432500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1895432500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3229578000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3229578000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014316                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.250313                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.141564                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.764706                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.764706                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.384060                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.384060                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014316                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.279571                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.173374                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014316                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.279571                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.173374                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60231.419544                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52579.398640                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52935.988452                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56549.489687                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56549.489687                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60231.419544                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53772.468182                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53985.997988                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60231.419544                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53772.468182                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53985.997988                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           1390190                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.978877                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            14030691                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1390702                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             10.088927                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         107775250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.978877                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999959                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999959                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          257                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          63076279                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         63076279                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data      7802806                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total         7802806                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      5845593                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        5845593                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       183040                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       183040                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       199235                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       199235                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      13648399                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         13648399                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     13648399                       # number of overall hits
system.cpu.dcache.overall_hits::total        13648399                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1069264                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1069264                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       304240                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       304240                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        17216                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        17216                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1373504                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1373504                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1373504                       # number of overall misses
system.cpu.dcache.overall_misses::total       1373504                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  29001409504                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  29001409504                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  10907701386                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  10907701386                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    228213250                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    228213250                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  39909110890                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  39909110890                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  39909110890                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  39909110890                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data      8872070                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total      8872070                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      6149833                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6149833                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200256                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       200256                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       199235                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       199235                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     15021903                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     15021903                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     15021903                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     15021903                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120520                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.120520                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049471                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.049471                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085970                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.085970                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.091433                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.091433                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.091433                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.091433                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27122.777447                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 27122.777447                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35852.292223                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35852.292223                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13255.881157                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13255.881157                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 29056.421306                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 29056.421306                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 29056.421306                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 29056.421306                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       834591                       # number of writebacks
system.cpu.dcache.writebacks::total            834591                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1069264                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1069264                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304240                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       304240                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17216                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        17216                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1373504                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1373504                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1373504                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1373504                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  26737269496                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  26737269496                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10246531614                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  10246531614                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    193767750                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    193767750                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  36983801110                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  36983801110                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  36983801110                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  36983801110                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1424235500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1424235500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2011220500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2011220500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3435456000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   3435456000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120520                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120520                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049471                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049471                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.085970                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.085970                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091433                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.091433                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091433                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.091433                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25005.302242                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25005.302242                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33679.107330                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33679.107330                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11255.097003                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11255.097003                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26926.606046                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26926.606046                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26926.606046                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26926.606046                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput               105186760                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        2022129                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2022112                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq          9649                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp         9649                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       834591                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           17                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           17                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       345775                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       304224                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1857072                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3649346                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           5506418                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     59425664                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    142473420                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      201899084                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         201889036                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus        11328                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     2424633500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       235500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1395400760                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2186975140                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)

---------- End Simulation Statistics   ----------