path: root/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.920428                       # Number of seconds simulated
sim_ticks                                1920427877000                       # Number of ticks simulated
final_tick                               1920427877000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 694902                       # Simulator instruction rate (inst/s)
host_op_rate                                   694902                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            23785763794                       # Simulator tick rate (ticks/s)
host_mem_usage                                 317148                       # Number of bytes of host memory used
host_seconds                                    80.74                       # Real time elapsed on the host
sim_insts                                    56105324                       # Number of instructions simulated
sim_ops                                      56105324                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            850752                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24858304                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             25710016                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       850752                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          850752                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7404096                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7404096                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst              13293                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             388411                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                401719                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          115689                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               115689                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               443001                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             12944149                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide               500                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                13387650                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          443001                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             443001                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3855441                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3855441                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3855441                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              443001                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            12944149                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide              500                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               17243091                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        401719                       # Number of read requests accepted
system.physmem.writeReqs                       157241                       # Number of write requests accepted
system.physmem.readBursts                      401719                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     157241                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 25703424                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      6592                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   9932992                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  25710016                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               10063424                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      103                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2011                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs            130                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               25160                       # Per bank write bursts
system.physmem.perBankRdBursts::1               25539                       # Per bank write bursts
system.physmem.perBankRdBursts::2               25602                       # Per bank write bursts
system.physmem.perBankRdBursts::3               25522                       # Per bank write bursts
system.physmem.perBankRdBursts::4               24974                       # Per bank write bursts
system.physmem.perBankRdBursts::5               24970                       # Per bank write bursts
system.physmem.perBankRdBursts::6               24210                       # Per bank write bursts
system.physmem.perBankRdBursts::7               24489                       # Per bank write bursts
system.physmem.perBankRdBursts::8               25140                       # Per bank write bursts
system.physmem.perBankRdBursts::9               24800                       # Per bank write bursts
system.physmem.perBankRdBursts::10              25361                       # Per bank write bursts
system.physmem.perBankRdBursts::11              24836                       # Per bank write bursts
system.physmem.perBankRdBursts::12              24395                       # Per bank write bursts
system.physmem.perBankRdBursts::13              25368                       # Per bank write bursts
system.physmem.perBankRdBursts::14              25772                       # Per bank write bursts
system.physmem.perBankRdBursts::15              25478                       # Per bank write bursts
system.physmem.perBankWrBursts::0               10040                       # Per bank write bursts
system.physmem.perBankWrBursts::1                9905                       # Per bank write bursts
system.physmem.perBankWrBursts::2               10447                       # Per bank write bursts
system.physmem.perBankWrBursts::3                9982                       # Per bank write bursts
system.physmem.perBankWrBursts::4                9551                       # Per bank write bursts
system.physmem.perBankWrBursts::5                9392                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8805                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8555                       # Per bank write bursts
system.physmem.perBankWrBursts::8                9942                       # Per bank write bursts
system.physmem.perBankWrBursts::9                8777                       # Per bank write bursts
system.physmem.perBankWrBursts::10               9524                       # Per bank write bursts
system.physmem.perBankWrBursts::11               9288                       # Per bank write bursts
system.physmem.perBankWrBursts::12               9847                       # Per bank write bursts
system.physmem.perBankWrBursts::13              10608                       # Per bank write bursts
system.physmem.perBankWrBursts::14              10278                       # Per bank write bursts
system.physmem.perBankWrBursts::15              10262                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    1920415956000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  401719                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 157241                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    401602                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2241                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     4297                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     7960                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     9080                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     9749                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    10574                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    11119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    12096                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    11614                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    11639                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    10464                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9678                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8171                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7710                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     6526                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6096                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5950                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5885                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      334                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      334                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      336                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      291                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      274                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      265                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      251                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      211                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      210                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      205                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      194                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      177                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      146                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      133                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      114                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       77                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       58                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       42                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       26                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       24                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        66429                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      536.458715                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     326.725513                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     417.454187                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          15065     22.68%     22.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        11458     17.25%     39.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         4677      7.04%     46.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3146      4.74%     51.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         3014      4.54%     56.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1853      2.79%     59.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1319      1.99%     61.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1472      2.22%     63.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        24425     36.77%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          66429                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5535                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        72.556098                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     2836.858046                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191           5532     99.95%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5535                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5535                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        28.040289                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       21.079799                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       34.913440                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23            4499     81.28%     81.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31             176      3.18%     84.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39             297      5.37%     89.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47              50      0.90%     90.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55              97      1.75%     92.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63              48      0.87%     93.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71              11      0.20%     93.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79               7      0.13%     93.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87              21      0.38%     94.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95               7      0.13%     94.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103             14      0.25%     94.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111             6      0.11%     94.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119            14      0.25%     94.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127             3      0.05%     94.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135            11      0.20%     95.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143            48      0.87%     95.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151            16      0.29%     96.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159            19      0.34%     96.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167            91      1.64%     98.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175            36      0.65%     98.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183             6      0.11%     98.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191            14      0.25%     99.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199            14      0.25%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-207             5      0.09%     99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215             9      0.16%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-223             3      0.05%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231             5      0.09%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::232-239             1      0.02%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-247             3      0.05%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::248-255             2      0.04%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263             1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::264-271             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5535                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2119831750                       # Total ticks spent queuing
system.physmem.totMemAccLat                9650131750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2008080000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        5278.26                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  24028.26                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          13.38                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           5.17                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       13.39                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        5.24                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.10                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.04                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.55                       # Average write queue length when enqueuing
system.physmem.readRowHits                     359880                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    130510                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   89.61                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  84.08                       # Row buffer hit rate for writes
system.physmem.avgGap                      3435694.78                       # Average gap between requests
system.physmem.pageHitRate                      88.07                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     1801057353000                       # Time in different power states
system.physmem.memoryStateTime::REF       64127180000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       55239785750                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                 245964600                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                 256238640                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                 134206875                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                 139812750                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0               1563634800                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1               1568970000                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0               496866960                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1               508848480                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0          125432764080                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1          125432764080                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0           64118860245                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1           64485707400                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          1096009968750                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          1095688173000                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            1288002266310                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            1288080514350                       # Total energy per rank (pJ)
system.physmem.averagePower::0             670.686297                       # Core power per rank (mW)
system.physmem.averagePower::1             670.727042                       # Core power per rank (mW)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                      9053154                       # DTB read hits
system.cpu.dtb.read_misses                      10325                       # DTB read misses
system.cpu.dtb.read_acv                           210                       # DTB read access violations
system.cpu.dtb.read_accesses                   728854                       # DTB read accesses
system.cpu.dtb.write_hits                     6349573                       # DTB write hits
system.cpu.dtb.write_misses                      1142                       # DTB write misses
system.cpu.dtb.write_acv                          157                       # DTB write access violations
system.cpu.dtb.write_accesses                  291931                       # DTB write accesses
system.cpu.dtb.data_hits                     15402727                       # DTB hits
system.cpu.dtb.data_misses                      11467                       # DTB misses
system.cpu.dtb.data_acv                           367                       # DTB access violations
system.cpu.dtb.data_accesses                  1020785                       # DTB accesses
system.cpu.itb.fetch_hits                     4974627                       # ITB hits
system.cpu.itb.fetch_misses                      5010                       # ITB misses
system.cpu.itb.fetch_acv                          184                       # ITB acv
system.cpu.itb.fetch_accesses                 4979637                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.numCycles                       3840855754                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                    56105324                       # Number of instructions committed
system.cpu.committedOps                      56105324                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses              51980283                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                 324527                       # Number of float alu accesses
system.cpu.num_func_calls                     1481352                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts      6461346                       # number of instructions that are conditional controls
system.cpu.num_int_insts                     51980283                       # number of integer instructions
system.cpu.num_fp_insts                        324527                       # number of float instructions
system.cpu.num_int_register_reads            71211532                       # number of times the integer registers were read
system.cpu.num_int_register_writes           38461399                       # number of times the integer registers were written
system.cpu.num_fp_register_reads               163675                       # number of times the floating registers were read
system.cpu.num_fp_register_writes              166554                       # number of times the floating registers were written
system.cpu.num_mem_refs                      15455353                       # number of memory refs
system.cpu.num_load_insts                     9090013                       # Number of load instructions
system.cpu.num_store_insts                    6365340                       # Number of store instructions
system.cpu.num_idle_cycles               3589191785.998131                       # Number of idle cycles
system.cpu.num_busy_cycles               251663968.001869                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.065523                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.934477                       # Percentage of idle cycles
system.cpu.Branches                           8413247                       # Number of branches fetched
system.cpu.op_class::No_OpClass               3197750      5.70%      5.70% # Class of executed instruction
system.cpu.op_class::IntAlu                  36174854     64.46%     70.16% # Class of executed instruction
system.cpu.op_class::IntMult                    61015      0.11%     70.27% # Class of executed instruction
system.cpu.op_class::IntDiv                         0      0.00%     70.27% # Class of executed instruction
system.cpu.op_class::FloatAdd                   38089      0.07%     70.34% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::FloatCvt                       0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::FloatDiv                    3636      0.01%     70.34% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                   0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                   0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc                  0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::MemRead                  9317103     16.60%     86.95% # Class of executed instruction
system.cpu.op_class::MemWrite                 6371414     11.35%     98.30% # Class of executed instruction
system.cpu.op_class::IprAccess                 953297      1.70%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                   56117158                       # Class of executed instruction
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     6382                       # number of quiesce instructions executed
system.cpu.kern.inst.hwrei                     212003                       # number of hwrei instructions executed
system.cpu.kern.ipl_count::0                    74898     40.89%     40.89% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21                     131      0.07%     40.96% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22                    1932      1.05%     42.01% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31                  106222     57.99%    100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total               183183                       # number of times we switched to this ipl
system.cpu.kern.ipl_good::0                     73531     49.31%     49.31% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22                     1932      1.30%     50.69% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31                    73531     49.31%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total                149125                       # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0             1858233349500     96.76%     96.76% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21                91228000      0.00%     96.77% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22               737074000      0.04%     96.80% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31             61365491500      3.20%    100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total         1920427143000                       # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0                  0.981749                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31                 0.692239                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total              0.814077                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
system.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
system.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
system.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
system.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
system.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
system.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
system.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
system.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
system.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
system.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
system.cpu.kern.syscall::total                    326                       # number of syscalls executed
system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx                  4178      2.17%      2.17% # number of callpals executed
system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
system.cpu.kern.callpal::swpipl                175962     91.21%     93.41% # number of callpals executed
system.cpu.kern.callpal::rdps                    6833      3.54%     96.96% # number of callpals executed
system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
system.cpu.kern.callpal::wrusp                      7      0.00%     96.96% # number of callpals executed
system.cpu.kern.callpal::rdusp                      9      0.00%     96.96% # number of callpals executed
system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::rti                     5157      2.67%     99.64% # number of callpals executed
system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
system.cpu.kern.callpal::total                 192910                       # number of callpals executed
system.cpu.kern.mode_switch::kernel              5901                       # number of protection mode switches
system.cpu.kern.mode_switch::user                1743                       # number of protection mode switches
system.cpu.kern.mode_switch::idle                2100                       # number of protection mode switches
system.cpu.kern.mode_good::kernel                1914                      
system.cpu.kern.mode_good::user                  1743                      
system.cpu.kern.mode_good::idle                   171                      
system.cpu.kern.mode_switch_good::kernel     0.324352                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle       0.081429                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total      0.392857                       # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel        46106755000      2.40%      2.40% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user           5190620000      0.27%      2.67% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle         1869129766000     97.33%    100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context                     4179                       # number of times the context was actually changed
system.cpu.dcache.tags.replacements           1390139                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.978885                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            14031130                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1390651                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             10.089613                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         107775250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.978885                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999959                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999959                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          257                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          63077780                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         63077780                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data      7803062                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total         7803062                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      5845783                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        5845783                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       183030                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       183030                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       199238                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       199238                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      13648845                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         13648845                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     13648845                       # number of overall hits
system.cpu.dcache.overall_hits::total        13648845                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1069228                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1069228                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       304213                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       304213                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        17228                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        17228                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1373441                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1373441                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1373441                       # number of overall misses
system.cpu.dcache.overall_misses::total       1373441                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  29002641750                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  29002641750                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  10915376130                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  10915376130                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    228802500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    228802500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  39918017880                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  39918017880                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  39918017880                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  39918017880                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data      8872290                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total      8872290                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      6149996                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6149996                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200258                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       200258                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       199238                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       199238                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     15022286                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     15022286                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     15022286                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     15022286                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120513                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.120513                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049466                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.049466                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086029                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086029                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.091427                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.091427                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.091427                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.091427                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27124.843111                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 27124.843111                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35880.702435                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35880.702435                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13280.850940                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13280.850940                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 29064.239294                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 29064.239294                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 29064.239294                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 29064.239294                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       834534                       # number of writebacks
system.cpu.dcache.writebacks::total            834534                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1069228                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1069228                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304213                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       304213                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17228                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        17228                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1373441                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1373441                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1373441                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1373441                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  26738553250                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  26738553250                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10254282870                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  10254282870                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    194333500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    194333500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  36992836120                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  36992836120                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  36992836120                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  36992836120                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1424273000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1424273000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2009400000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2009400000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3433673000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   3433673000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120513                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120513                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049466                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049466                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086029                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086029                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091427                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.091427                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091427                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.091427                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25007.344785                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25007.344785                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33707.576172                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33707.576172                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11280.096355                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11280.096355                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26934.419549                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26934.419549                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26934.419549                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26934.419549                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements            927958                       # number of replacements
system.cpu.icache.tags.tagsinuse           508.305941                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            55188530                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            928469                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             59.440358                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       39853785250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   508.305941                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.992785                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.992785                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          438                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          57045788                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         57045788                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     55188530                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        55188530                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      55188530                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         55188530                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     55188530                       # number of overall hits
system.cpu.icache.overall_hits::total        55188530                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       928629                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        928629                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       928629                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         928629                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       928629                       # number of overall misses
system.cpu.icache.overall_misses::total        928629                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  12911718500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  12911718500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  12911718500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  12911718500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  12911718500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  12911718500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     56117159                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     56117159                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     56117159                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     56117159                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     56117159                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     56117159                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016548                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.016548                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.016548                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.016548                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.016548                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.016548                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13904.065563                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13904.065563                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13904.065563                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13904.065563                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13904.065563                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13904.065563                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       928629                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       928629                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       928629                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       928629                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       928629                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       928629                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11049312500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  11049312500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11049312500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  11049312500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11049312500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  11049312500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016548                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016548                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016548                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.016548                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.016548                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.016548                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11898.521907                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11898.521907                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11898.521907                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11898.521907                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11898.521907                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11898.521907                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           336233                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65296.128852                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            2446119                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           401395                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             6.094045                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle       6784872750                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 55552.665832                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  4768.375008                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  4975.088012                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.847666                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.072760                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.075914                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.996340                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65162                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          178                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1074                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         4872                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3259                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55779                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994293                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         25936314                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        25936314                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst       915316                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       814497                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1729813                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       834534                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       834534                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       187354                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       187354                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst       915316                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1001851                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1917167                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst       915316                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1001851                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1917167                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst        13293                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       271959                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       285252                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data           13                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           13                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       116842                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       116842                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst        13293                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       388801                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        402094                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        13293                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       388801                       # number of overall misses
system.cpu.l2cache.overall_misses::total       402094                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    967503500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  17701460750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  18668964250                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       190498                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       190498                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8076097381                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   8076097381                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    967503500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  25777558131                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  26745061631                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    967503500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  25777558131                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  26745061631                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst       928609                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1086456                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2015065                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       834534                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       834534                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           17                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           17                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       304196                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       304196                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst       928609                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1390652                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2319261                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       928609                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1390652                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2319261                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014315                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.250318                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.141560                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.764706                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.764706                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.384101                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.384101                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014315                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.279582                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.173372                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014315                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.279582                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.173372                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72782.930866                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65088.710982                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 65447.268556                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14653.692308                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14653.692308                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69119.814630                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69119.814630                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72782.930866                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66300.133310                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 66514.450927                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72782.930866                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66300.133310                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 66514.450927                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        74177                       # number of writebacks
system.cpu.l2cache.writebacks::total            74177                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        13293                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       271959                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       285252                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           13                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           13                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       116842                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       116842                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        13293                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       388801                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       402094                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        13293                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       388801                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       402094                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    800925500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  14301564750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  15102490250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       230011                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       230011                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6615159119                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6615159119                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    800925500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20916723869                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  21717649369                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    800925500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20916723869                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  21717649369                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1334183000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1334183000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1893600000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1893600000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3227783000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3227783000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014315                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.250318                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.141560                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.764706                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.764706                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.384101                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.384101                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014315                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.279582                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.173372                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014315                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.279582                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.173372                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60251.673813                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52587.208918                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52944.379882                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56616.277700                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56616.277700                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60251.673813                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53798.019730                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54011.373880                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60251.673813                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53798.019730                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54011.373880                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq        2022188                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2022171                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq          9650                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp         9650                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       834534                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           17                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           17                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       304196                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       304196                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1857238                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3649188                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           5506426                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     59430976                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    142466452                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          201897428                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                       41901                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      3195557                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        1.013057                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.113520                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1            3153832     98.69%     98.69% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2              41725      1.31%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        3195557                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     2424565000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       234000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1395517500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2186897880                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
system.iobus.trans_dist::WriteReq               51202                       # Transaction distribution
system.iobus.trans_dist::WriteResp               9650                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5156                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        33160                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  116610                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20624                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total        44564                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2706172                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              4767000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               353000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            13484000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy             1887000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy               76000                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer29.occupancy           406189794                       # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            23510000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            42010500                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                41685                       # number of replacements
system.iocache.tags.tagsinuse                1.352352                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1753525032000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     1.352352                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.084522                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.084522                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
system.iocache.tags.data_accesses              375525                       # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::tsunami.ide        41552                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total        41552                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
system.iocache.overall_misses::total              173                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21133383                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21133383                       # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide  13634918911                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total  13634918911                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide     21133383                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     21133383                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide     21133383                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     21133383                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 122158.283237                       # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328141.098166                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 328141.098166                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 122158.283237                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 122158.283237                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        206323                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                23561                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     8.756971                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41512                       # number of writebacks
system.iocache.writebacks::total                41512                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        41552                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        41552                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide          173                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide          173                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12136383                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     12136383                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide  11474214911                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total  11474214911                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide     12136383                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     12136383                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide     12136383                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     12136383                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276141.098166                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276141.098166                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70152.502890                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 70152.502890                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              292355                       # Transaction distribution
system.membus.trans_dist::ReadResp             292355                       # Transaction distribution
system.membus.trans_dist::WriteReq               9650                       # Transaction distribution
system.membus.trans_dist::WriteResp              9650                       # Transaction distribution
system.membus.trans_dist::Writeback            115689                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              132                       # Transaction distribution
system.membus.trans_dist::UpgradeResp             132                       # Transaction distribution
system.membus.trans_dist::ReadExReq            116723                       # Transaction distribution
system.membus.trans_dist::ReadExResp           116723                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33160                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       878118                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total       911278                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124804                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       124804                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1036082                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44564                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30456384                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30500948                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      5317056                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      5317056                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                35818004                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              431                       # Total snoops (count)
system.membus.snoop_fanout::samples            559521                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  559521    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              559521                       # Request fanout histogram
system.membus.reqLayer0.occupancy            30373000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy          1824623000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer1.occupancy         3751921620                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy           43109500                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped

---------- End Simulation Statistics   ----------