path: root/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.910548                       # Number of seconds simulated
sim_ticks                                1910547559000                       # Number of ticks simulated
final_tick                               1910547559000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1284259                       # Simulator instruction rate (inst/s)
host_op_rate                                  1284258                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            43720523895                       # Simulator tick rate (ticks/s)
host_mem_usage                                 330356                       # Number of bytes of host memory used
host_seconds                                    43.70                       # Real time elapsed on the host
sim_insts                                    56120911                       # Number of instructions simulated
sim_ops                                      56120911                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            850624                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24858368                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2652352                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28361344                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       850624                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          850624                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7404352                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7404352                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst              13291                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             388412                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41443                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                443146                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          115693                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               115693                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               445225                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             13011122                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1388268                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                14844616                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          445225                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             445225                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3875513                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3875513                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3875513                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              445225                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            13011122                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1388268                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               18720129                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        443146                       # Total number of read requests seen
system.physmem.writeReqs                       115693                       # Total number of write requests seen
system.physmem.cpureqs                         561589                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                     28361344                       # Total number of bytes read from memory
system.physmem.bytesWritten                   7404352                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               28361344                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                7404352                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       45                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite                130                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                 27901                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                 27706                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                 27556                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                 27375                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                 27676                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                 27765                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                 27827                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                 27615                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                 28008                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                 27777                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                27792                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                27562                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                27598                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                27733                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                27646                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                27564                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  7483                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  7263                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  7148                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  7032                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  7167                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  7214                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  7312                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  7182                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  7584                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  7357                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 7354                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 7067                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 7154                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 7184                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 7113                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 7079                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                        2065                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    1910535659000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  443146                       # Categorize read packet sizes
system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # categorize write packet sizes
system.physmem.writePktSize::1                      0                       # categorize write packet sizes
system.physmem.writePktSize::2                      0                       # categorize write packet sizes
system.physmem.writePktSize::3                      0                       # categorize write packet sizes
system.physmem.writePktSize::4                      0                       # categorize write packet sizes
system.physmem.writePktSize::5                      0                       # categorize write packet sizes
system.physmem.writePktSize::6                 117758                       # categorize write packet sizes
system.physmem.writePktSize::7                      0                       # categorize write packet sizes
system.physmem.writePktSize::8                      0                       # categorize write packet sizes
system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::6                  130                       # categorize neither packet sizes
system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
system.physmem.rdQLenPdf::0                    402456                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      4645                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      3680                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      2219                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      3123                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      2964                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      2721                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      2721                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      2666                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      2589                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1544                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1454                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1412                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1360                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     1368                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     1379                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                     1611                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                     1491                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      926                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      759                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       13                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      3510                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      3683                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      4101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      4153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      4653                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      5001                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      5007                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      5012                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      5015                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     1521                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     1348                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                      930                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                      877                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                      377                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       29                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                       23                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                       18                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                     4718066660                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat               13230246660                       # Sum of mem lat for all requests
system.physmem.totBusLat                   2215505000                       # Total cycles spent in databus access
system.physmem.totBankLat                  6296675000                       # Total cycles spent in bank access
system.physmem.avgQLat                       10647.84                       # Average queueing delay per request
system.physmem.avgBankLat                    14210.47                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  29858.31                       # Average memory access latency
system.physmem.avgRdBW                          14.84                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           3.88                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  14.84                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   3.88                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.01                       # Average read queue length over time
system.physmem.avgWrQLen                        11.47                       # Average write queue length over time
system.physmem.readRowHits                     415807                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     89941                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   93.84                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  77.74                       # Row buffer hit rate for writes
system.physmem.avgGap                      3418758.64                       # Average gap between requests
system.iocache.replacements                     41685                       # number of replacements
system.iocache.tagsinuse                     1.342284                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              1745701071000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide       1.342284                       # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide      0.083893                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.083893                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
system.iocache.overall_misses::total            41725                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     20927998                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     20927998                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide  10644331806                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  10644331806                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide  10665259804                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  10665259804                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide  10665259804                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  10665259804                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120971.086705                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256168.940268                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 256168.940268                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 255608.383559                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 255608.383559                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 255608.383559                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 255608.383559                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        285028                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                27152                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.497496                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41512                       # number of writebacks
system.iocache.writebacks::total                41512                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11931250                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     11931250                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   8482336109                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   8482336109                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide   8494267359                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   8494267359                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide   8494267359                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   8494267359                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.763006                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.763006                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204137.853990                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 204137.853990                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203577.408244                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 203577.408244                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203577.408244                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 203577.408244                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                      9055197                       # DTB read hits
system.cpu.dtb.read_misses                      10329                       # DTB read misses
system.cpu.dtb.read_acv                           210                       # DTB read access violations
system.cpu.dtb.read_accesses                   728856                       # DTB read accesses
system.cpu.dtb.write_hits                     6350929                       # DTB write hits
system.cpu.dtb.write_misses                      1142                       # DTB write misses
system.cpu.dtb.write_acv                          157                       # DTB write access violations
system.cpu.dtb.write_accesses                  291931                       # DTB write accesses
system.cpu.dtb.data_hits                     15406126                       # DTB hits
system.cpu.dtb.data_misses                      11471                       # DTB misses
system.cpu.dtb.data_acv                           367                       # DTB access violations
system.cpu.dtb.data_accesses                  1020787                       # DTB accesses
system.cpu.itb.fetch_hits                     4974131                       # ITB hits
system.cpu.itb.fetch_misses                      5006                       # ITB misses
system.cpu.itb.fetch_acv                          184                       # ITB acv
system.cpu.itb.fetch_accesses                 4979137                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.numCycles                       3821095118                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                    56120911                       # Number of instructions committed
system.cpu.committedOps                      56120911                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses              51995405                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                 324259                       # Number of float alu accesses
system.cpu.num_func_calls                     1481756                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts      6462892                       # number of instructions that are conditional controls
system.cpu.num_int_insts                     51995405                       # number of integer instructions
system.cpu.num_fp_insts                        324259                       # number of float instructions
system.cpu.num_int_register_reads            71234690                       # number of times the integer registers were read
system.cpu.num_int_register_writes           38473511                       # number of times the integer registers were written
system.cpu.num_fp_register_reads               163543                       # number of times the floating registers were read
system.cpu.num_fp_register_writes              166418                       # number of times the floating registers were written
system.cpu.num_mem_refs                      15458726                       # number of memory refs
system.cpu.num_load_insts                     9092044                       # Number of load instructions
system.cpu.num_store_insts                    6366682                       # Number of store instructions
system.cpu.num_idle_cycles               3587142255.998123                       # Number of idle cycles
system.cpu.num_busy_cycles               233952862.001878                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.061227                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.938773                       # Percentage of idle cycles
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     6380                       # number of quiesce instructions executed
system.cpu.kern.inst.hwrei                     211970                       # number of hwrei instructions executed
system.cpu.kern.ipl_count::0                    74891     40.89%     40.89% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21                     131      0.07%     40.96% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22                    1930      1.05%     42.01% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31                  106204     57.99%    100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total               183156                       # number of times we switched to this ipl
system.cpu.kern.ipl_good::0                     73524     49.31%     49.31% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22                     1930      1.29%     50.69% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31                    73524     49.31%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total                149109                       # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0             1855675111500     97.13%     97.13% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21                91586500      0.00%     97.13% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22               735892500      0.04%     97.17% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31             54044234500      2.83%    100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total         1910546825000                       # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0                  0.981747                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31                 0.692290                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total              0.814109                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
system.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
system.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
system.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
system.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
system.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
system.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
system.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
system.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
system.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
system.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
system.cpu.kern.syscall::total                    326                       # number of syscalls executed
system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx                  4174      2.16%      2.17% # number of callpals executed
system.cpu.kern.callpal::tbi                       54      0.03%      2.19% # number of callpals executed
system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
system.cpu.kern.callpal::swpipl                175939     91.22%     93.42% # number of callpals executed
system.cpu.kern.callpal::rdps                    6831      3.54%     96.96% # number of callpals executed
system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
system.cpu.kern.callpal::wrusp                      7      0.00%     96.96% # number of callpals executed
system.cpu.kern.callpal::rdusp                      9      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::rti                     5155      2.67%     99.64% # number of callpals executed
system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
system.cpu.kern.callpal::total                 192879                       # number of callpals executed
system.cpu.kern.mode_switch::kernel              5900                       # number of protection mode switches
system.cpu.kern.mode_switch::user                1744                       # number of protection mode switches
system.cpu.kern.mode_switch::idle                2095                       # number of protection mode switches
system.cpu.kern.mode_good::kernel                1913                      
system.cpu.kern.mode_good::user                  1744                      
system.cpu.kern.mode_good::idle                   169                      
system.cpu.kern.mode_switch_good::kernel     0.324237                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle       0.080668                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total      0.392853                       # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel        45393996500      2.38%      2.38% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user           5132973000      0.27%      2.64% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle         1860019853500     97.36%    100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context                     4175                       # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.cpu.icache.replacements                 927816                       # number of replacements
system.cpu.icache.tagsinuse                509.100001                       # Cycle average of tags in use
system.cpu.icache.total_refs                 55204264                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                 928327                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                  59.466399                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle            32331359000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     509.100001                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.994336                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.994336                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     55204264                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        55204264                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      55204264                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         55204264                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     55204264                       # number of overall hits
system.cpu.icache.overall_hits::total        55204264                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       928486                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        928486                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       928486                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         928486                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       928486                       # number of overall misses
system.cpu.icache.overall_misses::total        928486                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  12769098000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  12769098000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  12769098000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  12769098000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  12769098000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  12769098000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     56132750                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     56132750                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     56132750                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     56132750                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     56132750                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     56132750                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016541                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.016541                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.016541                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.016541                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.016541                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.016541                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13752.601547                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13752.601547                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13752.601547                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13752.601547                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13752.601547                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13752.601547                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       928486                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       928486                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       928486                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       928486                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       928486                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       928486                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  10912126000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  10912126000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  10912126000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  10912126000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  10912126000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  10912126000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016541                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016541                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016541                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.016541                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.016541                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.016541                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11752.601547                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11752.601547                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11752.601547                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11752.601547                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11752.601547                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11752.601547                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                336232                       # number of replacements
system.cpu.l2cache.tagsinuse             65320.349460                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 2445455                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                401395                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  6.092390                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle            5253905752                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 55746.369541                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   4781.447334                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data   4792.532585                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.850622                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.072959                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.073128                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.996709                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst       915175                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       814009                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1729184                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       834499                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       834499                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       187516                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       187516                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst       915175                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1001525                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1916700                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst       915175                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1001525                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1916700                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst        13291                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       271961                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       285252                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data           13                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           13                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       116841                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       116841                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst        13291                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       388802                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        402093                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        13291                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       388802                       # number of overall misses
system.cpu.l2cache.overall_misses::total       402093                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    831870000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  11715487000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  12547357000                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       189500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       189500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5599308500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   5599308500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    831870000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  17314795500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  18146665500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    831870000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  17314795500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  18146665500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst       928466                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1085970                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2014436                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       834499                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       834499                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           17                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           17                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       304357                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       304357                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst       928466                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1390327                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2318793                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       928466                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1390327                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2318793                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014315                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.250431                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.141604                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.764706                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.764706                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383895                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.383895                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014315                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.279648                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.173406                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014315                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.279648                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.173406                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62588.969980                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43077.819982                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 43986.920337                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14576.923077                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14576.923077                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 47922.463005                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47922.463005                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62588.969980                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 44533.709960                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 45130.518313                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62588.969980                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44533.709960                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 45130.518313                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        74181                       # number of writebacks
system.cpu.l2cache.writebacks::total            74181                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        13291                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       271961                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       285252                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           13                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           13                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       116841                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       116841                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        13291                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       388802                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       402093                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        13291                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       388802                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       402093                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    666952085                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   8376868075                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   9043820160                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       230011                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       230011                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4162858124                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4162858124                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    666952085                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  12539726199                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  13206678284                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    666952085                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  12539726199                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  13206678284                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1334145500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1334145500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1895221000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1895221000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3229366500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3229366500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014315                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.250431                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.141604                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.764706                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.764706                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383895                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383895                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014315                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.279648                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.173406                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014315                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.279648                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.173406                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 50180.730193                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30801.725523                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31704.668714                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35628.402051                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35628.402051                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50180.730193                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32252.216293                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32844.835110                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50180.730193                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32252.216293                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32844.835110                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1389814                       # number of replacements
system.cpu.dcache.tagsinuse                511.980842                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 14034828                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1390326                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  10.094631                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               93552000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.980842                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999963                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999963                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data      7805620                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total         7805620                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      5846988                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        5846988                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       182985                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       182985                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       199218                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       199218                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      13652608                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         13652608                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     13652608                       # number of overall hits
system.cpu.dcache.overall_hits::total        13652608                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1068716                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1068716                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       304374                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       304374                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        17254                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        17254                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1373090                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1373090                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1373090                       # number of overall misses
system.cpu.dcache.overall_misses::total       1373090                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  22883646000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  22883646000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   8388017500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   8388017500                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    229841000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    229841000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  31271663500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  31271663500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  31271663500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  31271663500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data      8874336                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total      8874336                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      6151362                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6151362                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200239                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       200239                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       199218                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       199218                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     15025698                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     15025698                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     15025698                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     15025698                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120428                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.120428                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049481                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.049481                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086167                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086167                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.091383                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.091383                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.091383                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.091383                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21412.279782                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 21412.279782                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27558.258918                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 27558.258918                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13321.027008                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13321.027008                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22774.664079                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22774.664079                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22774.664079                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22774.664079                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       834499                       # number of writebacks
system.cpu.dcache.writebacks::total            834499                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1068716                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1068716                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304374                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       304374                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17254                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        17254                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1373090                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1373090                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1373090                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1373090                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  20746214000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  20746214000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   7779269500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   7779269500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    195333000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    195333000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  28525483500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  28525483500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28525483500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  28525483500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1424235500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1424235500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2010997000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2010997000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3435232500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   3435232500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120428                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120428                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049481                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049481                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086167                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086167                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091383                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.091383                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091383                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.091383                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19412.279782                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19412.279782                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25558.258918                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25558.258918                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11321.027008                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11321.027008                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20774.664079                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20774.664079                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20774.664079                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20774.664079                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------