path: root/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.918467                       # Number of seconds simulated
sim_ticks                                1918467182000                       # Number of ticks simulated
final_tick                               1918467182000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 829809                       # Simulator instruction rate (inst/s)
host_op_rate                                   829809                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            28329510825                       # Simulator tick rate (ticks/s)
host_mem_usage                                 306208                       # Number of bytes of host memory used
host_seconds                                    67.72                       # Real time elapsed on the host
sim_insts                                    56194431                       # Number of instructions simulated
sim_ops                                      56194431                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            850752                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24859200                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2652352                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28362304                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       850752                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          850752                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7404544                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7404544                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst              13293                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             388425                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41443                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                443161                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          115696                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               115696                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               443454                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             12957845                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1382537                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                14783836                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          443454                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             443454                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3859615                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3859615                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3859615                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              443454                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            12957845                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1382537                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               18643451                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        443161                       # Total number of read requests seen
system.physmem.writeReqs                       115696                       # Total number of write requests seen
system.physmem.cpureqs                         558987                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                     28362304                       # Total number of bytes read from memory
system.physmem.bytesWritten                   7404544                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               28362304                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                7404544                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       54                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite                130                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                 27850                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                 28128                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                 28329                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                 28032                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                 27520                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                 27540                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                 26738                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                 26867                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                 27896                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                 27091                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                27744                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                27474                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                27482                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                28202                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                28119                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                28095                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  7621                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  7634                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  7863                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  7544                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  7117                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  6982                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  6321                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  6315                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  7316                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  6513                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 7108                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 6910                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 7064                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 7822                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 7859                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 7707                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    1918455311000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  443161                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                 115696                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                    402425                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      6960                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      5341                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      3282                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      3278                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      3029                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      1564                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1523                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      1479                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1447                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1416                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1406                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1371                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     2035                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     2356                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     2252                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                     1207                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      414                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      213                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      104                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        5                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      3570                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      3665                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      4737                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      5028                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      5029                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     1461                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     1366                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                      294                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        37346                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      957.575108                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     229.677714                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev    2441.521254                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-67          13136     35.17%     35.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-131         5703     15.27%     50.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-195         3412      9.14%     59.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-259         2227      5.96%     65.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-323         1623      4.35%     69.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-387         1358      3.64%     73.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-451          966      2.59%     76.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-515          781      2.09%     78.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-579          632      1.69%     79.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-643          563      1.51%     81.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-707          543      1.45%     82.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-771          430      1.15%     84.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-835          310      0.83%     84.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-899          236      0.63%     85.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-963          166      0.44%     85.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1027          218      0.58%     86.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1091          124      0.33%     86.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1155           90      0.24%     87.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1219           81      0.22%     87.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1283           99      0.27%     87.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1347           87      0.23%     87.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1411           95      0.25%     88.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1475         1075      2.88%     90.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1539          150      0.40%     91.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1603           90      0.24%     91.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1667           48      0.13%     91.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1731           42      0.11%     91.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1795           35      0.09%     91.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1859           29      0.08%     91.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1923           22      0.06%     92.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1987           18      0.05%     92.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2051           29      0.08%     92.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2115           17      0.05%     92.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2179            5      0.01%     92.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2243           12      0.03%     92.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2307            7      0.02%     92.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2371            8      0.02%     92.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2435            4      0.01%     92.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2499            3      0.01%     92.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2563            3      0.01%     92.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2627            6      0.02%     92.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2691            5      0.01%     92.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2755            3      0.01%     92.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2819            5      0.01%     92.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2883            4      0.01%     92.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2947            2      0.01%     92.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3011            2      0.01%     92.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3075            4      0.01%     92.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3139            2      0.01%     92.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3203            6      0.02%     92.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3267            4      0.01%     92.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3331            5      0.01%     92.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3395            2      0.01%     92.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3459            1      0.00%     92.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3523            3      0.01%     92.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3587            1      0.00%     92.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3715            2      0.01%     92.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3779            3      0.01%     92.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3843            1      0.00%     92.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3907            3      0.01%     92.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3971            3      0.01%     92.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4035            1      0.00%     92.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4099            1      0.00%     92.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4227            1      0.00%     92.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4355            2      0.01%     92.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4419            1      0.00%     92.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4675            1      0.00%     92.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4739            2      0.01%     92.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4931            4      0.01%     92.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4995            1      0.00%     92.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5123            1      0.00%     92.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5315            2      0.01%     92.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5379            2      0.01%     92.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5699            2      0.01%     92.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5891            1      0.00%     92.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6083            1      0.00%     92.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6403            1      0.00%     92.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6595            1      0.00%     92.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6851            1      0.00%     92.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7171            2      0.01%     92.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7235            2      0.01%     92.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7299            2      0.01%     92.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7363            1      0.00%     92.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7555            1      0.00%     92.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7619            1      0.00%     92.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7683            1      0.00%     92.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7747            1      0.00%     92.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7811            1      0.00%     92.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7939            4      0.01%     92.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8003            3      0.01%     92.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8131            4      0.01%     92.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8195         2437      6.53%     99.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8256-8259            1      0.00%     99.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9024-9027            1      0.00%     99.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9219            1      0.00%     99.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9728-9731            1      0.00%     99.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10432-10435            1      0.00%     99.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11712-11715            1      0.00%     99.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13440-13443            1      0.00%     99.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14208-14211            1      0.00%     99.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14272-14275            2      0.01%     99.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14464-14467            2      0.01%     99.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14528-14531            1      0.00%     99.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14656-14659            1      0.00%     99.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14720-14723            1      0.00%     99.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14784-14787            1      0.00%     99.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14912-14915            2      0.01%     99.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14976-14979            1      0.00%     99.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15232-15235            1      0.00%     99.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15296-15299            1      0.00%     99.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15363           15      0.04%     99.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15424-15427            1      0.00%     99.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15744-15747            1      0.00%     99.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15936-15939            1      0.00%     99.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16192-16195            1      0.00%     99.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16387          239      0.64%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16448-16451            9      0.02%     99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16512-16515            8      0.02%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16576-16579            4      0.01%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16640-16643            3      0.01%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16704-16707            1      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16768-16771            1      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16832-16835            2      0.01%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16896-16899            2      0.01%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16960-16963            2      0.01%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17024-17027            4      0.01%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17536-17539            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          37346                       # Bytes accessed per row activation
system.physmem.totQLat                     3689041500                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat               11833576500                       # Sum of mem lat for all requests
system.physmem.totBusLat                   2215535000                       # Total cycles spent in databus access
system.physmem.totBankLat                  5929000000                       # Total cycles spent in bank access
system.physmem.avgQLat                        8325.40                       # Average queueing delay per request
system.physmem.avgBankLat                    13380.52                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  26705.91                       # Average memory access latency
system.physmem.avgRdBW                          14.78                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           3.86                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  14.78                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   3.86                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.01                       # Average read queue length over time
system.physmem.avgWrQLen                        11.67                       # Average write queue length over time
system.physmem.readRowHits                     427971                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     93480                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   96.58                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  80.80                       # Row buffer hit rate for writes
system.physmem.avgGap                      3432819.69                       # Average gap between requests
system.membus.throughput                     18685123                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              292355                       # Transaction distribution
system.membus.trans_dist::ReadResp             292355                       # Transaction distribution
system.membus.trans_dist::WriteReq               9649                       # Transaction distribution
system.membus.trans_dist::WriteResp              9649                       # Transaction distribution
system.membus.trans_dist::Writeback            115696                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              132                       # Transaction distribution
system.membus.trans_dist::UpgradeResp             132                       # Transaction distribution
system.membus.trans_dist::ReadExReq            158289                       # Transaction distribution
system.membus.trans_dist::ReadExResp           158289                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33158                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       878153                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total       911311                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124680                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       124680                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.bridge.slave        33158                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.physmem.port      1002833                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1035991                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44556                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30457728                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     30502284                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5309120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total      5309120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.bridge.slave        44556                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.physmem.port     35766848                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            35811404                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               35811404                       # Total data (bytes)
system.membus.snoop_data_through_bus            35392                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy            32374500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy          1489970000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer1.occupancy         3747469854                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy          376209000                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.iocache.replacements                     41685                       # number of replacements
system.iocache.tagsinuse                     1.345466                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              1752554384000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide       1.345466                       # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide      0.084092                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.084092                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
system.iocache.overall_misses::total            41725                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21342883                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21342883                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide  10435666030                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  10435666030                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide  10457008913                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  10457008913                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide  10457008913                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  10457008913                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123369.265896                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 123369.265896                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251147.141654                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 251147.141654                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 250617.349623                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 250617.349623                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 250617.349623                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 250617.349623                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        271244                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                27003                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.044958                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41512                       # number of writebacks
system.iocache.writebacks::total                41512                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12346133                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     12346133                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   8274278780                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   8274278780                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide   8286624913                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   8286624913                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide   8286624913                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   8286624913                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71364.930636                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 71364.930636                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199130.698402                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 199130.698402                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198600.956573                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 198600.956573                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198600.956573                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 198600.956573                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                      9066498                       # DTB read hits
system.cpu.dtb.read_misses                      10324                       # DTB read misses
system.cpu.dtb.read_acv                           210                       # DTB read access violations
system.cpu.dtb.read_accesses                   728853                       # DTB read accesses
system.cpu.dtb.write_hits                     6357377                       # DTB write hits
system.cpu.dtb.write_misses                      1142                       # DTB write misses
system.cpu.dtb.write_acv                          157                       # DTB write access violations
system.cpu.dtb.write_accesses                  291931                       # DTB write accesses
system.cpu.dtb.data_hits                     15423875                       # DTB hits
system.cpu.dtb.data_misses                      11466                       # DTB misses
system.cpu.dtb.data_acv                           367                       # DTB access violations
system.cpu.dtb.data_accesses                  1020784                       # DTB accesses
system.cpu.itb.fetch_hits                     4974559                       # ITB hits
system.cpu.itb.fetch_misses                      5010                       # ITB misses
system.cpu.itb.fetch_acv                          184                       # ITB acv
system.cpu.itb.fetch_accesses                 4979569                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.numCycles                       3836934364                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                    56194431                       # Number of instructions committed
system.cpu.committedOps                      56194431                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses              52065988                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                 324527                       # Number of float alu accesses
system.cpu.num_func_calls                     1483664                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts      6469615                       # number of instructions that are conditional controls
system.cpu.num_int_insts                     52065988                       # number of integer instructions
system.cpu.num_fp_insts                        324527                       # number of float instructions
system.cpu.num_int_register_reads            71339773                       # number of times the integer registers were read
system.cpu.num_int_register_writes           38529890                       # number of times the integer registers were written
system.cpu.num_fp_register_reads               163675                       # number of times the floating registers were read
system.cpu.num_fp_register_writes              166554                       # number of times the floating registers were written
system.cpu.num_mem_refs                      15476497                       # number of memory refs
system.cpu.num_load_insts                     9103354                       # Number of load instructions
system.cpu.num_store_insts                    6373143                       # Number of store instructions
system.cpu.num_idle_cycles               3587701469.998130                       # Number of idle cycles
system.cpu.num_busy_cycles               249232894.001870                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.064956                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.935044                       # Percentage of idle cycles
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     6375                       # number of quiesce instructions executed
system.cpu.kern.inst.hwrei                     212005                       # number of hwrei instructions executed
system.cpu.kern.ipl_count::0                    74904     40.89%     40.89% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21                     131      0.07%     40.96% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22                    1931      1.05%     42.01% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31                  106221     57.99%    100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total               183187                       # number of times we switched to this ipl
system.cpu.kern.ipl_good::0                     73537     49.31%     49.31% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22                     1931      1.29%     50.69% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31                    73537     49.31%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total                149136                       # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0             1857459158500     96.82%     96.82% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21                91312500      0.00%     96.82% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22               736664500      0.04%     96.86% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31             60179312500      3.14%    100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total         1918466448000                       # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0                  0.981750                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31                 0.692302                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total              0.814119                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
system.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
system.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
system.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
system.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
system.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
system.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
system.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
system.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
system.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
system.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
system.cpu.kern.syscall::total                    326                       # number of syscalls executed
system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx                  4178      2.17%      2.17% # number of callpals executed
system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
system.cpu.kern.callpal::swpipl                175968     91.22%     93.42% # number of callpals executed
system.cpu.kern.callpal::rdps                    6832      3.54%     96.96% # number of callpals executed
system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
system.cpu.kern.callpal::wrusp                      7      0.00%     96.96% # number of callpals executed
system.cpu.kern.callpal::rdusp                      9      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::rti                     5156      2.67%     99.64% # number of callpals executed
system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
system.cpu.kern.callpal::total                 192914                       # number of callpals executed
system.cpu.kern.mode_switch::kernel              5904                       # number of protection mode switches
system.cpu.kern.mode_switch::user                1740                       # number of protection mode switches
system.cpu.kern.mode_switch::idle                2096                       # number of protection mode switches
system.cpu.kern.mode_good::kernel                1911                      
system.cpu.kern.mode_good::user                  1740                      
system.cpu.kern.mode_good::idle                   171                      
system.cpu.kern.mode_switch_good::kernel     0.323679                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle       0.081584                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total      0.392402                       # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel        46102035000      2.40%      2.40% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user           5243076000      0.27%      2.68% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle         1867121335000     97.32%    100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context                     4179                       # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.iobus.throughput                       1410587                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
system.iobus.trans_dist::WriteReq               51201                       # Transaction distribution
system.iobus.trans_dist::WriteResp              51201                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5154                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        33158                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.cchip.pio         5154                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  116608                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        20616                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total        44556                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.cchip.pio        20616                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total              2706164                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                 2706164                       # Total data (bytes)
system.iobus.reqLayer0.occupancy              4765000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               353000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            13484000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy             1887000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy               76000                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer29.occupancy           378256913                       # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            23509000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            42010000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.cpu.icache.replacements                 928573                       # number of replacements
system.cpu.icache.tagsinuse                508.447268                       # Cycle average of tags in use
system.cpu.icache.total_refs                 55277021                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                 929084                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                  59.496258                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle            38501717000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     508.447268                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.993061                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.993061                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     55277021                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        55277021                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      55277021                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         55277021                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     55277021                       # number of overall hits
system.cpu.icache.overall_hits::total        55277021                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       929244                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        929244                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       929244                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         929244                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       929244                       # number of overall misses
system.cpu.icache.overall_misses::total        929244                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  12990910500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  12990910500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  12990910500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  12990910500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  12990910500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  12990910500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     56206265                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     56206265                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     56206265                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     56206265                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     56206265                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     56206265                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016533                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.016533                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.016533                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.016533                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.016533                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.016533                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13980.085424                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13980.085424                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13980.085424                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13980.085424                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13980.085424                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13980.085424                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       929244                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       929244                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       929244                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       929244                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       929244                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       929244                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11132422500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  11132422500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11132422500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  11132422500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11132422500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  11132422500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016533                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016533                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016533                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.016533                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.016533                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.016533                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11980.085424                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11980.085424                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11980.085424                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11980.085424                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11980.085424                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11980.085424                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                336249                       # number of replacements
system.cpu.l2cache.tagsinuse             65299.317705                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 2448334                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                401410                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  6.099335                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle            6517964750                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 55625.043454                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   4760.305477                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data   4913.968774                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.848771                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.072636                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.074981                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.996389                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst       915931                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       815128                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1731059                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       835526                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       835526                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       187585                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       187585                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst       915931                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1002713                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1918644                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst       915931                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1002713                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1918644                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst        13293                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       271959                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       285252                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data           13                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           13                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       116856                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       116856                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst        13293                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       388815                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        402108                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        13293                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       388815                       # number of overall misses
system.cpu.l2cache.overall_misses::total       402108                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1043848500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  16878045500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  17921894000                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       189500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       189500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7749920500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   7749920500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1043848500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  24627966000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  25671814500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1043848500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  24627966000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  25671814500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst       929224                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1087087                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2016311                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       835526                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       835526                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           17                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           17                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       304441                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       304441                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst       929224                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1391528                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2320752                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       929224                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1391528                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2320752                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014305                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.250172                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.141472                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.764706                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.764706                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383838                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.383838                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014305                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.279416                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.173266                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014305                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.279416                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.173266                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78526.179192                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62060.992650                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 62828.285165                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14576.923077                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14576.923077                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66320.261690                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66320.261690                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78526.179192                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63341.090236                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 63843.083202                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78526.179192                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63341.090236                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 63843.083202                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        74184                       # number of writebacks
system.cpu.l2cache.writebacks::total            74184                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        13293                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       271959                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       285252                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           13                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           13                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       116856                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       116856                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        13293                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       388815                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       402108                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        13293                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       388815                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       402108                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    879542258                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  13544515256                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  14424057514                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       230011                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       230011                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6316543121                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6316543121                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    879542258                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  19861058377                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  20740600635                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    879542258                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  19861058377                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  20740600635                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1334145000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1334145000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1895431500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1895431500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3229576500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3229576500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014305                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.250172                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.141472                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.764706                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.764706                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383838                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383838                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014305                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.279416                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.173266                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014305                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.279416                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.173266                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66165.820958                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 49803.519119                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50566.017115                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54054.076136                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54054.076136                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66165.820958                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 51080.998359                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 51579.676691                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66165.820958                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 51080.998359                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 51579.676691                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1391015                       # number of replacements
system.cpu.dcache.tagsinuse                511.979232                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 14051400                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1391527                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  10.097828                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle              105127000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.979232                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999959                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999959                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data      7815804                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total         7815804                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      5853333                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        5853333                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       182999                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       182999                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       199247                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       199247                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      13669137                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         13669137                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     13669137                       # number of overall hits
system.cpu.dcache.overall_hits::total        13669137                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1069817                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1069817                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       304458                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       304458                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        17270                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        17270                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1374275                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1374275                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1374275                       # number of overall misses
system.cpu.dcache.overall_misses::total       1374275                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  28060990500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  28060990500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  10539571500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  10539571500                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    229596000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    229596000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  38600562000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  38600562000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  38600562000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  38600562000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data      8885621                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total      8885621                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      6157791                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6157791                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200269                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       200269                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       199247                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       199247                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     15043412                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     15043412                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     15043412                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     15043412                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120399                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.120399                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049443                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.049443                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086234                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086234                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.091354                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.091354                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.091354                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.091354                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26229.710782                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 26229.710782                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34617.489112                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 34617.489112                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13294.499131                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13294.499131                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 28087.946008                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 28087.946008                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28087.946008                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 28087.946008                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       835526                       # number of writebacks
system.cpu.dcache.writebacks::total            835526                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1069817                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1069817                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304458                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       304458                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17270                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        17270                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1374275                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1374275                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1374275                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1374275                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  25921356500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  25921356500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9930655500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   9930655500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    195056000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    195056000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  35852012000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  35852012000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  35852012000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  35852012000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1424235000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1424235000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2011219500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2011219500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3435454500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   3435454500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120399                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120399                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049443                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049443                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086234                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086234                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091354                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.091354                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091354                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.091354                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24229.710782                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24229.710782                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32617.489112                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32617.489112                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11294.499131                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11294.499131                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26087.946008                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26087.946008                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26087.946008                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26087.946008                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput               105322456                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        2023434                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2023417                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq          9649                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp         9649                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       835526                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           17                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           17                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       345993                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       304442                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side      1858468                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side      3651931                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count                  5510399                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side     59470336                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side    142586060                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size             202056396                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         202046348                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus        11328                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     2426797500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       235500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1393866000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2099055000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)

---------- End Simulation Statistics   ----------