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|
{
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],
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},
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},
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"role": "SLAVE"
},
"in_addr_map": true
},
"clcd": {
"pio": {
"peer": "system.iobus.master[5]",
"role": "SLAVE"
},
"system": "system",
"cxx_class": "Pl111",
"enable_capture": true,
"pio_addr": 471793664,
"pio_latency": 10000,
"clk_domain": "system.clk_domain",
"int_num": 46,
"gic": "system.realview.gic",
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"eventq_index": 0,
"type": "Pl111",
"vnc": "system.vncserver",
"p_state_clk_gate_min": 1000,
"power_model": null,
"path": "system.realview.clcd",
"dma": {
"peer": "system.iobus.slave[1]",
"role": "MASTER"
},
"name": "clcd",
"p_state_clk_gate_bins": 20,
"pixel_clock": 41667,
"amba_id": 1315089
},
"name": "realview",
"uart": {
"p_state_clk_gate_min": 1000,
"terminal": "system.terminal",
"pio": {
"peer": "system.iobus.master[0]",
"role": "SLAVE"
},
"name": "uart",
"int_delay": 100000,
"platform": "system.realview",
"p_state_clk_gate_bins": 20,
"cxx_class": "Pl011",
"pio_latency": 100000,
"clk_domain": "system.clk_domain",
"power_model": null,
"system": "system",
"gic": "system.realview.gic",
"int_num": 37,
"eventq_index": 0,
"end_on_eot": false,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"path": "system.realview.uart",
"pio_addr": 470351872,
"type": "Pl011"
},
"intrctrl": "system.intrctrl",
"kmi1": {
"p_state_clk_gate_min": 1000,
"p_state_clk_gate_bins": 20,
"vnc": "system.vncserver",
"name": "kmi1",
"int_delay": 1000000,
"pio": {
"peer": "system.iobus.master[8]",
"role": "SLAVE"
},
"amba_id": 1314896,
"default_p_state": "UNDEFINED",
"pio_latency": 100000,
"clk_domain": "system.clk_domain",
"power_model": null,
"system": "system",
"gic": "system.realview.gic",
"int_num": 45,
"eventq_index": 0,
"is_mouse": true,
"cxx_class": "Pl050",
"p_state_clk_gate_max": 1000000000000,
"path": "system.realview.kmi1",
"pio_addr": 470220800,
"type": "Pl050"
},
"kmi0": {
"p_state_clk_gate_min": 1000,
"p_state_clk_gate_bins": 20,
"vnc": "system.vncserver",
"name": "kmi0",
"int_delay": 1000000,
"pio": {
"peer": "system.iobus.master[7]",
"role": "SLAVE"
},
"amba_id": 1314896,
"default_p_state": "UNDEFINED",
"pio_latency": 100000,
"clk_domain": "system.clk_domain",
"power_model": null,
"system": "system",
"gic": "system.realview.gic",
"int_num": 44,
"eventq_index": 0,
"is_mouse": false,
"cxx_class": "Pl050",
"p_state_clk_gate_max": 1000000000000,
"path": "system.realview.kmi0",
"pio_addr": 470155264,
"type": "Pl050"
},
"cf_ctrl": {
"PMCAPNextCapability": 0,
"InterruptPin": 1,
"HeaderType": 0,
"VendorID": 32902,
"MSIXMsgCtrl": 0,
"MSIXCAPNextCapability": 0,
"PXCAPLinkCtrl": 0,
"Revision": 0,
"LegacyIOBase": 0,
"pio_latency": 30000,
"PXCAPLinkCap": 0,
"CapabilityPtr": 0,
"MSIXCAPBaseOffset": 0,
"PXCAPDevCapabilities": 0,
"MSIXCAPCapId": 0,
"BAR3Size": 4,
"power_model": null,
"PXCAPCapabilities": 0,
"SubsystemID": 0,
"PXCAPCapId": 0,
"BAR4": 1,
"BAR1": 471466240,
"BAR0": 471465984,
"BAR3": 1,
"BAR2": 1,
"BAR5": 1,
"PXCAPDevStatus": 0,
"disks": [],
"BAR2Size": 8,
"MSICAPNextCapability": 0,
"ExpansionROM": 0,
"MSICAPMsgCtrl": 0,
"BAR5Size": 0,
"CardbusCIS": 0,
"MSIXPbaOffset": 0,
"MSICAPBaseOffset": 0,
"MaximumLatency": 0,
"BAR2LegacyIO": false,
"LatencyTimer": 0,
"BAR4LegacyIO": false,
"p_state_clk_gate_max": 1000000000000,
"PXCAPLinkStatus": 0,
"PXCAPDevCap2": 0,
"p_state_clk_gate_min": 1000,
"PXCAPDevCtrl": 0,
"MSICAPMaskBits": 0,
"host": "system.realview.pci_host",
"Command": 1,
"SubClassCode": 1,
"pci_func": 0,
"BAR5LegacyIO": false,
"MSICAPMsgData": 0,
"BIST": 0,
"PXCAPDevCtrl2": 0,
"pci_bus": 2,
"InterruptLine": 31,
"MSICAPMsgAddr": 0,
"BAR3LegacyIO": false,
"BAR4Size": 16,
"path": "system.realview.cf_ctrl",
"MinimumGrant": 0,
"Status": 640,
"BAR0Size": 256,
"system": "system",
"name": "cf_ctrl",
"PXCAPNextCapability": 0,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"type": "IdeController",
"ctrl_offset": 2,
"PXCAPBaseOffset": 0,
"DeviceID": 28945,
"io_shift": 2,
"CacheLineSize": 0,
"dma": {
"peer": "system.iobus.slave[2]",
"role": "MASTER"
},
"PMCAPCapId": 0,
"config_latency": 20000,
"BAR1Size": 4096,
"pio": {
"peer": "system.iobus.master[9]",
"role": "SLAVE"
},
"pci_dev": 0,
"PMCAPCtrlStatus": 0,
"cxx_class": "IdeController",
"clk_domain": "system.clk_domain",
"SubsystemVendorID": 0,
"PMCAPBaseOffset": 0,
"MSICAPPendingBits": 0,
"MSIXTableOffset": 0,
"MSICAPMsgUpperAddr": 0,
"MSICAPCapId": 0,
"BAR0LegacyIO": true,
"ProgIF": 133,
"BAR1LegacyIO": true,
"PMCAPCapabilities": 0,
"ClassCode": 1,
"p_state_clk_gate_bins": 20
},
"sp810_fake": {
"p_state_clk_gate_bins": 20,
"name": "sp810_fake",
"p_state_clk_gate_min": 1000,
"pio": {
"peer": "system.iobus.master[16]",
"role": "SLAVE"
},
"amba_id": 0,
"ignore_access": true,
"default_p_state": "UNDEFINED",
"pio_latency": 100000,
"clk_domain": "system.clk_domain",
"power_model": null,
"system": "system",
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"cxx_class": "AmbaFake",
"p_state_clk_gate_max": 1000000000000,
"path": "system.realview.sp810_fake",
"pio_addr": 469893120,
"type": "AmbaFake"
},
"ethernet": {
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"InterruptPin": 1,
"HeaderType": 0,
"VendorID": 32902,
"MSIXMsgCtrl": 0,
"MSIXCAPNextCapability": 0,
"PXCAPLinkCtrl": 0,
"Revision": 0,
"hardware_address": "00:90:00:00:00:01",
"LegacyIOBase": 0,
"pio_latency": 30000,
"PXCAPLinkCap": 0,
"CapabilityPtr": 0,
"MSIXCAPBaseOffset": 0,
"PXCAPDevCapabilities": 0,
"MSIXCAPCapId": 0,
"BAR3Size": 0,
"rx_desc_cache_size": 64,
"power_model": null,
"PXCAPCapabilities": 0,
"SubsystemID": 4104,
"PXCAPCapId": 0,
"BAR4": 0,
"BAR1": 0,
"BAR0": 0,
"BAR3": 0,
"BAR2": 0,
"BAR5": 0,
"PXCAPDevStatus": 0,
"BAR2Size": 0,
"MSICAPNextCapability": 0,
"ExpansionROM": 0,
"rx_write_delay": 0,
"MSICAPMsgCtrl": 0,
"BAR5Size": 0,
"CardbusCIS": 0,
"MSIXPbaOffset": 0,
"MSICAPBaseOffset": 0,
"MaximumLatency": 0,
"BAR2LegacyIO": false,
"LatencyTimer": 0,
"BAR4LegacyIO": false,
"p_state_clk_gate_max": 1000000000000,
"PXCAPLinkStatus": 0,
"PXCAPDevCap2": 0,
"p_state_clk_gate_min": 1000,
"PXCAPDevCtrl": 0,
"MSICAPMaskBits": 0,
"host": "system.realview.pci_host",
"Command": 0,
"SubClassCode": 0,
"pci_func": 0,
"BAR5LegacyIO": false,
"MSICAPMsgData": 0,
"BIST": 0,
"PXCAPDevCtrl2": 0,
"pci_bus": 0,
"InterruptLine": 1,
"fetch_delay": 10000,
"MSICAPMsgAddr": 0,
"BAR3LegacyIO": false,
"BAR4Size": 0,
"path": "system.realview.ethernet",
"MinimumGrant": 255,
"phy_epid": 896,
"Status": 0,
"BAR0Size": 131072,
"system": "system",
"name": "ethernet",
"PXCAPNextCapability": 0,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"type": "IGbE",
"tx_fifo_size": 393216,
"PXCAPBaseOffset": 0,
"DeviceID": 4213,
"tx_read_delay": 0,
"CacheLineSize": 0,
"dma": {
"peer": "system.iobus.slave[4]",
"role": "MASTER"
},
"PMCAPCapId": 0,
"tx_desc_cache_size": 64,
"config_latency": 20000,
"BAR1Size": 0,
"pio": {
"peer": "system.iobus.master[24]",
"role": "SLAVE"
},
"pci_dev": 0,
"PMCAPCtrlStatus": 0,
"cxx_class": "IGbE",
"wb_delay": 10000,
"fetch_comp_delay": 10000,
"clk_domain": "system.clk_domain",
"SubsystemVendorID": 32902,
"PMCAPBaseOffset": 0,
"MSICAPPendingBits": 0,
"MSIXTableOffset": 0,
"MSICAPMsgUpperAddr": 0,
"MSICAPCapId": 0,
"BAR0LegacyIO": false,
"ProgIF": 0,
"BAR1LegacyIO": false,
"wb_comp_delay": 10000,
"PMCAPCapabilities": 0,
"ClassCode": 2,
"p_state_clk_gate_bins": 20,
"rx_fifo_size": 393216,
"phy_pid": 680
},
"ide": {
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"InterruptPin": 2,
"HeaderType": 0,
"VendorID": 32902,
"MSIXMsgCtrl": 0,
"MSIXCAPNextCapability": 0,
"PXCAPLinkCtrl": 0,
"Revision": 0,
"LegacyIOBase": 0,
"pio_latency": 30000,
"PXCAPLinkCap": 0,
"CapabilityPtr": 0,
"MSIXCAPBaseOffset": 0,
"PXCAPDevCapabilities": 0,
"MSIXCAPCapId": 0,
"BAR3Size": 4,
"power_model": null,
"PXCAPCapabilities": 0,
"SubsystemID": 0,
"PXCAPCapId": 0,
"BAR4": 1,
"BAR1": 1,
"BAR0": 1,
"BAR3": 1,
"BAR2": 1,
"BAR5": 1,
"PXCAPDevStatus": 0,
"disks": [
"system.cf0"
],
"BAR2Size": 8,
"MSICAPNextCapability": 0,
"ExpansionROM": 0,
"MSICAPMsgCtrl": 0,
"BAR5Size": 0,
"CardbusCIS": 0,
"MSIXPbaOffset": 0,
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"MaximumLatency": 0,
"BAR2LegacyIO": false,
"LatencyTimer": 0,
"BAR4LegacyIO": false,
"p_state_clk_gate_max": 1000000000000,
"PXCAPLinkStatus": 0,
"PXCAPDevCap2": 0,
"p_state_clk_gate_min": 1000,
"PXCAPDevCtrl": 0,
"MSICAPMaskBits": 0,
"host": "system.realview.pci_host",
"Command": 0,
"SubClassCode": 1,
"pci_func": 0,
"BAR5LegacyIO": false,
"MSICAPMsgData": 0,
"BIST": 0,
"PXCAPDevCtrl2": 0,
"pci_bus": 0,
"InterruptLine": 2,
"MSICAPMsgAddr": 0,
"BAR3LegacyIO": false,
"BAR4Size": 16,
"path": "system.realview.ide",
"MinimumGrant": 0,
"Status": 640,
"BAR0Size": 8,
"system": "system",
"name": "ide",
"PXCAPNextCapability": 0,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"type": "IdeController",
"ctrl_offset": 0,
"PXCAPBaseOffset": 0,
"DeviceID": 28945,
"io_shift": 0,
"CacheLineSize": 0,
"dma": {
"peer": "system.iobus.slave[3]",
"role": "MASTER"
},
"PMCAPCapId": 0,
"config_latency": 20000,
"BAR1Size": 4,
"pio": {
"peer": "system.iobus.master[23]",
"role": "SLAVE"
},
"pci_dev": 1,
"PMCAPCtrlStatus": 0,
"cxx_class": "IdeController",
"clk_domain": "system.clk_domain",
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"PMCAPBaseOffset": 0,
"MSICAPPendingBits": 0,
"MSIXTableOffset": 0,
"MSICAPMsgUpperAddr": 0,
"MSICAPCapId": 0,
"BAR0LegacyIO": false,
"ProgIF": 133,
"BAR1LegacyIO": false,
"PMCAPCapabilities": 0,
"ClassCode": 1,
"p_state_clk_gate_bins": 20
}
},
"membus": {
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"system": "system",
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"cxx_class": "CoherentXBar",
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"peer": "system.membus.default",
"role": "SLAVE"
},
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"clk_domain": "system.clk_domain",
"cxx_class": "IsaFake",
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"update_data": false,
"warn_access": "warn",
"pio_latency": 100000,
"system": "system",
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"default_p_state": "UNDEFINED",
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"type": "IsaFake",
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"power_model": null,
"ret_data32": 4294967295,
"path": "system.membus.badaddr_responder",
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"ret_data8": 255,
"name": "badaddr_responder",
"ret_bad_addr": true,
"pio_size": 8,
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},
"forward_latency": 4,
"clk_domain": "system.clk_domain",
"width": 16,
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"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"master": {
"peer": [
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"system.realview.nvmem.port",
"system.realview.gic.pio",
"system.realview.vgic.pio",
"system.realview.local_cpu_timer.pio",
"system.physmem.port"
],
"role": "MASTER"
},
"type": "CoherentXBar",
"frontend_latency": 3,
"slave": {
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"system.system_port",
"system.cpu.l2cache.mem_side",
"system.iocache.mem_side"
],
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},
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"snoop_filter": null,
"power_model": null,
"path": "system.membus",
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"name": "membus",
"default": {
"peer": "system.membus.badaddr_responder.pio",
"role": "MASTER"
},
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},
"multi_thread": false,
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"default_p_state": "UNDEFINED",
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},
"clusivity": "mostly_incl",
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"system": "system",
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"response_latency": 50,
"cxx_class": "Cache",
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"tags": {
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"assoc": 8,
"cxx_class": "LRU",
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"path": "system.iocache.tags",
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"type": "LRU",
"size": 1024
},
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"default_p_state": "UNDEFINED",
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"mem_side": {
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},
"type": "Cache",
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"addr_ranges": [
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],
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"path": "system.iocache",
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"name": "iocache",
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"sequential_access": false,
"assoc": 8
},
"dvfs_handler": {
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"name": "dvfs_handler",
"sys_clk_domain": "system.clk_domain",
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"cxx_class": "DVFSHandler",
"domains": [],
"path": "system.dvfs_handler",
"type": "DVFSHandler"
},
"work_end_exit_count": 0,
"type": "LinuxArmSystem",
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"voltage": [
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],
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"path": "system.voltage_domain",
"type": "VoltageDomain"
},
"cache_line_size": 64,
"boot_osflags": "earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1",
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"role": "MASTER"
},
"physmem": [
{
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"latency": 30000,
"name": "physmem",
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"default_p_state": "UNDEFINED",
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"bandwidth": "73.000000",
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"cxx_class": "SimpleMemory",
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"path": "system.physmem",
"null": false,
"type": "SimpleMemory",
"port": {
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"role": "SLAVE"
},
"in_addr_map": true
}
],
"terminal": {
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"output": true,
"number": 0,
"intr_control": "system.intrctrl",
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"cxx_class": "Terminal",
"path": "system.terminal",
"type": "Terminal",
"port": 3456
},
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"reset_addr_64": 0,
"cpu": [
{
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"itb": {
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"cxx_class": "ArmISA::TLB",
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"name": "walker",
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"cxx_class": "ArmISA::TableWalker",
"clk_domain": "system.cpu_clk_domain",
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"sys": "system",
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"default_p_state": "UNDEFINED",
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"path": "system.cpu.itb.walker",
"type": "ArmTableWalker",
"port": {
"peer": "system.cpu.toL2Bus.slave[2]",
"role": "MASTER"
},
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},
"path": "system.cpu.itb",
"type": "ArmTLB",
"size": 64
},
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"istage2_mmu": {
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"tlb": "system.cpu.itb",
"sys": "system",
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"cxx_class": "ArmISA::TLB",
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"name": "walker",
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"cxx_class": "ArmISA::TableWalker",
"clk_domain": "system.cpu_clk_domain",
"power_model": null,
"sys": "system",
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"default_p_state": "UNDEFINED",
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"path": "system.cpu.istage2_mmu.stage2_tlb.walker",
"type": "ArmTableWalker",
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},
"path": "system.cpu.istage2_mmu.stage2_tlb",
"type": "ArmTLB",
"size": 32
},
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"cxx_class": "ArmISA::Stage2MMU",
"path": "system.cpu.istage2_mmu",
"type": "ArmStage2MMU"
},
"icache": {
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"role": "SLAVE"
},
"clusivity": "mostly_incl",
"prefetcher": null,
"system": "system",
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"tags": {
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"default_p_state": "UNDEFINED",
"clk_domain": "system.cpu_clk_domain",
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"path": "system.cpu.icache.tags",
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"type": "LRU",
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},
"clk_domain": "system.cpu_clk_domain",
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"default_p_state": "UNDEFINED",
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"mem_side": {
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"role": "MASTER"
},
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"addr_ranges": [
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],
"is_read_only": true,
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"path": "system.cpu.icache",
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|
