1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
|
---------- Begin Simulation Statistics ----------
sim_seconds 2.802895 # Number of seconds simulated
sim_ticks 2802894699500 # Number of ticks simulated
final_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 935329 # Simulator instruction rate (inst/s)
host_op_rate 1139685 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 17855077822 # Simulator tick rate (ticks/s)
host_mem_usage 572752 # Number of bytes of host memory used
host_seconds 156.98 # Real time elapsed on the host
sim_insts 146828240 # Number of instructions simulated
sim_ops 178908039 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 1118628 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 9439908 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 149524 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1084244 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 11793968 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 1118628 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 149524 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1268152 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8394176 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
system.physmem.bytes_written::total 8411740 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 25932 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 148018 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 2491 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 16962 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 193429 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 131159 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
system.physmem.num_writes::total 135550 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 399097 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 3367914 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 53346 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 386830 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 4207781 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 399097 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 53346 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 452444 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2994824 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3001090 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2994824 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 399097 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 3374166 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 53346 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 386844 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7208872 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.walks 7967 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 7967 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walkWaitTime::samples 7967 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 7967 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 7967 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 5082 77.32% 77.32% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M 1491 22.68% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 6573 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7967 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7967 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6573 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6573 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 14540 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 20339720 # DTB read hits
system.cpu0.dtb.read_misses 6874 # DTB read misses
system.cpu0.dtb.write_hits 16391078 # DTB write hits
system.cpu0.dtb.write_misses 1093 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 20346594 # DTB read accesses
system.cpu0.dtb.write_accesses 16392171 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 36730798 # DTB hits
system.cpu0.dtb.misses 7967 # DTB misses
system.cpu0.dtb.accesses 36738765 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.walks 3358 # Table walker walks requested
system.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 2040 87.11% 87.11% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M 302 12.89% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 2342 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3358 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 97439331 # ITB inst hits
system.cpu0.itb.inst_misses 3358 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 97442689 # ITB inst accesses
system.cpu0.itb.hits 97439331 # DTB hits
system.cpu0.itb.misses 3358 # DTB misses
system.cpu0.itb.accesses 97442689 # DTB accesses
system.cpu0.numCycles 5605791368 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 95426926 # Number of instructions committed
system.cpu0.committedOps 115560427 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 100762696 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses
system.cpu0.num_func_calls 8000180 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 13204202 # number of instructions that are conditional controls
system.cpu0.num_int_insts 100762696 # number of integer instructions
system.cpu0.num_fp_insts 9755 # number of float instructions
system.cpu0.num_int_register_reads 182457229 # number of times the integer registers were read
system.cpu0.num_int_register_writes 69135541 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 349971383 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 44907438 # number of times the CC registers were written
system.cpu0.num_mem_refs 37873810 # number of memory refs
system.cpu0.num_load_insts 20597310 # Number of load instructions
system.cpu0.num_store_insts 17276500 # Number of store instructions
system.cpu0.num_idle_cycles 5488206876.247207 # Number of idle cycles
system.cpu0.num_busy_cycles 117584491.752793 # Number of busy cycles
system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles
system.cpu0.Branches 21941499 # Number of branches fetched
system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu 78887256 67.49% 67.49% # Class of executed instruction
system.cpu0.op_class::IntMult 110639 0.09% 67.59% # Class of executed instruction
system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction
system.cpu0.op_class::MemRead 20597310 17.62% 85.22% # Class of executed instruction
system.cpu0.op_class::MemWrite 17276500 14.78% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 116882065 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 1968 # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements 693486 # number of replacements
system.cpu0.dcache.tags.tagsinuse 494.853665 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 35932410 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 693998 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 51.775956 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853665 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 74113887 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 74113887 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 19108541 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 19108541 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 15690414 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 15690414 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346093 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 346093 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379629 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 379629 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363041 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 363041 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 34798955 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 34798955 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 35145048 # number of overall hits
system.cpu0.dcache.overall_hits::total 35145048 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 373103 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 373103 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 295771 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 295771 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18444 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 18444 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 668874 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 668874 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 769195 # number of overall misses
system.cpu0.dcache.overall_misses::total 769195 # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481644 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 19481644 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986185 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 15986185 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446414 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 446414 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386371 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 386371 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381485 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 381485 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 35467829 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 35467829 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 35914243 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 35914243 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019152 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.019152 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018502 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.018502 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224726 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224726 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017450 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017450 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048348 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048348 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018859 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.018859 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021418 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.021418 # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 511485 # number of writebacks
system.cpu0.dcache.writebacks::total 511485 # number of writebacks
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 1109735 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.809992 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 96331417 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 1110247 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 86.765753 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809992 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 195993602 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 195993602 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 96331417 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 96331417 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 96331417 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 96331417 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 96331417 # number of overall hits
system.cpu0.icache.overall_hits::total 96331417 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 1110256 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 1110256 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 1110256 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 1110256 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 1110256 # number of overall misses
system.cpu0.icache.overall_misses::total 1110256 # number of overall misses
system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441673 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 97441673 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 97441673 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 97441673 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 97441673 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 97441673 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011394 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.011394 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011394 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.011394 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011394 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.011394 # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements 252829 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16127.674334 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 1809277 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 269026 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 6.725287 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 1764261500 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 8127.481443 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.302152 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.089300 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4685.625756 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3313.175683 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.496062 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000079 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.285988 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.202220 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.984355 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16189 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5612 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7505 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2706 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.988098 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 39447877 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 39447877 # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7572 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3251 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1065262 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data 351770 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 1427855 # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks 511485 # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total 511485 # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total 17 # number of UpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94095 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 94095 # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7572 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3251 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 1065262 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 445865 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 1521950 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7572 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3251 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 1065262 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 445865 # number of overall hits
system.cpu0.l2cache.overall_hits::total 1521950 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 216 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 137 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst 44994 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.data 128396 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 173743 # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26231 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 26231 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18444 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 18444 # number of SCUpgradeReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175428 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 175428 # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 216 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 137 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 44994 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 303824 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 349171 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 216 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 137 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 44994 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 303824 # number of overall misses
system.cpu0.l2cache.overall_misses::total 349171 # number of overall misses
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7788 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3388 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1110256 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480166 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 1601598 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks 511485 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total 511485 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26248 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 26248 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18444 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 18444 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269523 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 269523 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7788 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3388 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 1110256 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data 749689 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total 1871121 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7788 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3388 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 1110256 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data 749689 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total 1871121 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.027735 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.040437 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040526 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.267399 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.108481 # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999352 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999352 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650883 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650883 # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.027735 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.040437 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040526 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.405267 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.186611 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.027735 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.040437 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040526 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.405267 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.186611 # miss rate for overall accesses
system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks 193152 # number of writebacks
system.cpu0.l2cache.writebacks::total 193152 # number of writebacks
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq 1651838 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 1651838 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback 511485 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 26248 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18444 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 44692 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 269523 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 269523 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238556 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220081 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 4500273 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092472 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80905668 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 152081412 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 327909 # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples 2731172 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 1.090112 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.286342 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 2485061 90.99% 90.99% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 246111 9.01% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total 2731172 # Request fanout histogram
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.walks 3358 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 3358 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walksPending::samples -1804206736 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 -1804206736 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total -1804206736 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 1919 74.15% 74.15% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M 669 25.85% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 2588 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3358 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2588 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 5946 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 12173916 # DTB read hits
system.cpu1.dtb.read_misses 2852 # DTB read misses
system.cpu1.dtb.write_hits 7587209 # DTB write hits
system.cpu1.dtb.write_misses 506 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 12176768 # DTB read accesses
system.cpu1.dtb.write_accesses 7587715 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 19761125 # DTB hits
system.cpu1.dtb.misses 3358 # DTB misses
system.cpu1.dtb.accesses 19764483 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.walks 1734 # Table walker walks requested
system.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walksPending::samples -1804209236 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 -1804209236 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total -1804209236 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 935 85.39% 85.39% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M 160 14.61% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 1095 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1734 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1734 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 53671575 # ITB inst hits
system.cpu1.itb.inst_misses 1734 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 1136 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 53673309 # ITB inst accesses
system.cpu1.itb.hits 53671575 # DTB hits
system.cpu1.itb.misses 1734 # DTB misses
system.cpu1.itb.accesses 53673309 # DTB accesses
system.cpu1.numCycles 5605320274 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 51401314 # Number of instructions committed
system.cpu1.committedOps 63347612 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 56984241 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses
system.cpu1.num_func_calls 9170855 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 5967100 # number of instructions that are conditional controls
system.cpu1.num_int_insts 56984241 # number of integer instructions
system.cpu1.num_fp_insts 1792 # number of float instructions
system.cpu1.num_int_register_reads 110674739 # number of times the integer registers were read
system.cpu1.num_int_register_writes 41298353 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 196268655 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 18894365 # number of times the CC registers were written
system.cpu1.num_mem_refs 20026381 # number of memory refs
system.cpu1.num_load_insts 12289537 # Number of load instructions
system.cpu1.num_store_insts 7736844 # Number of store instructions
system.cpu1.num_idle_cycles 5539706759.565366 # Number of idle cycles
system.cpu1.num_busy_cycles 65613514.434634 # Number of busy cycles
system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles
system.cpu1.Branches 15217493 # Number of branches fetched
system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu 45401310 69.36% 69.36% # Class of executed instruction
system.cpu1.op_class::IntMult 28388 0.04% 69.40% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::MemRead 12289537 18.77% 88.18% # Class of executed instruction
system.cpu1.op_class::MemWrite 7736844 11.82% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 65459464 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed
system.cpu1.dcache.tags.replacements 191938 # number of replacements
system.cpu1.dcache.tags.tagsinuse 472.735415 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 19503509 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 192292 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 101.426523 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.735415 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923311 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.923311 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 39751979 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 39751979 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 11858694 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 11858694 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 7397479 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 7397479 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50099 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 50099 # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72442 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 72442 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 19256173 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 19256173 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 19306272 # number of overall hits
system.cpu1.dcache.overall_hits::total 19306272 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 136630 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 136630 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 92483 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 92483 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30719 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 30719 # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22537 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 22537 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 229113 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 229113 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 259832 # number of overall misses
system.cpu1.dcache.overall_misses::total 259832 # number of overall misses
system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995324 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 11995324 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489962 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 7489962 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 19485286 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 19485286 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 19566104 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 19566104 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011390 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.011390 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012348 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.012348 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380101 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380101 # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237284 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237284 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013280 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.013280 # miss rate for overall accesses
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 120843 # number of writebacks
system.cpu1.dcache.writebacks::total 120843 # number of writebacks
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements 523373 # number of replacements
system.cpu1.icache.tags.tagsinuse 499.711129 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 53148780 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 523885 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 101.451235 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711129 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 107869215 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 107869215 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 53148780 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 53148780 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 53148780 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 53148780 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 53148780 # number of overall hits
system.cpu1.icache.overall_hits::total 53148780 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 523885 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 523885 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 523885 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 523885 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 523885 # number of overall misses
system.cpu1.icache.overall_misses::total 523885 # number of overall misses
system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672665 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 53672665 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 53672665 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 53672665 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 53672665 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 53672665 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.009761 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009761 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.009761 # miss rate for overall accesses
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements 48543 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 15314.912528 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 717091 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 63380 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 11.314153 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 8302.426392 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.123905 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.034953 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3306.071742 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3701.255535 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.506740 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000191 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.201787 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.225907 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.934748 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 29 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14808 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 531 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9377 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4900 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001770 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903809 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 15213000 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 15213000 # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3125 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1708 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst 510060 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data 99394 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 614287 # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks 120843 # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total 120843 # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19811 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 19811 # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3125 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1708 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 510060 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 119205 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 634098 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3125 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1708 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 510060 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 119205 # number of overall hits
system.cpu1.l2cache.overall_hits::total 634098 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 344 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 267 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13825 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data 73273 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 87709 # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28859 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 28859 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22537 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 22537 # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43805 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 43805 # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 344 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 267 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 13825 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 117078 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 131514 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 344 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 267 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 13825 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 117078 # number of overall misses
system.cpu1.l2cache.overall_misses::total 131514 # number of overall misses
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3469 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1975 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523885 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data 172667 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 701996 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks 120843 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total 120843 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28867 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 28867 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22537 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 22537 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63616 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 63616 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3469 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1975 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 523885 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 236283 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 765612 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3469 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1975 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 523885 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 236283 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 765612 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.099164 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.135190 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026389 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424360 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.124942 # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999723 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999723 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688585 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688585 # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.099164 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.135190 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026389 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495499 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.171776 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.099164 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.135190 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026389 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495499 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.171776 # miss rate for overall accesses
system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks 32966 # number of writebacks
system.cpu1.l2cache.writebacks::total 32966 # number of writebacks
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq 709301 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback 120843 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 28867 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22537 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 51404 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1048124 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707677 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 1774495 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33529348 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22875246 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 56441982 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 568922 # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples 1446930 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 1.351508 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.477442 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 938322 64.85% 64.85% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 508608 35.15% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total 1446930 # Request fanout histogram
system.iobus.trans_dist::ReadReq 30995 # Transaction distribution
system.iobus.trans_dist::ReadResp 30995 # Transaction distribution
system.iobus.trans_dist::WriteReq 59419 # Transaction distribution
system.iobus.trans_dist::WriteResp 23195 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 107876 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 180828 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71526 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes)
system.iocache.tags.replacements 36442 # number of replacements
system.iocache.tags.tagsinuse 14.586092 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 14.586092 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.911631 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.911631 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328284 # Number of tag accesses
system.iocache.tags.data_accesses 328284 # Number of data accesses
system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses
system.iocache.demand_misses::total 252 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 252 # number of overall misses
system.iocache.overall_misses::total 252 # number of overall misses
system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 107655 # number of replacements
system.l2c.tags.tagsinuse 62149.484460 # Cycle average of tags in use
system.l2c.tags.total_refs 208536 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 168097 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 1.240569 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 48591.950970 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.942995 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030795 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 7375.890834 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 3824.198641 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.861600 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 1621.181926 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 731.426698 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.741454 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.112547 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.058353 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000013 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.024737 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.011161 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.948326 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 60436 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 70 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 1845 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 13049 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 45441 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.922180 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 4909092 # Number of tag accesses
system.l2c.tags.data_accesses 4909092 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 79 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 78 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 28077 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 76273 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 42 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 36 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 11499 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 11319 # number of ReadReq hits
system.l2c.ReadReq_hits::total 127403 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 226118 # number of Writeback hits
system.l2c.Writeback_hits::total 226118 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 498 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 64 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 562 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 63 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 12 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 75 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 14019 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 3098 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 17117 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 79 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 78 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 28077 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 90292 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 42 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 36 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 11499 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 14417 # number of demand (read+write) hits
system.l2c.demand_hits::total 144520 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 79 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 78 # number of overall hits
system.l2c.overall_hits::cpu0.inst 28077 # number of overall hits
system.l2c.overall_hits::cpu0.data 90292 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 42 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 36 # number of overall hits
system.l2c.overall_hits::cpu1.inst 11499 # number of overall hits
system.l2c.overall_hits::cpu1.data 14417 # number of overall hits
system.l2c.overall_hits::total 144520 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 16917 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 11327 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 2326 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 1158 # number of ReadReq misses
system.l2c.ReadReq_misses::total 31739 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 10006 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 3273 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 13279 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 754 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 1176 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1930 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 136759 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 15819 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 152578 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 16917 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 148086 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 2326 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 16977 # number of demand (read+write) misses
system.l2c.demand_misses::total 184317 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
system.l2c.overall_misses::cpu0.inst 16917 # number of overall misses
system.l2c.overall_misses::cpu0.data 148086 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu1.inst 2326 # number of overall misses
system.l2c.overall_misses::cpu1.data 16977 # number of overall misses
system.l2c.overall_misses::total 184317 # number of overall misses
system.l2c.ReadReq_accesses::cpu0.dtb.walker 87 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 80 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 44994 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 87600 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 43 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 36 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 13825 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 12477 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 159142 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 226118 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 226118 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 10504 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 3337 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 13841 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 817 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 1188 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 2005 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 150778 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 18917 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 169695 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 87 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 80 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 44994 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 238378 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 43 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 36 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 13825 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 31394 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 328837 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 87 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 80 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 44994 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 238378 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 43 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 36 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 13825 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 31394 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 328837 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.025000 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.375983 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.129304 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.168246 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.092811 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.199438 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.952589 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980821 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.959396 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.922889 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.989899 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.962594 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.907022 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.836232 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.899131 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.025000 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.375983 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.621223 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.168246 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.540772 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.560512 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.025000 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.375983 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.621223 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.168246 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.540772 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.560512 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 94969 # number of writebacks
system.l2c.writebacks::total 94969 # number of writebacks
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 75988 # Transaction distribution
system.membus.trans_dist::ReadResp 75988 # Transaction distribution
system.membus.trans_dist::WriteReq 30846 # Transaction distribution
system.membus.trans_dist::WriteResp 30846 # Transaction distribution
system.membus.trans_dist::Writeback 131159 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
system.membus.trans_dist::UpgradeReq 60361 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 40906 # Transaction distribution
system.membus.trans_dist::UpgradeResp 15595 # Transaction distribution
system.membus.trans_dist::ReadExReq 196283 # Transaction distribution
system.membus.trans_dist::ReadExResp 152192 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652086 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 773470 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109142 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 109142 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 882612 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17906316 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 18096098 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4650624 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 4650624 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 22746722 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 571767 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 571767 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 571767 # Request fanout histogram
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.toL2Bus.trans_dist::ReadReq 305452 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 305452 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 226118 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 60537 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 40981 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 101518 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 213786 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 213786 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1118722 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410600 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 1529322 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34707388 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10425906 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 45133294 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 36713 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 914196 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.039900 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.195723 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 877720 96.01% 96.01% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 36476 3.99% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 914196 # Request fanout histogram
---------- End Simulation Statistics ----------
|