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|
---------- Begin Simulation Statistics ----------
sim_seconds 2.802882 # Number of seconds simulated
sim_ticks 2802882496500 # Number of ticks simulated
final_tick 2802882496500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1330236 # Simulator instruction rate (inst/s)
host_op_rate 1620871 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 25395755903 # Simulator tick rate (ticks/s)
host_mem_usage 564312 # Number of bytes of host memory used
host_seconds 110.37 # Real time elapsed on the host
sim_insts 146815698 # Number of instructions simulated
sim_ops 178892459 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.realview.nvmem.bytes_read::cpu0.inst 24 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 52 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 76 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 24 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 52 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 76 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 6 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 19 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 27 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 19 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 19 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 27 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 1117476 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 9458684 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 149780 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1082912 # Number of bytes read from this memory
system.physmem.bytes_read::total 11810580 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 1117476 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 149780 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1267256 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 6081216 # Number of bytes written to this memory
system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
system.physmem.bytes_written::total 8417296 # Number of bytes written to this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 25914 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 148317 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 2495 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 16944 # Number of read requests responded to by this memory
system.physmem.num_reads::total 193697 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 95019 # Number of write requests responded to by this memory
system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
system.physmem.num_writes::total 135679 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 398688 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 3374627 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 53438 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 386357 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 4213726 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 398688 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 53438 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 452126 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2169629 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::realview.ide 827126 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6316 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3003086 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2169629 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 827468 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 398688 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 3380944 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 53438 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 386371 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7216812 # Total bandwidth to/from this memory (bytes/s)
system.membus.trans_dist::ReadReq 75963 # Transaction distribution
system.membus.trans_dist::ReadResp 75963 # Transaction distribution
system.membus.trans_dist::WriteReq 30903 # Transaction distribution
system.membus.trans_dist::WriteResp 30903 # Transaction distribution
system.membus.trans_dist::Writeback 95019 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
system.membus.trans_dist::UpgradeReq 60332 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 40886 # Transaction distribution
system.membus.trans_dist::UpgradeResp 15607 # Transaction distribution
system.membus.trans_dist::ReadExReq 196321 # Transaction distribution
system.membus.trans_dist::ReadExResp 152216 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13468 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652185 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 773609 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72952 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 72952 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 846561 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162808 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 76 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26936 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17908580 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 18098400 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2334464 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2334464 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 20432864 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 460731 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 460731 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 460731 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.l2c.tags.replacements 107723 # number of replacements
system.l2c.tags.tagsinuse 62123.921751 # Cycle average of tags in use
system.l2c.tags.total_refs 208051 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 168144 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 1.237338 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 48622.171138 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.975943 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030392 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 7348.709599 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 3778.182164 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.823425 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 1628.255131 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 741.773959 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.741915 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.112132 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.057650 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000028 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.024845 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.011319 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.947936 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 60415 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 1884 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 13069 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 45357 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.921860 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 4905185 # Number of tag accesses
system.l2c.tags.data_accesses 4905185 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 79 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 74 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 28057 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 75985 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 42 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 33 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 11512 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 11347 # number of ReadReq hits
system.l2c.ReadReq_hits::total 127129 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 225966 # number of Writeback hits
system.l2c.Writeback_hits::total 225966 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 512 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 65 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 577 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 56 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 11 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 67 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 13971 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 3083 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 17054 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 79 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 74 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 28057 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 89956 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 42 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 33 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 11512 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 14430 # number of demand (read+write) hits
system.l2c.demand_hits::total 144183 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 79 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 74 # number of overall hits
system.l2c.overall_hits::cpu0.inst 28057 # number of overall hits
system.l2c.overall_hits::cpu0.data 89956 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 42 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 33 # number of overall hits
system.l2c.overall_hits::cpu1.inst 11512 # number of overall hits
system.l2c.overall_hits::cpu1.data 14430 # number of overall hits
system.l2c.overall_hits::total 144183 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 16897 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 11316 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 2330 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 1142 # number of ReadReq misses
system.l2c.ReadReq_misses::total 31697 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 9967 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 3302 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 13269 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 763 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 1181 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1944 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 136796 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 15814 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 152610 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 16897 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 148112 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 2330 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 16956 # number of demand (read+write) misses
system.l2c.demand_misses::total 184307 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
system.l2c.overall_misses::cpu0.inst 16897 # number of overall misses
system.l2c.overall_misses::cpu0.data 148112 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses
system.l2c.overall_misses::cpu1.inst 2330 # number of overall misses
system.l2c.overall_misses::cpu1.data 16956 # number of overall misses
system.l2c.overall_misses::total 184307 # number of overall misses
system.l2c.ReadReq_accesses::cpu0.dtb.walker 87 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 76 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 44954 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 87301 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 44 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 33 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 13842 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 12489 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 158826 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 225966 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 225966 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 10479 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 3367 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 13846 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 819 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 1192 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 2011 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 150767 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 18897 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 169664 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 87 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 76 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 44954 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 238068 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 44 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 33 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 13842 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 31386 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 328490 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 87 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 76 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 44954 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 238068 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 44 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 33 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 13842 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 31386 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 328490 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.026316 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.375873 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.129621 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.168328 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.091440 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.199571 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951140 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980695 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.958327 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.931624 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.990772 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.966683 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.907334 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.836852 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.899484 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.026316 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.375873 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.622142 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.168328 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.540241 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.561073 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.026316 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.375873 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.622142 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.168328 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.540241 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.561073 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 95019 # number of writebacks
system.l2c.writebacks::total 95019 # number of writebacks
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.toL2Bus.trans_dist::ReadReq 305028 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 305028 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 30903 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 30903 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 225966 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 60515 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 40953 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 101468 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 213769 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 213769 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117772 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410530 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 1528302 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34667382 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10427306 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 45094688 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 36713 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 838693 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.043491 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.203961 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 802217 95.65% 95.65% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 36476 4.35% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 838693 # Request fanout histogram
system.iobus.trans_dist::ReadReq 31002 # Transaction distribution
system.iobus.trans_dist::ReadResp 31002 # Transaction distribution
system.iobus.trans_dist::WriteReq 59433 # Transaction distribution
system.iobus.trans_dist::WriteResp 23209 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56624 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 180870 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71568 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 162808 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 20338466 # DTB read hits
system.cpu0.dtb.read_misses 6871 # DTB read misses
system.cpu0.dtb.write_hits 16389914 # DTB write hits
system.cpu0.dtb.write_misses 1093 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 20345337 # DTB read accesses
system.cpu0.dtb.write_accesses 16391007 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 36728380 # DTB hits
system.cpu0.dtb.misses 7964 # DTB misses
system.cpu0.dtb.accesses 36736344 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.inst_hits 97433991 # ITB inst hits
system.cpu0.itb.inst_misses 3358 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 97437349 # ITB inst accesses
system.cpu0.itb.hits 97433991 # DTB hits
system.cpu0.itb.misses 3358 # DTB misses
system.cpu0.itb.accesses 97437349 # DTB accesses
system.cpu0.numCycles 5605766965 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 95421538 # Number of instructions committed
system.cpu0.committedOps 115553717 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 100756647 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses
system.cpu0.num_func_calls 7999979 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 13203645 # number of instructions that are conditional controls
system.cpu0.num_int_insts 100756647 # number of integer instructions
system.cpu0.num_fp_insts 9755 # number of float instructions
system.cpu0.num_int_register_reads 182446507 # number of times the integer registers were read
system.cpu0.num_int_register_writes 69131058 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 349951369 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 44905035 # number of times the CC registers were written
system.cpu0.num_mem_refs 37871263 # number of memory refs
system.cpu0.num_load_insts 20596038 # Number of load instructions
system.cpu0.num_store_insts 17275225 # Number of store instructions
system.cpu0.num_idle_cycles 5488189135.402444 # Number of idle cycles
system.cpu0.num_busy_cycles 117577829.597556 # Number of busy cycles
system.cpu0.not_idle_fraction 0.020974 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.979026 # Percentage of idle cycles
system.cpu0.Branches 21940727 # Number of branches fetched
system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu 78883166 67.49% 67.50% # Class of executed instruction
system.cpu0.op_class::IntMult 110618 0.09% 67.59% # Class of executed instruction
system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction
system.cpu0.op_class::MemRead 20596038 17.62% 85.22% # Class of executed instruction
system.cpu0.op_class::MemWrite 17275225 14.78% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 116875407 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 1971 # number of quiesce instructions executed
system.cpu0.icache.tags.replacements 1109428 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 96326384 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 1109940 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 86.785217 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 6345717500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 195982615 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 195982615 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 96326384 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 96326384 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 96326384 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 96326384 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 96326384 # number of overall hits
system.cpu0.icache.overall_hits::total 96326384 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 1109949 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 1109949 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 1109949 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 1109949 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 1109949 # number of overall misses
system.cpu0.icache.overall_misses::total 1109949 # number of overall misses
system.cpu0.icache.ReadReq_accesses::cpu0.inst 97436333 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 97436333 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 97436333 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 97436333 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 97436333 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 97436333 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011392 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.011392 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011392 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.011392 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011392 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.011392 # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu0.l2cache.tags.replacements 252470 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16140.899010 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 1809063 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 268660 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 6.733652 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 1814551000 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 8130.897895 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.403919 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.095149 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4678.277611 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3330.224436 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.496271 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000086 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.285539 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.203261 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.985162 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16181 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 280 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5558 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7600 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2662 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.987610 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 39435786 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 39435786 # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7516 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3210 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1064995 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data 352145 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 1427866 # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks 511188 # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total 511188 # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total 17 # number of UpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94088 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 94088 # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7516 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3210 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 1064995 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 446233 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 1521954 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7516 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3210 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 1064995 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 446233 # number of overall hits
system.cpu0.l2cache.overall_hits::total 1521954 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 216 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 135 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst 44954 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.data 128031 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 173336 # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26217 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 26217 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18426 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 18426 # number of SCUpgradeReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175429 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 175429 # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 216 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 135 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 44954 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 303460 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 348765 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 216 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 135 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 44954 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 303460 # number of overall misses
system.cpu0.l2cache.overall_misses::total 348765 # number of overall misses
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7732 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3345 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1109949 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480176 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 1601202 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks 511188 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total 511188 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26234 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 26234 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18426 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 18426 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269517 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 269517 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7732 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3345 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 1109949 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data 749693 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total 1870719 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7732 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3345 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 1109949 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data 749693 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total 1870719 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.027936 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.040359 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040501 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266633 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.108254 # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999352 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999352 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650901 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650901 # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.027936 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.040359 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040501 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404779 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.186434 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.027936 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.040359 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040501 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404779 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.186434 # miss rate for overall accesses
system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks 192932 # number of writebacks
system.cpu0.l2cache.writebacks::total 192932 # number of writebacks
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 693475 # number of replacements
system.cpu0.dcache.tags.tagsinuse 494.745909 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 35929913 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 693987 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 51.773179 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 23662000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.745909 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966301 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.966301 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 74108905 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 74108905 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 19107323 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 19107323 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 15689235 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 15689235 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346054 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 346054 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379605 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 379605 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363036 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 363036 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 34796558 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 34796558 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 35142612 # number of overall hits
system.cpu0.dcache.overall_hits::total 35142612 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 373110 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 373110 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 295751 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 295751 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100324 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 100324 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18426 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 18426 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 668861 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 668861 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 769185 # number of overall misses
system.cpu0.dcache.overall_misses::total 769185 # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data 19480433 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 19480433 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 15984986 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 15984986 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446378 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 446378 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386347 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 386347 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381462 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 381462 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 35465419 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 35465419 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 35911797 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 35911797 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019153 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.019153 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018502 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.018502 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224751 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224751 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017451 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017451 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048304 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048304 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018860 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.018860 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021419 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.021419 # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 511188 # number of writebacks
system.cpu0.dcache.writebacks::total 511188 # number of writebacks
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq 1651550 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 1651550 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 28399 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 28399 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback 511188 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 26234 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18426 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 44660 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 269517 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 269517 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2237944 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2219872 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 4499440 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71072828 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80887162 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 152043238 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 321922 # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples 2655621 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 5.082587 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.275257 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::5 2436302 91.74% 91.74% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::6 219319 8.26% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total 2655621 # Request fanout histogram
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 12172110 # DTB read hits
system.cpu1.dtb.read_misses 2853 # DTB read misses
system.cpu1.dtb.write_hits 7585805 # DTB write hits
system.cpu1.dtb.write_misses 506 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 12174963 # DTB read accesses
system.cpu1.dtb.write_accesses 7586311 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 19757915 # DTB hits
system.cpu1.dtb.misses 3359 # DTB misses
system.cpu1.dtb.accesses 19761274 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.inst_hits 53664371 # ITB inst hits
system.cpu1.itb.inst_misses 1734 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 1136 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 53666105 # ITB inst accesses
system.cpu1.itb.hits 53664371 # DTB hits
system.cpu1.itb.misses 1734 # DTB misses
system.cpu1.itb.accesses 53666105 # DTB accesses
system.cpu1.numCycles 5605295863 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 51394160 # Number of instructions committed
system.cpu1.committedOps 63338742 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 56976202 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses
system.cpu1.num_func_calls 9170283 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 5966381 # number of instructions that are conditional controls
system.cpu1.num_int_insts 56976202 # number of integer instructions
system.cpu1.num_fp_insts 1792 # number of float instructions
system.cpu1.num_int_register_reads 110660301 # number of times the integer registers were read
system.cpu1.num_int_register_writes 41292600 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 196241872 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 18891627 # number of times the CC registers were written
system.cpu1.num_mem_refs 20022980 # number of memory refs
system.cpu1.num_load_insts 12287666 # Number of load instructions
system.cpu1.num_store_insts 7735314 # Number of store instructions
system.cpu1.num_idle_cycles 5539691262.121797 # Number of idle cycles
system.cpu1.num_busy_cycles 65604600.878203 # Number of busy cycles
system.cpu1.not_idle_fraction 0.011704 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.988296 # Percentage of idle cycles
system.cpu1.Branches 15216192 # Number of branches fetched
system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu 45395839 69.36% 69.36% # Class of executed instruction
system.cpu1.op_class::IntMult 28345 0.04% 69.40% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 3315 0.01% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::MemRead 12287666 18.77% 88.18% # Class of executed instruction
system.cpu1.op_class::MemWrite 7735314 11.82% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 65450545 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 2734 # number of quiesce instructions executed
system.cpu1.icache.tags.replacements 523179 # number of replacements
system.cpu1.icache.tags.tagsinuse 499.711075 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 53141770 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 523691 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 101.475431 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 76931405000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711075 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 107854613 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 107854613 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 53141770 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 53141770 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 53141770 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 53141770 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 53141770 # number of overall hits
system.cpu1.icache.overall_hits::total 53141770 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 523691 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 523691 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 523691 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 523691 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 523691 # number of overall misses
system.cpu1.icache.overall_misses::total 523691 # number of overall misses
system.cpu1.icache.ReadReq_accesses::cpu1.inst 53665461 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 53665461 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 53665461 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 53665461 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 53665461 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 53665461 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009758 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.009758 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009758 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.009758 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009758 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.009758 # miss rate for overall accesses
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.l2cache.tags.replacements 48552 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 15311.760536 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 716558 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 63379 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 11.305922 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 8243.045220 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.958358 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.015688 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3303.816337 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3759.924934 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.503116 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000181 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.201649 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.229488 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.934556 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 18 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14809 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 540 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9336 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4933 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903870 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 15206583 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 15206583 # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3143 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1725 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst 509849 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data 99406 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 614123 # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks 120669 # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total 120669 # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19820 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 19820 # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3143 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1725 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 509849 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 119226 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 633943 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3143 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1725 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 509849 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 119226 # number of overall hits
system.cpu1.l2cache.overall_hits::total 633943 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 348 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 271 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13842 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data 73217 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 87678 # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28845 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 28845 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22527 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 22527 # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43793 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 43793 # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 348 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 271 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 13842 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 117010 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 131471 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 348 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 271 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 13842 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 117010 # number of overall misses
system.cpu1.l2cache.overall_misses::total 131471 # number of overall misses
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3491 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1996 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523691 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data 172623 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 701801 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks 120669 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total 120669 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28853 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 28853 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22527 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 22527 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63613 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 63613 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3491 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1996 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 523691 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 236236 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 765414 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3491 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1996 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 523691 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 236236 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 765414 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.099685 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.135772 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026432 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424144 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.124933 # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999723 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999723 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688428 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688428 # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.099685 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.135772 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026432 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495310 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.171765 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.099685 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.135772 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026432 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495310 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.171765 # miss rate for overall accesses
system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks 33034 # number of writebacks
system.cpu1.l2cache.writebacks::total 33034 # number of writebacks
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements 191901 # number of replacements
system.cpu1.dcache.tags.tagsinuse 472.757627 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 19500351 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 192255 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 101.429617 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 105851562500 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.757627 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923355 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.923355 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 39745522 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 39745522 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 11856979 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 11856979 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 7396120 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 7396120 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50084 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 50084 # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91418 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 91418 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72426 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 72426 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 19253099 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 19253099 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 19303183 # number of overall hits
system.cpu1.dcache.overall_hits::total 19303183 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 136590 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 136590 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 92466 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 92466 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30716 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 30716 # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5317 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 5317 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22527 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 22527 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 229056 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 229056 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 259772 # number of overall misses
system.cpu1.dcache.overall_misses::total 259772 # number of overall misses
system.cpu1.dcache.ReadReq_accesses::cpu1.data 11993569 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 11993569 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 7488586 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 7488586 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80800 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 80800 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96735 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 96735 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94953 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 94953 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 19482155 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 19482155 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 19562955 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 19562955 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011389 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.011389 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012348 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.012348 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380149 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380149 # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054965 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054965 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237244 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237244 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 120669 # number of writebacks
system.cpu1.dcache.writebacks::total 120669 # number of writebacks
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq 709063 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 709063 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 2504 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 2504 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback 120669 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 28853 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22527 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 51380 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 63613 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 63613 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1047738 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707355 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 1773789 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33516936 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22861090 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 56415418 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 499577 # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples 1371208 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 5.313508 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.463919 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::5 941324 68.65% 68.65% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::6 429884 31.35% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total 1371208 # Request fanout histogram
system.iocache.tags.replacements 36442 # number of replacements
system.iocache.tags.tagsinuse 14.586086 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 246641119509 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 14.586086 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328284 # Number of tag accesses
system.iocache.tags.data_accesses 328284 # Number of data accesses
system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses
system.iocache.demand_misses::total 252 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 252 # number of overall misses
system.iocache.overall_misses::total 252 # number of overall misses
system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 36224 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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